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Beam Positoning Monitor - Gateware
Commit 38870233 authored by Lucas Russo's avatar Lucas Russo
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Merge branch 'fmcpico1m_4ch' into devel

parents 65222ba3 9101fb05
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Showing with 7015 additions and 176 deletions
dsp-cores @ 010af6aa
Subproject commit 2ddc9d03aa248af1fbb953bfa417b09891593a14
Subproject commit 010af6aa9b8bad4b820d3adca4b68a7809e53805
hdl/modules/dbe_wishbone/Manifest.py
View file @ 38870233
......@@ -10,6 +10,7 @@ modules = { "local" : [
"wb_fmc516",
"wb_fmc130m_4ch",
"wb_fmc250m_4ch",
"wb_fmcpico1m_4ch",
"wb_ethmac_adapter",
"wb_ethmac",
"wb_dbe_periph",
......
hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
View file @ 38870233
......@@ -1328,6 +1328,128 @@ package dbe_wishbone_pkg is
);
end component;
component wb_fmcpico1m_4ch
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false;
g_num_adc_bits : natural := 20;
g_num_adc_channels : natural := 4;
g_clk_freq : natural := 300000000; -- Hz
g_sclk_freq : natural := 75000000 --Hz
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
adc_fast_spi_clk_i : in std_logic;
adc_fast_spi_rstn_i : in std_logic;
-- Control signals
adc_start_i : in std_logic;
-- SPI bus
adc_sdo1_i : in std_logic;
adc_sdo2_i : in std_logic;
adc_sdo3_i : in std_logic;
adc_sdo4_i : in std_logic;
adc_sck_o : out std_logic;
adc_sck_rtrn_i : in std_logic;
adc_busy_cmn_i : in std_logic;
adc_cnv_out_o : out std_logic;
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
-- clock to CDC. This must be g_sclk_freq/g_num_adc_bits. A regular 100MHz should
-- suffice in all cases
adc_clk_i : in std_logic;
adc_data_o : out std_logic_vector(g_num_adc_channels*g_num_adc_bits-1 downto 0);
adc_data_valid_o : out std_logic_vector(g_num_adc_channels-1 downto 0);
adc_out_busy_o : out std_logic
);
end component;
component xwb_fmcpico1m_4ch
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false;
g_num_adc_bits : natural := 20;
g_num_adc_channels : natural := 4;
g_clk_freq : natural := 300000000; -- Hz
g_sclk_freq : natural := 75000000 --Hz
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
adc_fast_spi_clk_i : in std_logic;
adc_fast_spi_rstn_i : in std_logic;
-- Control signals
adc_start_i : in std_logic;
-- SPI bus
adc_sdo1_i : in std_logic;
adc_sdo2_i : in std_logic;
adc_sdo3_i : in std_logic;
adc_sdo4_i : in std_logic;
adc_sck_o : out std_logic;
adc_sck_rtrn_i : in std_logic;
adc_busy_cmn_i : in std_logic;
adc_cnv_out_o : out std_logic;
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
-- clock to CDC. This must be g_sclk_freq/g_num_adc_bits. A regular 100MHz should
-- suffice in all cases
adc_clk_i : in std_logic;
adc_data_o : out std_logic_vector(g_num_adc_channels*g_num_adc_bits-1 downto 0);
adc_data_valid_o : out std_logic_vector(g_num_adc_channels-1 downto 0);
adc_out_busy_o : out std_logic
);
end component;
component xwb_ethmac_adapter
port(
clk_i : in std_logic;
......@@ -3219,4 +3341,22 @@ package dbe_wishbone_pkg is
date => x"20160203",
name => "LNLS_TRIGGER_IFACE ")));
-- fmcpico_1m_4CH
constant c_xwb_fmcpico_1m_4ch_regs_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"669f7e38",
version => x"00000001",
date => x"20171603",
name => "LNLS_FMCPICO_REGS ")));
end dbe_wishbone_pkg;
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/Manifest.py 0 → 100644
View file @ 38870233
files = [
"cdc_fifo.vhd",
"fmc_pico_spi.v",
"wb_fmcpico1m_4ch.vhd",
"xwb_fmcpico1m_4ch.vhd",
"wbgen/wb_fmcpico1m_4ch_regs_pkg.vhd",
"wbgen/wb_fmcpico1m_4ch_regs.vhd"
];
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/cdc_fifo.vhd 0 → 100644
View file @ 38870233
------------------------------------------------------------------------------
-- Title : CDC FIFO for Position data
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-09-23
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: CDC FIFO for generic data. Suitable for CDC position data
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-09-23 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Genrams
use work.genram_pkg.all;
use work.dsp_cores_pkg.all;
entity cdc_fifo is
generic
(
g_data_width : natural;
g_size : natural
);
port
(
clk_wr_i : in std_logic;
data_i : in std_logic_vector(g_data_width-1 downto 0);
valid_i : in std_logic;
clk_rd_i : in std_logic;
data_o : out std_logic_vector(g_data_width-1 downto 0);
valid_o : out std_logic
);
end cdc_fifo;
architecture rtl of cdc_fifo is
constant c_guard_size : integer := 2;
constant c_almost_empty_thres : integer := c_guard_size;
constant c_almost_full_thres : integer := g_size - c_guard_size;
signal fifo_cdc_rd : std_logic;
signal fifo_cdc_empty : std_logic;
signal fifo_cdc_valid : std_logic;
begin
cmp_cdc_fifo : inferred_async_fifo
generic map(
g_data_width => g_data_width,
g_size => g_size,
g_almost_empty_threshold => c_almost_empty_thres,
g_almost_full_threshold => c_almost_full_thres
)
port map(
rst_n_i => '1',
-- write port
clk_wr_i => clk_wr_i,
d_i => data_i,
we_i => valid_i, -- and valid
wr_full_o => open,
-- read port
clk_rd_i => clk_rd_i,
q_o => data_o,
rd_i => fifo_cdc_rd,
rd_empty_o => fifo_cdc_empty
);
fifo_cdc_rd <= '1' when fifo_cdc_empty = '0' else '0';
p_gen_cdc_valid: process (clk_rd_i)
begin
if rising_edge (clk_rd_i) then
fifo_cdc_valid <= fifo_cdc_rd;
if fifo_cdc_empty = '1' then
fifo_cdc_valid <= '0';
end if;
end if;
end process;
valid_o <= fifo_cdc_valid;
end rtl;
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wb_fmcpico1m_4ch.vhd 0 → 100644
View file @ 38870233
This diff is collapsed.
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/build_wb.sh 0 → 100755
View file @ 38870233
#!/bin/bash
wbgen2 -V wb_fmcpico1m_4ch_regs.vhd -H record -p wb_fmcpico1m_4ch_regs_pkg.vhd -K ../../../../sim/regs/wb_fmcpico1m_4ch_regs.vh -s defines -C wb_fmcpico1m_4ch_regs.h -f html -D doc/fmcpico1m_4ch_regs_wb.html wb_fmcpico1m_4ch_regs.wb
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs.h 0 → 100644
View file @ 38870233
/*
Register definitions for slave core: Control and status registers for FMC PICO 1M 4CH
* File : wb_fmcpico1m_4ch_regs.h
* Author : auto-generated by wbgen2 from wb_fmcpico1m_4ch_regs.wb
* Created : Wed Mar 15 18:50:17 2017
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmcpico1m_4ch_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WB_FMCPICO1M_4CH_REGS_WB
#define __WBGEN2_REGDEFS_WB_FMCPICO1M_4CH_REGS_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: FMC Status */
/* definitions for field: FMC Present in reg: FMC Status */
#define WB_FMCPICO1M_4CH_CSR_FMC_STATUS_PRSNT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Power Good from mezzanine in reg: FMC Status */
#define WB_FMCPICO1M_4CH_CSR_FMC_STATUS_PG_M2C WBGEN2_GEN_MASK(1, 1)
/* definitions for register: FMC Control */
/* definitions for field: LED 1 Control in reg: FMC Control */
#define WB_FMCPICO1M_4CH_CSR_FMC_CTL_LED1 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: LED 2 Control in reg: FMC Control */
#define WB_FMCPICO1M_4CH_CSR_FMC_CTL_LED2 WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Input Range Control */
/* definitions for field: R0 in reg: Input Range Control */
#define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: R1 in reg: Input Range Control */
#define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R1 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: R2 in reg: Input Range Control */
#define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R2 WBGEN2_GEN_MASK(16, 1)
/* definitions for field: R3 in reg: Input Range Control */
#define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R3 WBGEN2_GEN_MASK(24, 1)
/* definitions for register: ADC Data Channel 0 */
/* definitions for field: DATA0 in reg: ADC Data Channel 0 */
#define WB_FMCPICO1M_4CH_CSR_DATA0_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMCPICO1M_4CH_CSR_DATA0_VAL_SHIFT 0
#define WB_FMCPICO1M_4CH_CSR_DATA0_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMCPICO1M_4CH_CSR_DATA0_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: ADC Data Channel 1 */
/* definitions for field: DATA1 in reg: ADC Data Channel 1 */
#define WB_FMCPICO1M_4CH_CSR_DATA1_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMCPICO1M_4CH_CSR_DATA1_VAL_SHIFT 0
#define WB_FMCPICO1M_4CH_CSR_DATA1_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMCPICO1M_4CH_CSR_DATA1_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: ADC Data Channel 2 */
/* definitions for field: DATA2 in reg: ADC Data Channel 2 */
#define WB_FMCPICO1M_4CH_CSR_DATA2_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMCPICO1M_4CH_CSR_DATA2_VAL_SHIFT 0
#define WB_FMCPICO1M_4CH_CSR_DATA2_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMCPICO1M_4CH_CSR_DATA2_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: ADC Data Channel 3 */
/* definitions for field: DATA3 in reg: ADC Data Channel 3 */
#define WB_FMCPICO1M_4CH_CSR_DATA3_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMCPICO1M_4CH_CSR_DATA3_VAL_SHIFT 0
#define WB_FMCPICO1M_4CH_CSR_DATA3_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMCPICO1M_4CH_CSR_DATA3_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* [0x0]: REG FMC Status */
#define WB_FMCPICO1M_4CH_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG FMC Control */
#define WB_FMCPICO1M_4CH_CSR_REG_FMC_CTL 0x00000004
/* [0x8]: REG Input Range Control */
#define WB_FMCPICO1M_4CH_CSR_REG_RNG_CTL 0x00000008
/* [0xc]: REG ADC Data Channel 0 */
#define WB_FMCPICO1M_4CH_CSR_REG_DATA0 0x0000000c
/* [0x10]: REG ADC Data Channel 1 */
#define WB_FMCPICO1M_4CH_CSR_REG_DATA1 0x00000010
/* [0x14]: REG ADC Data Channel 2 */
#define WB_FMCPICO1M_4CH_CSR_REG_DATA2 0x00000014
/* [0x18]: REG ADC Data Channel 3 */
#define WB_FMCPICO1M_4CH_CSR_REG_DATA3 0x00000018
#endif
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs.wb 0 → 100644
View file @ 38870233
peripheral {
name = "Control and status registers for FMC PICO 1M 4CH";
description = "Wishbone slave for control and status registers related to FMC PICO 1M 4CH with access from CSR bus";
hdl_entity = "wb_fmcpico1m_4ch_csr";
prefix = "wb_fmcpico1m_4ch_csr";
reg {
name = "FMC Status";
prefix = "fmc_status";
field {
name = "FMC Present";
prefix = "prsnt";
description = "FMC PRSNT_M2C Pin\n0 - FMC card present\n1 - no FMC card on carrier";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Power Good from mezzanine";
prefix = "pg_m2c";
description = "FMC Power Good Pin\nNot used";
type = BIT;
--size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "FMC Control";
prefix = "fmc_ctl";
field {
name = "LED 1 Control";
prefix = "led1";
description = "0 - Led Off\n1 - Led On";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "LED 2 Control";
prefix = "led2";
description = "0 - Led Off\n1 - Led On";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Input Range Control";
prefix = "rng_ctl";
field {
name = "R0";
prefix = "r0";
description = "Input Range Control for ADC0\n0 - RNG1 = +/- 1uA\n1 - RNG0 = +/- 1mA";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "R1";
prefix = "r1";
description = "Input Range Control for ADC1\n0 - RNG1 = +/- 1uA\n1 - RNG0 = +/- 1mA";
align = 8;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "R2";
prefix = "r2";
description = "Input Range Control for ADC2\n0 - RNG1 = +/- 1uA\n1 - RNG0 = +/- 1mA";
align = 16;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "R3";
prefix = "r3";
description = "Input Range Control for ADC3\n0 - RNG1 = +/- 1uA\n1 - RNG0 = +/- 1mA";
align = 24;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "ADC Data Channel 0";
prefix = "data0";
field {
name = "DATA0";
prefix = "val";
description = "ADC data from channel 0";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Data Channel 1";
prefix = "data1";
field {
name = "DATA1";
prefix = "val";
description = "ADC data from channel 1";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Data Channel 2";
prefix = "data2";
field {
name = "DATA2";
prefix = "val";
description = "ADC data from channel 2";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Data Channel 3";
prefix = "data3";
field {
name = "DATA3";
prefix = "val";
description = "ADC data from channel 3";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs_pkg.vhd 0 → 100644
View file @ 38870233
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Control and status registers for FMC PICO 1M 4CH
---------------------------------------------------------------------------------------
-- File : wb_fmcpico1m_4ch_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from wb_fmcpico1m_4ch_regs.wb
-- Created : Wed Mar 15 18:50:17 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmcpico1m_4ch_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wb_fmcpico1m_4ch_csr_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_wb_fmcpico1m_4ch_csr_in_registers is record
fmc_status_prsnt_i : std_logic;
fmc_status_pg_m2c_i : std_logic;
data0_val_i : std_logic_vector(31 downto 0);
data1_val_i : std_logic_vector(31 downto 0);
data2_val_i : std_logic_vector(31 downto 0);
data3_val_i : std_logic_vector(31 downto 0);
end record;
constant c_wb_fmcpico1m_4ch_csr_in_registers_init_value: t_wb_fmcpico1m_4ch_csr_in_registers := (
fmc_status_prsnt_i => '0',
fmc_status_pg_m2c_i => '0',
data0_val_i => (others => '0'),
data1_val_i => (others => '0'),
data2_val_i => (others => '0'),
data3_val_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_wb_fmcpico1m_4ch_csr_out_registers is record
fmc_ctl_led1_o : std_logic;
fmc_ctl_led2_o : std_logic;
rng_ctl_r0_o : std_logic;
rng_ctl_r1_o : std_logic;
rng_ctl_r2_o : std_logic;
rng_ctl_r3_o : std_logic;
end record;
constant c_wb_fmcpico1m_4ch_csr_out_registers_init_value: t_wb_fmcpico1m_4ch_csr_out_registers := (
fmc_ctl_led1_o => '0',
fmc_ctl_led2_o => '0',
rng_ctl_r0_o => '0',
rng_ctl_r1_o => '0',
rng_ctl_r2_o => '0',
rng_ctl_r3_o => '0'
);
function "or" (left, right: t_wb_fmcpico1m_4ch_csr_in_registers) return t_wb_fmcpico1m_4ch_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body wb_fmcpico1m_4ch_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_wb_fmcpico1m_4ch_csr_in_registers) return t_wb_fmcpico1m_4ch_csr_in_registers is
variable tmp: t_wb_fmcpico1m_4ch_csr_in_registers;
begin
tmp.fmc_status_prsnt_i := f_x_to_zero(left.fmc_status_prsnt_i) or f_x_to_zero(right.fmc_status_prsnt_i);
tmp.fmc_status_pg_m2c_i := f_x_to_zero(left.fmc_status_pg_m2c_i) or f_x_to_zero(right.fmc_status_pg_m2c_i);
tmp.data0_val_i := f_x_to_zero(left.data0_val_i) or f_x_to_zero(right.data0_val_i);
tmp.data1_val_i := f_x_to_zero(left.data1_val_i) or f_x_to_zero(right.data1_val_i);
tmp.data2_val_i := f_x_to_zero(left.data2_val_i) or f_x_to_zero(right.data2_val_i);
tmp.data3_val_i := f_x_to_zero(left.data3_val_i) or f_x_to_zero(right.data3_val_i);
return tmp;
end function;
end package body;
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/xwb_fmcpico1m_4ch.vhd 0 → 100644
View file @ 38870233
------------------------------------------------------------------------------
-- Title : Wishbone FMC250 Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-02-19
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top Module for the BPM with FMC250.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-19 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Wishbone Stream Interface
use work.wb_stream_generic_pkg.all;
-- FMC ADC package
--use work.fmc_adc_pkg.all;
entity xwb_fmcpico1m_4ch is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false;
g_num_adc_bits : natural := 20;
g_num_adc_channels : natural := 4;
g_clk_freq : natural := 300000000; -- Hz
g_sclk_freq : natural := 75000000 --Hz
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
adc_fast_spi_clk_i : in std_logic;
adc_fast_spi_rstn_i : in std_logic;
-- Control signals
adc_start_i : in std_logic;
-- SPI bus
adc_sdo1_i : in std_logic;
adc_sdo2_i : in std_logic;
adc_sdo3_i : in std_logic;
adc_sdo4_i : in std_logic;
adc_sck_o : out std_logic;
adc_sck_rtrn_i : in std_logic;
adc_busy_cmn_i : in std_logic;
adc_cnv_out_o : out std_logic;
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
-- clock to CDC. This must be g_sclk_freq/g_num_adc_bits. A regular 100MHz should
-- suffice in all cases
adc_clk_i : in std_logic;
adc_data_o : out std_logic_vector(g_num_adc_channels*g_num_adc_bits-1 downto 0);
adc_data_valid_o : out std_logic_vector(g_num_adc_channels-1 downto 0);
adc_out_busy_o : out std_logic
);
end xwb_fmcpico1m_4ch;
architecture rtl of xwb_fmcpico1m_4ch is
signal wbs_adr_int : std_logic_vector(g_num_adc_channels*c_wbs_adr4_width-1 downto 0);
signal wbs_dat_int : std_logic_vector(g_num_adc_channels*c_wbs_dat16_width-1 downto 0);
signal wbs_cyc_int : std_logic_vector(g_num_adc_channels-1 downto 0);
signal wbs_stb_int : std_logic_vector(g_num_adc_channels-1 downto 0);
signal wbs_we_int : std_logic_vector(g_num_adc_channels-1 downto 0);
signal wbs_sel_int : std_logic_vector(g_num_adc_channels*c_wbs_sel16_width-1 downto 0);
signal wbs_ack_int : std_logic_vector(g_num_adc_channels-1 downto 0);
signal wbs_stall_int : std_logic_vector(g_num_adc_channels-1 downto 0);
signal wbs_err_int : std_logic_vector(g_num_adc_channels-1 downto 0);
signal wbs_rty_int : std_logic_vector(g_num_adc_channels-1 downto 0);
begin
cmp_wb_fmcpico1m_4ch : wb_fmcpico1m_4ch
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_with_extra_wb_reg => g_with_extra_wb_reg,
g_num_adc_bits => g_num_adc_bits,
g_num_adc_channels => g_num_adc_channels,
g_clk_freq => g_clk_freq,
g_sclk_freq => g_sclk_freq
)
port map (
sys_clk_i => sys_clk_i,
sys_rst_n_i => sys_rst_n_i,
sys_clk_200Mhz_i => sys_clk_200Mhz_i,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_err_o => wb_slv_o.err,
wb_rty_o => wb_slv_o.rty,
wb_stall_o => wb_slv_o.stall,
-----------------------------
-- External ports
-----------------------------
adc_fast_spi_clk_i => adc_fast_spi_clk_i,
adc_fast_spi_rstn_i => adc_fast_spi_rstn_i,
-- Control signals
adc_start_i => adc_start_i,
-- SPI bus
adc_sdo1_i => adc_sdo1_i,
adc_sdo2_i => adc_sdo2_i,
adc_sdo3_i => adc_sdo3_i,
adc_sdo4_i => adc_sdo4_i,
adc_sck_o => adc_sck_o,
adc_sck_rtrn_i => adc_sck_rtrn_i,
adc_busy_cmn_i => adc_busy_cmn_i,
adc_cnv_out_o => adc_cnv_out_o,
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
-- clock to CDC. This must be g_sclk_freq/g_num_adc_bits. A regular 100MHz should
-- suffice in all cases
adc_clk_i => adc_clk_i,
adc_data_o => adc_data_o,
adc_data_valid_o => adc_data_valid_o,
adc_out_busy_o => adc_out_busy_o
);
--gen_wbs_interfaces : for i in 0 to g_num_adc_channels-1 generate
-- gen_wbs_interfaces_ch : if g_use_data_chains(i) = '1' generate
-- wbs_ack_int(i) <= wbs_source_i(i).ack;
-- wbs_stall_int(i) <= wbs_source_i(i).stall;
-- wbs_err_int(i) <= wbs_source_i(i).err;
-- wbs_rty_int(i) <= wbs_source_i(i).rty;
-- wbs_source_o(i).adr <= wbs_adr_int(c_wbs_adr4_width*(i+1)-1 downto
-- c_wbs_adr4_width*i);
-- wbs_source_o(i).dat <= wbs_dat_int(c_wbs_dat16_width*(i+1)-1 downto
-- c_wbs_dat16_width*i);
-- wbs_source_o(i).sel <= wbs_sel_int(c_wbs_sel16_width*(i+1)-1 downto
-- c_wbs_sel16_width*i);
-- wbs_source_o(i).cyc <= wbs_cyc_int(i);
-- wbs_source_o(i).stb <= wbs_stb_int(i);
-- wbs_source_o(i).we <= wbs_we_int(i);
-- end generate;
--end generate;
end rtl;
hdl/platform/artix7/afc_v3/axi_datamover_0/axi_datamover_0.xci
View file @ 38870233
......@@ -85,7 +85,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg1156</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
......
hdl/platform/artix7/afc_v3/axi_datamover_bpm/axi_datamover_bpm.xci
View file @ 38870233
......@@ -85,7 +85,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg1156</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
......
hdl/platform/artix7/afc_v3/axi_datamover_bpm/axi_datamover_bpm.xml
View file @ 38870233
......@@ -871,12 +871,12 @@
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_veriloginstantiationtemplate</spirit:name>
<spirit:displayName>Verilog Instantiation Template</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:name>xilinx_vhdlinstantiationtemplate</spirit:name>
<spirit:displayName>VHDL Instantiation Template</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:fileSetRef>
<spirit:localName>xilinx_veriloginstantiationtemplate_view_fileset</spirit:localName>
<spirit:localName>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
......@@ -3260,7 +3260,7 @@
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_veriloginstantiationtemplate_view_fileset</spirit:name>
<spirit:name>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:name>
<spirit:file>
<spirit:name>axi_datamover_bpm.vho</spirit:name>
<spirit:userFileType>vhdlTemplate</spirit:userFileType>
......
hdl/platform/artix7/afc_v3/axi_interconnect/axi_interconnect.xci
View file @ 38870233
......@@ -431,7 +431,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg1156</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
......
hdl/platform/artix7/afc_v3/axi_interconnect_bpm/axi_interconnect_bpm.xci
View file @ 38870233
......@@ -431,7 +431,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg1156</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
......
hdl/platform/artix7/afc_v3/axi_interconnect_bpm/axi_interconnect_bpm.xml
View file @ 38870233
......@@ -5705,12 +5705,12 @@
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_veriloginstantiationtemplate</spirit:name>
<spirit:displayName>Verilog Instantiation Template</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:name>xilinx_vhdlinstantiationtemplate</spirit:name>
<spirit:displayName>VHDL Instantiation Template</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:fileSetRef>
<spirit:localName>xilinx_veriloginstantiationtemplate_view_fileset</spirit:localName>
<spirit:localName>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
......@@ -22768,7 +22768,7 @@
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_veriloginstantiationtemplate_view_fileset</spirit:name>
<spirit:name>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:name>
<spirit:file>
<spirit:name>axi_interconnect_bpm.vho</spirit:name>
<spirit:userFileType>vhdlTemplate</spirit:userFileType>
hdl/platform/artix7/afc_v3/pcie_core/pcie_core.xci
View file @ 38870233
......@@ -460,7 +460,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg1156</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
......
hdl/sim/regs/wb_fmcpico1m_4ch_regs.vh 0 → 100644
View file @ 38870233
`define ADDR_WB_FMCPICO1M_4CH_CSR_FMC_STATUS 5'h0
`define WB_FMCPICO1M_4CH_CSR_FMC_STATUS_PRSNT_OFFSET 0
`define WB_FMCPICO1M_4CH_CSR_FMC_STATUS_PRSNT 32'h00000001
`define WB_FMCPICO1M_4CH_CSR_FMC_STATUS_PG_M2C_OFFSET 1
`define WB_FMCPICO1M_4CH_CSR_FMC_STATUS_PG_M2C 32'h00000002
`define ADDR_WB_FMCPICO1M_4CH_CSR_FMC_CTL 5'h4
`define WB_FMCPICO1M_4CH_CSR_FMC_CTL_LED1_OFFSET 0
`define WB_FMCPICO1M_4CH_CSR_FMC_CTL_LED1 32'h00000001
`define WB_FMCPICO1M_4CH_CSR_FMC_CTL_LED2_OFFSET 1
`define WB_FMCPICO1M_4CH_CSR_FMC_CTL_LED2 32'h00000002
`define ADDR_WB_FMCPICO1M_4CH_CSR_RNG_CTL 5'h8
`define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R0_OFFSET 0
`define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R0 32'h00000001
`define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R1_OFFSET 8
`define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R1 32'h00000100
`define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R2_OFFSET 16
`define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R2 32'h00010000
`define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R3_OFFSET 24
`define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R3 32'h01000000
`define ADDR_WB_FMCPICO1M_4CH_CSR_DATA0 5'hc
`define WB_FMCPICO1M_4CH_CSR_DATA0_VAL_OFFSET 0
`define WB_FMCPICO1M_4CH_CSR_DATA0_VAL 32'hffffffff
`define ADDR_WB_FMCPICO1M_4CH_CSR_DATA1 5'h10
`define WB_FMCPICO1M_4CH_CSR_DATA1_VAL_OFFSET 0
`define WB_FMCPICO1M_4CH_CSR_DATA1_VAL 32'hffffffff
`define ADDR_WB_FMCPICO1M_4CH_CSR_DATA2 5'h14
`define WB_FMCPICO1M_4CH_CSR_DATA2_VAL_OFFSET 0
`define WB_FMCPICO1M_4CH_CSR_DATA2_VAL 32'hffffffff
`define ADDR_WB_FMCPICO1M_4CH_CSR_DATA3 5'h18
`define WB_FMCPICO1M_4CH_CSR_DATA3_VAL_OFFSET 0
`define WB_FMCPICO1M_4CH_CSR_DATA3_VAL 32'hffffffff
hdl/syn/afc_v3/vivado/dbe_pbpm/Manifest.py 0 → 100755
View file @ 38870233
target = "xilinx"
action = "synthesis"
syn_device = "xc7a200t"
syn_grade = "-2"
syn_package = "ffg1156"
syn_top = "dbe_pbpm"
syn_project = "dbe_pbpm"
syn_tool = "vivado"
syn_properties = [
["steps.synth_design.args.more options", "-verbose"],
["steps.opt_design.args.verbose", "1"],
["steps.opt_design.args.directive", "Explore"],
["steps.opt_design.is_enabled", "1"],
["steps.place_design.args.directive", "Explore"],
["steps.place_design.args.more options", "-verbose"],
["steps.phys_opt_design.args.directive", "AlternateFlowWithRetiming"],
["steps.phys_opt_design.args.more options", "-verbose"],
["steps.phys_opt_design.is_enabled", "1"],
["steps.route_design.args.directive", "Explore"],
["steps.route_design.args.more options", "-verbose"],
["steps.post_route_phys_opt_design.args.directive", "AddRetime"],
["steps.post_route_phys_opt_design.args.more options", "-verbose"],
["steps.post_route_phys_opt_design.is_enabled", "1"],
["steps.write_bitstream.args.verbose", "1"]]
import os
import sys
if os.path.isfile("synthesis_descriptor_pkg.vhd"):
files = ["synthesis_descriptor_pkg.vhd"];
else:
sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)")
# Doesn't matter got PBPM
machine_pkg = "uvx_250M"
modules = { "local" : [ "../../../../top/afc_v3/vivado/dbe_pbpm" ] };
hdl/syn/afc_v3/vivado/dbe_pbpm/build_bitstream_local.sh 0 → 100755
View file @ 38870233
#!/bin/bash
# Exit on error
set -e
# Check for uninitialized variables
set -u
COMMAND="(./build_synthesis_sdb.sh; hdlmake; time make; date) 2>&1 | tee make_output &"
echo $COMMAND
eval $COMMAND
hdl/syn/afc_v3/vivado/dbe_pbpm/build_bitstream_remote.sh 0 → 100755
View file @ 38870233
#!/bin/bash
# Exit on error
set -e
# Check for uninitialized variables
set -u
COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &"
echo $COMMAND
eval $COMMAND
hdl/syn/afc_v3/vivado/dbe_pbpm/build_synthesis_sdb.sh 0 → 100755
View file @ 38870233
#!/bin/bash
# Exit on error
set -e
# Check for uninitialized variables
set -u
SYNTH_INFO_PROJECT="bpm-pbpm"
SYNTH_INFO_TOOL="VIVADO"
SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2)
SYNTH_INFO_COMMAND="../../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}"
# Generate synthesis file
echo $SYNTH_INFO_COMMAND
eval $SYNTH_INFO_COMMAND
hdl/syn/afc_v3/vivado/dbe_pbpm/synthesis_descriptor_pkg.vhd 0 → 100644
View file @ 38870233
-- package generated automatically by gen_sdbsyn.py script --
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor_pkg is
constant c_sdb_repo_url : t_sdb_repo_url := (
repo_url => "https://github.com/lnls-dig/bpm-gw.git ");
constant c_sdb_top_syn_info : t_sdb_synthesis := (
syn_module_name => "bpm-gw+ ",
syn_commit_id => "960efc8c227ca92489e28547d5adb833",
syn_tool_name => "VIVADO ",
syn_tool_version => x"00201521",
syn_date => x"20151208",
syn_username => "LRusso ");
constant c_sdb_dsp_cores_syn_info : t_sdb_synthesis := (
syn_module_name => "dsp-cores+ ",
syn_commit_id => "befc6979e416ef28cc042b3030a8140b",
syn_tool_name => " ",
syn_tool_version => x"00000000",
syn_date => x"00000000",
syn_username => " ");
constant c_sdb_etherbone_core_syn_info : t_sdb_synthesis := (
syn_module_name => "etherbone-core ",
syn_commit_id => "b29565ac63ca92987cd9a9a754b6add8",
syn_tool_name => " ",
syn_tool_version => x"00000000",
syn_date => x"00000000",
syn_username => " ");
constant c_sdb_general_cores_syn_info : t_sdb_synthesis := (
syn_module_name => "general-cores ",
syn_commit_id => "cc53ef7f6c381ca1ce56355b2fd99246",
syn_tool_name => " ",
syn_tool_version => x"00000000",
syn_date => x"00000000",
syn_username => " ");
end package;
\ No newline at end of file
hdl/top/afc_v3/vivado/dbe_bpm/dbe_bpm.vhd
View file @ 38870233
This diff is collapsed.
hdl/top/afc_v3/vivado/dbe_bpm2/dbe_bpm2.vhd
View file @ 38870233
This diff is collapsed.
hdl/top/afc_v3/vivado/dbe_bpm_gen/sys_pll.vhd
View file @ 38870233
......@@ -36,13 +36,16 @@ generic(
-- 100 MHz output clock
g_clk0_divide_f : integer := 10;
-- 200 MHz output clock
g_clk1_divide : integer := 5
g_clk1_divide : integer := 5;
-- 200 MHz output clock
g_clk2_divide : integer := 5
);
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
clk2_o : out std_logic;
locked_o : out std_logic
);
end sys_pll;
......@@ -54,6 +57,7 @@ architecture syn of sys_pll is
signal s_clk0 : std_logic;
signal s_clk1 : std_logic;
signal s_clk2 : std_logic;
begin
-- Clock PLL
......@@ -68,7 +72,7 @@ begin
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => g_clk0_divide_f,
CLKOUT1_DIVIDE => g_clk1_divide,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DIVIDE => g_clk2_divide,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
......@@ -97,7 +101,7 @@ begin
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => s_clk0, -- 1-bit output: CLKOUT0
CLKOUT1 => s_clk1, -- 1-bit output: CLKOUT1
CLKOUT2 => open, -- 1-bit output: CLKOUT2
CLKOUT2 => s_clk2, -- 1-bit output: CLKOUT2
CLKOUT3 => open, -- 1-bit output: CLKOUT3
CLKOUT4 => open, -- 1-bit output: CLKOUT4
CLKOUT5 => open, -- 1-bit output: CLKOUT5
......@@ -143,4 +147,10 @@ begin
I => s_clk1
);
cmp_clkout2_buf : BUFG
port map(
O => clk2_o,
I => s_clk2
);
end syn;
hdl/top/afc_v3/vivado/dbe_pbpm/Manifest.py 0 → 100644
View file @ 38870233
files = [ "dbe_pbpm.vhd",
"dbe_pbpm.xdc",
"pcie_core.xdc",
"ddr_core.xdc",
"dbe_pbpm.xcf" ];
modules = { "local" :
["../../../..",
"../dbe_bpm_gen"
]
};
hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.vhd 0 → 100755
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hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.xcf 0 → 100644
View file @ 38870233
MODEL ui_rd_data max_fanout = 20;
BEGIN MODEL ui_wr_data
NET app_wdf_rdy_r max_fanout=20;
END;
BEGIN MODEL ui_cmd
NET app_rdy_r max_fanout=20;
END;
BEGIN MODEL phy_rdclk_gen
NET rst_oserdes max_fanout=10;
END;
BEGIN MODEL phy_data_io
NET rst_r max_fanout=1;
END;
BEGIN MODEL phy_control_io
NET rst_r max_fanout=1;
END;
hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.xdc 0 → 100644
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hdl/top/afc_v3/vivado/dbe_pbpm/ddr_core.xdc 0 → 100755
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This diff is collapsed.
hdl/top/afc_v3/vivado/dbe_pbpm/pcie_core.xdc 0 → 100755
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