hdl/testbench/*/wb_acq_core_test/*: add Artix 7 FPGA simulation

The main difference from the Virtex 6 simulation is the DDR3 generated controller.

hdl/testbench//wb_acq_core_test/: add Artix 7 FPGA simulation
The main difference from the Virtex 6 simulation is the DDR3 generated controller.
462c2bc5 · Lucas Russo · 65d8c401 · 462c2bc5 · 462c2bc5 · 462c2bc5
Commit 462c2bc5 authored Sep 08, 2014 by Lucas Russo
9 changed files
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/Makefile
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/Makefile
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/Manifest.py
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/Manifest.py
+action = "simulation"
+target = "xilinx"
+syn_device = "xc7a200t"
+
+modules = {"local" : [
+                    "../../../../../../modules/dbe_wishbone",
+                    "../../../../../../modules/dbe_common",
+                    "../../../../../../modules/rffe_top",
+                    "../../../../../../modules/fabric",
+                    "../../../../../../modules/fmc_adc_common",
+                    "../../../../../../modules/pcie",
+                    "../../../../../../ip_cores/general-cores",
+                    "../../../../../../ip_cores/etherbone-core",
+                    "../../../../../../platform/virtex6/chipscope",
+                    "../../../../../../platform/virtex6/ip_cores",
+                    "../../../../../../sim/ddr_model",
+#                    "../../../../../../ip_cores/pcie/7a200ffg1156/ddr_core_1_8/user_design/"]}
+                     "../../../../../../ip_cores/pcie/7a200ffg1156/ddr_core/user_design/"]}
+
+files = ["wb_acq_core_tb.v", "ddr_core_wrapper.vhd", "defines.v", "timescale.v",
+			"clk_rst.v"]
+
+vlog_opt = "+incdir+../../../../../../sim/regs +incdir+../../../../../../sim +incdir+../../../../../../sim/ddr_model"
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v
+`include "timescale.v"
+`include "defines.v"
+
+module clk_rst(
+  clk_sys_o,
+  clk_adc_o,
+  clk_100mhz_o,
+  clk_200mhz_o,
+  sys_rstn_o,
+  adc_rstn_o,
+  clk100mhz_rstn_o,
+  clk200mhz_rstn_o
+);
+
+  // Defaults parameters
+  parameter CLK_SYS_PERIOD = `CLK_SYS_PERIOD;
+  parameter CLK_ADC_PERIOD = `CLK_ADC_PERIOD;
+
+  localparam CLK_100MHZ_PERIOD = `CLK_100MHZ_PERIOD;
+  localparam CLK_200MHZ_PERIOD = `CLK_200MHZ_PERIOD;
+
+  // Output Clocks
+  output reg
+    clk_sys_o,
+    clk_adc_o,
+    clk_100mhz_o,
+    clk_200mhz_o;
+
+  // Output Reset
+  output reg
+    sys_rstn_o,
+    adc_rstn_o,
+    clk100mhz_rstn_o,
+    clk200mhz_rstn_o;
+
+  initial
+  begin
+    clk_sys_o = 0;
+    clk_adc_o = 0;
+    clk_100mhz_o = 0;
+    clk_200mhz_o = 0;
+  end
+
+  // Reset generate
+  initial
+  begin
+    sys_rstn_o <= 1'b0;
+
+    repeat (`RST_SYS_DELAY) begin
+      @(posedge clk_sys_o);
+    end
+
+    @(posedge clk_sys_o);
+    sys_rstn_o <= 1'b1;
+  end
+
+  initial
+  begin
+    adc_rstn_o <= 1'b0;
+
+    //repeat (`RST_ADC_DELAY) begin
+    //  @(posedge clk_adc_o);
+    //end
+    repeat (`RST_SYS_DELAY) begin
+      @(posedge clk_sys_o);
+    end
+
+    @(posedge clk_adc_o);
+    adc_rstn_o <= 1'b1;
+  end
+
+  initial
+  begin
+    clk100mhz_rstn_o <= 1'b0;
+
+    //repeat (`RST_SYS_DELAY) begin
+    //  @(posedge clk_100mhz_o);
+    //end
+    repeat (`RST_SYS_DELAY) begin
+      @(posedge clk_sys_o);
+    end
+
+    @(posedge clk_100mhz_o);
+    clk100mhz_rstn_o <= 1'b1;
+  end
+
+  initial
+  begin
+    clk200mhz_rstn_o <= 1'b0;
+
+    //repeat (`RST_ADC_DELAY) begin
+    //  @(posedge clk_200mhz_o);
+    //end
+    repeat (`RST_SYS_DELAY) begin
+      @(posedge clk_sys_o);
+    end
+
+    @(posedge clk_200mhz_o);
+    clk200mhz_rstn_o <= 1'b1;
+  end
+
+  // Clock Generation
+  always #(CLK_SYS_PERIOD/2) clk_sys_o <= ~clk_sys_o;
+  always #(CLK_ADC_PERIOD/2) clk_adc_o <= ~clk_adc_o;
+  always #(CLK_100MHZ_PERIOD/2) clk_100mhz_o <= ~clk_100mhz_o;
+  always #(CLK_200MHZ_PERIOD/2) clk_200mhz_o <= ~clk_200mhz_o;
+
+endmodule
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/ddr_core_wrapper.vhd
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/ddr_core_wrapper.vhd
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/defines.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/defines.v
+/*******************************
+ * Wishbone definitions
+ *******************************/
+
+// Wishbone Reference Clock
+`define WB_CLOCK_PERIOD 10.00
+`define WB_RESET_DELAY (10*`WB_CLOCK_PERIOD)
+`define WB_RESET_COUNTS 6
+// Wishbone Data Width
+`define WB_DATA_BUS_WIDTH 32
+// Wishbone Address Width
+`define WB_ADDRESS_BUS_WIDTH 32
+`define WB_BWSEL_WIDTH ((`WB_DATA_BUS_WIDTH + 7) / 8)
+`define WB_WORD_ACC 2
+
+/*******************************
+ * ADC (FMC516) definitions
+ *******************************/
+`define ADC_DATA_WIDTH 16
+`define DATA_TEST_WIDTH 64
+
+/*******************************
+ * General definitions
+ *******************************/
+
+// 100 MHz clock
+//`define CLK_SYS_PERIOD 10.00 //ns
+`define CLK_SYS_PERIOD 10000.00 //ps
+// 100 MHz clock
+//`define CLK_100MHZ_PERIOD 10.00 //ns
+`define CLK_100MHZ_PERIOD 10000.00 //ps
+// 200 MHz clock
+//`define CLK_200MHZ_PERIOD 5.00 //ns
+`define CLK_200MHZ_PERIOD 5000.00 //ps
+// 130 MHz clock
+//`define CLK_ADC_PERIOD 8.882 //ns
+`define CLK_ADC_PERIOD 8882.00 //ps
+
+// Reset Delay, in Clock Cycles
+`define RST_SYS_DELAY  500 // 5000//101000 // ??? > 500 us
+`define RST_ADC_DELAY  500 // 5000//101000 // ??? > 500 us
+
+/*******************************
+ * DDR3 definitions
+ *******************************/
+//`define DDR_DQ_WIDTH        64
+//`define DDR_PAYLOAD_WIDTH   256
+//`define DDR_DQS_WIDTH       8
+//`define DDR_DM_WIDTH        8
+//`define DDR_ROW_WIDTH       14
+//`define DDR_BANK_WIDTH      3
+//`define DDR_CK_WIDTH        1
+//`define DDR_CKE_WIDTH       1
+//`define DDR_ODT_WIDTH       1
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/run.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/run.do
+vlog wb_acq_core_tb.v +incdir+"." +incdir+../../../../../../sim +incdir+../../../../../../sim/regs
+-- make -f Makefile
+-- output log file to file "output.log", set siulation resolution to "fs"
+vsim -l output.log -voptargs="+acc" -t fs -L unisims_ver -L unisim -L secureip work.wb_acq_core_tb glbl
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+-- do wave.do
+do wave_compl.do
+radix -hexadecimal
+-- run 250us
+run 5000us
+wave zoomfull
+radix -hexadecimal
+
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/timescale.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/timescale.v
+// reference time = 1ns
+// precision time = 1ps
+//`timescale 1ns/1ps
+`timescale 1ps/100fs
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/wave_compl.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/wave_compl.do
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/wb_acq_core_tb.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/wb_acq_core_tb.v