hdl/*/platform/*: add new chipscope icon modules

hdl//platform/: add new chipscope icon modules
51f60662 · Lucas Russo · 9bd88252 · 51f60662 · 51f60662 · 51f60662
Commit 51f60662 authored May 27, 2013 by Lucas Russo
5 changed files
--- a/hdl/platform/virtex6/chipscope/Manifest.py
+++ b/hdl/platform/virtex6/chipscope/Manifest.py
 files = ["icon_1_port/chipscope_icon_1_port.ngc", "icon_2_port/chipscope_icon_2_port.ngc", 
-	"icon_4_port/chipscope_icon_4_port.ngc", "ila/chipscope_ila.ngc", "ila/chipscope_ila_8192.ngc"]
+	"icon_4_port/chipscope_icon_4_port.ngc", "icon_7_port/chipscope_icon_7_port.ngc", 
+	"icon_8_port/chipscope_icon_8_port.ngc", "ila/chipscope_ila.ngc", "ila/chipscope_ila_8192.ngc"]
--- a/hdl/platform/virtex6/chipscope/icon_7_port/chipscope_icon_7_port.ngc
+++ b/hdl/platform/virtex6/chipscope/icon_7_port/chipscope_icon_7_port.ngc
--- a/hdl/platform/virtex6/chipscope/icon_7_port/chipscope_icon_7_port.vhd
+++ b/hdl/platform/virtex6/chipscope/icon_7_port/chipscope_icon_7_port.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 13.4
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_icon_7_port.vhd
+-- /___/   /\     Timestamp  : Wed Apr 03 08:32:11 BRT 2013
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_icon_7_port IS
+  port (
+    CONTROL0: inout std_logic_vector(35 downto 0);
+    CONTROL1: inout std_logic_vector(35 downto 0);
+    CONTROL2: inout std_logic_vector(35 downto 0);
+    CONTROL3: inout std_logic_vector(35 downto 0);
+    CONTROL4: inout std_logic_vector(35 downto 0);
+    CONTROL5: inout std_logic_vector(35 downto 0);
+    CONTROL6: inout std_logic_vector(35 downto 0));
+END chipscope_icon_7_port;
+
+ARCHITECTURE chipscope_icon_7_port_a OF chipscope_icon_7_port IS
+BEGIN
+
+END chipscope_icon_7_port_a;
--- a/hdl/platform/virtex6/chipscope/icon_8_port/chipscope_icon_8_port.ngc
+++ b/hdl/platform/virtex6/chipscope/icon_8_port/chipscope_icon_8_port.ngc
--- a/hdl/platform/virtex6/chipscope/icon_8_port/chipscope_icon_8_port.vhd
+++ b/hdl/platform/virtex6/chipscope/icon_8_port/chipscope_icon_8_port.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 13.4
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_icon_8_port.vhd
+-- /___/   /\     Timestamp  : Tue Apr 02 16:25:10 BRT 2013
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_icon_8_port IS
+  port (
+    CONTROL0: inout std_logic_vector(35 downto 0);
+    CONTROL1: inout std_logic_vector(35 downto 0);
+    CONTROL2: inout std_logic_vector(35 downto 0);
+    CONTROL3: inout std_logic_vector(35 downto 0);
+    CONTROL4: inout std_logic_vector(35 downto 0);
+    CONTROL5: inout std_logic_vector(35 downto 0);
+    CONTROL6: inout std_logic_vector(35 downto 0);
+    CONTROL7: inout std_logic_vector(35 downto 0));
+END chipscope_icon_8_port;
+
+ARCHITECTURE chipscope_icon_8_port_a OF chipscope_icon_8_port IS
+BEGIN
+
+END chipscope_icon_8_port_a;