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Commit 551131ce authored by Lucas Russo's avatar Lucas Russo
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wb_fmc516/wbgen/*: add update delay signal for clk and data

parent 9ecdb26d
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hdl/modules/custom_wishbone/wb_fmc516/wbgen/doc/fmc516_regs_wb.html
View file @ 551131ce
......@@ -203,20 +203,25 @@ Global ADC control register.
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{UPDATE_DLY}
@code{UPDATE_CLK_DLY}
@tab @code{X} @tab
Reset/Update ADC clock/data chains delay
Reset/Update ADC clock chains delay
@item @code{1}
@tab R/W @tab
@code{UPDATE_DATA_DLY}
@tab @code{X} @tab
Reset/Update ADC data chains delay
@item @code{2}
@tab R/W @tab
@code{RST_ADCS}
@tab @code{X} @tab
Reset ADCs
@item @code{2}
@item @code{3}
@tab R/W @tab
@code{RST_DIV_ADCS}
@tab @code{X} @tab
Reset Div ADCs
@item @code{31...3}
@item @code{31...4}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
......@@ -224,7 +229,8 @@ Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{update_dly} @tab write 1: reset/update clock/data chains to its default @* values or from the values in the delay registers.@* write 0: no effect
@item @code{update_clk_dly} @tab write 1: reset/update clock chains to its default @* values or from the values in the delay registers.@* write 0: no effect
@item @code{update_data_dly} @tab write 1: reset/update data chains to its default @* values or from the values in the delay registers.@* write 0: no effect
@item @code{rst_adcs} @tab Reset and recalibrate ADCs@* write 0: no reset @* write 1: enable ADC reset
@item @code{rst_div_adcs} @tab Reset for synchronization between multiple ADCs @* write 0: no reset @* write 1: enable ADC div reset
@item @code{reserved} @tab Ignore on write, read as 0's
......
hdl/modules/custom_wishbone/wb_fmc516/wbgen/fmc516_regs.h
View file @ 551131ce
......@@ -3,7 +3,7 @@
* File : fmc516_regs.h
* Author : auto-generated by wbgen2 from wb_fmc516_regs.wb
* Created : Wed Mar 13 16:08:19 2013
* Created : Fri Mar 15 10:56:52 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
......@@ -122,20 +122,23 @@
/* definitions for register: Global ADC Control register */
/* definitions for field: Reset/Update ADC clock/data chains delay in reg: Global ADC Control register */
#define FMC516_ADC_CTL_UPDATE_DLY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Reset/Update ADC clock chains delay in reg: Global ADC Control register */
#define FMC516_ADC_CTL_UPDATE_CLK_DLY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Reset/Update ADC data chains delay in reg: Global ADC Control register */
#define FMC516_ADC_CTL_UPDATE_DATA_DLY WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reset ADCs in reg: Global ADC Control register */
#define FMC516_ADC_CTL_RST_ADCS WBGEN2_GEN_MASK(1, 1)
#define FMC516_ADC_CTL_RST_ADCS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reset Div ADCs in reg: Global ADC Control register */
#define FMC516_ADC_CTL_RST_DIV_ADCS WBGEN2_GEN_MASK(2, 1)
#define FMC516_ADC_CTL_RST_DIV_ADCS WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Global ADC Control register */
#define FMC516_ADC_CTL_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define FMC516_ADC_CTL_RESERVED_SHIFT 3
#define FMC516_ADC_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define FMC516_ADC_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
#define FMC516_ADC_CTL_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define FMC516_ADC_CTL_RESERVED_SHIFT 4
#define FMC516_ADC_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define FMC516_ADC_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Channel 0 status register */
......
hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd
View file @ 551131ce
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wb_fmc516_regs.vhd
-- Author : auto-generated by wbgen2 from wb_fmc516_regs.wb
-- Created : Wed Mar 13 16:08:18 2013
-- Created : Fri Mar 15 10:56:52 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
......@@ -53,11 +53,16 @@ signal fmc516_trig_cfg_hw_trig_en_int : std_logic ;
signal fmc516_trig_cfg_hw_trig_en_sync0 : std_logic ;
signal fmc516_trig_cfg_hw_trig_en_sync1 : std_logic ;
signal fmc516_trig_cfg_reserved_int : std_logic_vector(29 downto 0);
signal fmc516_adc_ctl_update_dly_int : std_logic ;
signal fmc516_adc_ctl_update_dly_int_delay : std_logic ;
signal fmc516_adc_ctl_update_dly_sync0 : std_logic ;
signal fmc516_adc_ctl_update_dly_sync1 : std_logic ;
signal fmc516_adc_ctl_update_dly_sync2 : std_logic ;
signal fmc516_adc_ctl_update_clk_dly_int : std_logic ;
signal fmc516_adc_ctl_update_clk_dly_int_delay : std_logic ;
signal fmc516_adc_ctl_update_clk_dly_sync0 : std_logic ;
signal fmc516_adc_ctl_update_clk_dly_sync1 : std_logic ;
signal fmc516_adc_ctl_update_clk_dly_sync2 : std_logic ;
signal fmc516_adc_ctl_update_data_dly_int : std_logic ;
signal fmc516_adc_ctl_update_data_dly_int_delay : std_logic ;
signal fmc516_adc_ctl_update_data_dly_sync0 : std_logic ;
signal fmc516_adc_ctl_update_data_dly_sync1 : std_logic ;
signal fmc516_adc_ctl_update_data_dly_sync2 : std_logic ;
signal fmc516_adc_ctl_rst_adcs_int : std_logic ;
signal fmc516_adc_ctl_rst_adcs_int_delay : std_logic ;
signal fmc516_adc_ctl_rst_adcs_sync0 : std_logic ;
......@@ -292,8 +297,10 @@ begin
fmc516_trig_cfg_hw_trig_pol_int <= '0';
fmc516_trig_cfg_hw_trig_en_int <= '0';
fmc516_trig_cfg_reserved_int <= "000000000000000000000000000000";
fmc516_adc_ctl_update_dly_int <= '0';
fmc516_adc_ctl_update_dly_int_delay <= '0';
fmc516_adc_ctl_update_clk_dly_int <= '0';
fmc516_adc_ctl_update_clk_dly_int_delay <= '0';
fmc516_adc_ctl_update_data_dly_int <= '0';
fmc516_adc_ctl_update_data_dly_int_delay <= '0';
fmc516_adc_ctl_rst_adcs_int <= '0';
fmc516_adc_ctl_rst_adcs_int_delay <= '0';
fmc516_adc_ctl_rst_div_adcs_int <= '0';
......@@ -398,8 +405,10 @@ begin
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
fmc516_adc_ctl_update_dly_int <= fmc516_adc_ctl_update_dly_int_delay;
fmc516_adc_ctl_update_dly_int_delay <= '0';
fmc516_adc_ctl_update_clk_dly_int <= fmc516_adc_ctl_update_clk_dly_int_delay;
fmc516_adc_ctl_update_clk_dly_int_delay <= '0';
fmc516_adc_ctl_update_data_dly_int <= fmc516_adc_ctl_update_data_dly_int_delay;
fmc516_adc_ctl_update_data_dly_int_delay <= '0';
fmc516_adc_ctl_rst_adcs_int <= fmc516_adc_ctl_rst_adcs_int_delay;
fmc516_adc_ctl_rst_adcs_int_delay <= '0';
fmc516_adc_ctl_rst_div_adcs_int <= fmc516_adc_ctl_rst_div_adcs_int_delay;
......@@ -562,17 +571,20 @@ begin
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
fmc516_adc_ctl_update_dly_int <= wrdata_reg(0);
fmc516_adc_ctl_update_dly_int_delay <= wrdata_reg(0);
fmc516_adc_ctl_rst_adcs_int <= wrdata_reg(1);
fmc516_adc_ctl_rst_adcs_int_delay <= wrdata_reg(1);
fmc516_adc_ctl_rst_div_adcs_int <= wrdata_reg(2);
fmc516_adc_ctl_rst_div_adcs_int_delay <= wrdata_reg(2);
fmc516_adc_ctl_update_clk_dly_int <= wrdata_reg(0);
fmc516_adc_ctl_update_clk_dly_int_delay <= wrdata_reg(0);
fmc516_adc_ctl_update_data_dly_int <= wrdata_reg(1);
fmc516_adc_ctl_update_data_dly_int_delay <= wrdata_reg(1);
fmc516_adc_ctl_rst_adcs_int <= wrdata_reg(2);
fmc516_adc_ctl_rst_adcs_int_delay <= wrdata_reg(2);
fmc516_adc_ctl_rst_div_adcs_int <= wrdata_reg(3);
fmc516_adc_ctl_rst_div_adcs_int_delay <= wrdata_reg(3);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(2) <= '0';
rddata_reg(31 downto 3) <= regs_i.adc_ctl_reserved_i;
rddata_reg(3) <= '0';
rddata_reg(31 downto 4) <= regs_i.adc_ctl_reserved_i;
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "0101" =>
......@@ -882,19 +894,36 @@ begin
-- FMC ADC Data chains
-- Reserved
-- FMC ADC packet size
-- Reset/Update ADC clock/data chains delay
-- Reset/Update ADC clock chains delay
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.adc_ctl_update_dly_o <= '0';
fmc516_adc_ctl_update_dly_sync0 <= '0';
fmc516_adc_ctl_update_dly_sync1 <= '0';
fmc516_adc_ctl_update_dly_sync2 <= '0';
regs_o.adc_ctl_update_clk_dly_o <= '0';
fmc516_adc_ctl_update_clk_dly_sync0 <= '0';
fmc516_adc_ctl_update_clk_dly_sync1 <= '0';
fmc516_adc_ctl_update_clk_dly_sync2 <= '0';
elsif rising_edge(fs_clk_i) then
fmc516_adc_ctl_update_dly_sync0 <= fmc516_adc_ctl_update_dly_int;
fmc516_adc_ctl_update_dly_sync1 <= fmc516_adc_ctl_update_dly_sync0;
fmc516_adc_ctl_update_dly_sync2 <= fmc516_adc_ctl_update_dly_sync1;
regs_o.adc_ctl_update_dly_o <= fmc516_adc_ctl_update_dly_sync2 and (not fmc516_adc_ctl_update_dly_sync1);
fmc516_adc_ctl_update_clk_dly_sync0 <= fmc516_adc_ctl_update_clk_dly_int;
fmc516_adc_ctl_update_clk_dly_sync1 <= fmc516_adc_ctl_update_clk_dly_sync0;
fmc516_adc_ctl_update_clk_dly_sync2 <= fmc516_adc_ctl_update_clk_dly_sync1;
regs_o.adc_ctl_update_clk_dly_o <= fmc516_adc_ctl_update_clk_dly_sync2 and (not fmc516_adc_ctl_update_clk_dly_sync1);
end if;
end process;
-- Reset/Update ADC data chains delay
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.adc_ctl_update_data_dly_o <= '0';
fmc516_adc_ctl_update_data_dly_sync0 <= '0';
fmc516_adc_ctl_update_data_dly_sync1 <= '0';
fmc516_adc_ctl_update_data_dly_sync2 <= '0';
elsif rising_edge(fs_clk_i) then
fmc516_adc_ctl_update_data_dly_sync0 <= fmc516_adc_ctl_update_data_dly_int;
fmc516_adc_ctl_update_data_dly_sync1 <= fmc516_adc_ctl_update_data_dly_sync0;
fmc516_adc_ctl_update_data_dly_sync2 <= fmc516_adc_ctl_update_data_dly_sync1;
regs_o.adc_ctl_update_data_dly_o <= fmc516_adc_ctl_update_data_dly_sync2 and (not fmc516_adc_ctl_update_data_dly_sync1);
end if;
end process;
......
hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.wb
View file @ 551131ce
......@@ -249,12 +249,26 @@ peripheral {
prefix = "adc_ctl";
field {
name = "Reset/Update ADC clock/data chains delay";
description = "write 1: reset/update clock/data chains to its default \
name = "Reset/Update ADC clock chains delay";
description = "write 1: reset/update clock chains to its default \
values or from the values in the delay registers.\
write 0: no effect";
prefix = "update_dly";
prefix = "update_clk_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reset/Update ADC data chains delay";
description = "write 1: reset/update data chains to its default \
values or from the values in the delay registers.\
write 0: no effect";
prefix = "update_data_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
......@@ -292,7 +306,7 @@ peripheral {
description = "Ignore on write, read as 0's";
prefix = "reserved";
type = SLV;
size = 29;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......
hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd
View file @ 551131ce
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wb_fmc516_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from wb_fmc516_regs.wb
-- Created : Wed Mar 13 16:08:18 2013
-- Created : Fri Mar 15 10:56:52 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
......@@ -30,7 +30,7 @@ package fmc516_wbgen2_pkg is
adc_sta_data_chains_i : std_logic_vector(3 downto 0);
adc_sta_reserved_data_chains_i : std_logic_vector(3 downto 0);
adc_sta_adc_pkt_size_i : std_logic_vector(15 downto 0);
adc_ctl_reserved_i : std_logic_vector(28 downto 0);
adc_ctl_reserved_i : std_logic_vector(27 downto 0);
ch0_sta_val_i : std_logic_vector(15 downto 0);
ch0_sta_reserved_i : std_logic_vector(15 downto 0);
ch0_ctl_clk_chain_dly_i : std_logic_vector(4 downto 0);
......@@ -107,7 +107,8 @@ package fmc516_wbgen2_pkg is
trig_cfg_hw_trig_pol_o : std_logic;
trig_cfg_hw_trig_en_o : std_logic;
trig_cfg_reserved_o : std_logic_vector(29 downto 0);
adc_ctl_update_dly_o : std_logic;
adc_ctl_update_clk_dly_o : std_logic;
adc_ctl_update_data_dly_o : std_logic;
adc_ctl_rst_adcs_o : std_logic;
adc_ctl_rst_div_adcs_o : std_logic;
ch0_ctl_clk_chain_dly_o : std_logic_vector(4 downto 0);
......@@ -162,7 +163,8 @@ package fmc516_wbgen2_pkg is
trig_cfg_hw_trig_pol_o => '0',
trig_cfg_hw_trig_en_o => '0',
trig_cfg_reserved_o => (others => '0'),
adc_ctl_update_dly_o => '0',
adc_ctl_update_clk_dly_o => '0',
adc_ctl_update_data_dly_o => '0',
adc_ctl_rst_adcs_o => '0',
adc_ctl_rst_div_adcs_o => '0',
ch0_ctl_clk_chain_dly_o => (others => '0'),
......
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