platform/**/ddr_core/ddr_core.xci: increase TID width to 8

Using cascaded AXI interconnects (as we do) and without any thread IDs
(thread id width = 0 on IP core generation), the downstream AXI interconnect
(2x1) will know which slave component a transaction belongs to, but it will
output, for the upstream AXI interconnext (8x1) the same thread ID for
every transaction. Thus, forwarding every transaction that arrives to the same
slave component.