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Commit 6a783b36 authored by Lucas Russo's avatar Lucas Russo
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wb_fmc516/*: various bugfixes and some cleanup 

data/clock delays are now synchronous to sys_clk
parent e0eec4d3
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Showing with 10111 additions and 2309 deletions
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd
View file @ 6a783b36
......@@ -140,8 +140,9 @@ begin
--idatain => adc_clk_ibufgds,
idatain => adc_clk_i,
dataout => adc_clk_ibufgds_dly,
-- FIX THIS CLOCK!
c => sys_clk_200Mhz_i,
c => sys_clk_i,
--c => sys_clk_200Mhz_i,
--c => adc_clk_bufg,
--ce => adc_clk_dly_pulse_i,
ce => '0',
inc => adc_clk_dly_incdec_i,
......@@ -215,7 +216,7 @@ begin
-- Let the synthesis tools select the best appropriate
-- compensation method (as dictated in Virtex-6 clocking
-- resourses guide page 53, note 2)
COMPENSATION => "ZHOLD",
--COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 4,
--DIVCLK_DIVIDE => 2,
......@@ -312,5 +313,4 @@ begin
adc_clk_bufg_o <= adc_clk_bufg;
adc_clk2x_bufg_o <= adc_clk2x_bufg;
end rtl;
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.vhd
View file @ 6a783b36
......@@ -121,14 +121,14 @@ architecture rtl of fmc516_adc_iface is
--type t_chain_intercon is array (natural range <>) of integer;
-- ADc and Clock chains
signal adc_clk_chain : t_adc_clk_chain_array(c_num_adc_channels-1 downto 0);
signal adc_clk_chain : t_adc_clk_chain_array(c_num_adc_channels-1 downto 0);
-- Fill out the intercon vector. This vector has c_num_data_chains positions
-- and means which clock is connected for each data chain (position index): -1,
-- means not to use this data chain; 0..c_num_clock_chains, means the clock
-- driving this data chain.
constant chain_intercon : t_chain_intercon :=
f_chain_intercon(g_use_clk_chains, g_use_data_chains);
f_generate_chain_intercon(g_use_clk_chains, g_use_data_chains, g_map_clk_data_chains);
-----------------------------
-- Components declaration
......@@ -311,7 +311,7 @@ begin
mmcm_adc_locked_and(i+1) <= mmcm_adc_locked_and(i) and adc_clk_chain(i).mmcm_adc_locked;
end generate;
-- output the MSB of mmcm_adc_locked_and, as it contains the and of all the chain.
-- Output the MSB of mmcm_adc_locked_and, as it contains the and of all the chain.
-- Note, however, that the snsthesis tool will generate an AND tree for all the
-- inputs and a single output (mmcm_adc_locked_and(c_num_clock_chains))
mmcm_adc_locked_o <= mmcm_adc_locked_and(c_num_adc_channels);
......@@ -322,7 +322,7 @@ begin
-- Check if this data chain is to be instanciated
gen_adc_data_chains_check : if chain_intercon(i) /= -1 generate
gen_implicitly_clk_data_map : if f_explicitly_clk_data_map(g_map_clk_data_chains) = false generate
--gen_implicitly_clk_data_map : if f_explicitly_clk_data_map(g_map_clk_data_chains) = false generate
cmp_fmc516_adc_data : fmc516_adc_data
generic map (
g_default_adc_data_delay => g_data_default_dly(i),
......@@ -411,6 +411,9 @@ begin
adc_data_dly_val_o => adc_dly_o(i).adc_data_dly_val,
adc_data_dly_incdec_i => adc_dly_i(i).adc_data_dly_incdec,
adc_data_fe_d1_en_i => adc_dly_ctl_i(i).adc_data_fe_d1_en,
adc_data_fe_d2_en_i => adc_dly_ctl_i(i).adc_data_fe_d2_en,
-----------------------------
-- ADC output signals.
-----------------------------
......@@ -422,7 +425,61 @@ begin
fifo_debug_full_o => fifo_debug_full_o(i),
fifo_debug_empty_o => fifo_debug_empty_o(i)
);
end generate;
--end generate;
--gen_explicitly_clk_data_map : if f_explicitly_clk_data_map(g_map_clk_data_chains) = true generate
-- cmp_fmc516_adc_data : fmc516_adc_data
-- generic map (
-- g_default_adc_data_delay => g_data_default_dly(i),
-- --g_delay_type => "VARIABLE",
-- g_delay_type => g_delay_type,
-- g_sim => g_sim
-- )
-- port map (
-- sys_clk_i => sys_clk_i,
-- sys_clk_200Mhz_i => sys_clk_200Mhz_i,
-- sys_rst_n_i => adc_in_i(i).adc_rst_n,--sys_rst_n_i,
--
-- -----------------------------
-- -- External ports
-- -----------------------------
--
-- -- DDR ADC data channels.
-- adc_data_i => adc_in_i(i).adc_data,
--
-- -----------------------------
-- -- Input Clocks from fmc516_adc_clk signals
-- -----------------------------
-- adc_clk_bufio_i => adc_clk_chain(g_map_clk_data_chains(i)).adc_clk_bufio,
-- adc_clk_bufr_i => adc_clk_chain(g_map_clk_data_chains(i)).adc_clk_bufr,
-- adc_clk_bufg_i => adc_clk_chain(g_map_clk_data_chains(i)).adc_clk_bufg,
-- adc_clk2x_bufg_i => adc_clk_chain(g_map_clk_data_chains(i)).adc_clk2x_bufg,
-- --adc_clk_bufg_rst_n_i => adc_in_i(i).adc_rst_n,
--
-- -----------------------------
-- -- ADC Data Delay signals.
-- -----------------------------
-- -- Pulse this to update the delay value
-- adc_data_dly_pulse_i => adc_dly_i(i).adc_data_dly_pulse,
-- adc_data_dly_val_i => adc_dly_i(i).adc_data_dly_val,
-- adc_data_dly_val_o => adc_dly_o(i).adc_data_dly_val,
-- adc_data_dly_incdec_i => adc_dly_i(i).adc_data_dly_incdec,
--
-- adc_data_fe_d1_en_i => adc_dly_ctl_i(i).adc_data_fe_d1_en,
-- adc_data_fe_d2_en_i => adc_dly_ctl_i(i).adc_data_fe_d2_en,
--
-- -----------------------------
-- -- ADC output signals.
-- -----------------------------
-- adc_data_o => adc_out_o(i).adc_data,
-- adc_data_valid_o => adc_out_o(i).adc_data_valid,
-- adc_clk_o => adc_out_o(i).adc_clk,
-- adc_clk2x_o => adc_out_o(i).adc_clk2x,
-- fifo_debug_valid_o => fifo_debug_valid_o(i),
-- fifo_debug_full_o => fifo_debug_full_o(i),
-- fifo_debug_empty_o => fifo_debug_empty_o(i)
-- );
-- end generate;
end generate;
end generate;
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_pkg.vhd
View file @ 6a783b36
......@@ -84,6 +84,17 @@ package fmc516_pkg is
type t_adc_dly_reg_array is array (natural range<>) of t_adc_dly_reg;
<<<<<<< HEAD
=======
-- ADC falling edge delay control
type t_adc_dly_ctl is record
adc_data_fe_d1_en : std_logic;
adc_data_fe_d2_en : std_logic;
end record;
type t_adc_dly_ctl_array is array (natural range<>) of t_adc_dly_ctl;
>>>>>>> 0caa735... various: bug-fixes: temp-mess 12
type t_adc_out is record
adc_clk : std_logic;
adc_clk2x : std_logic;
......@@ -106,7 +117,7 @@ package fmc516_pkg is
constant default_adc_clk_period_values : t_clk_values_array :=
(4.0, 4.0, 4.0, 4.0);
constant default_clk_use_chain : t_clk_use_chain :=
("0010");
("0011");
constant default_data_use_chain : t_data_use_chain :=
("1111");
-- Fallback to general conflict resolution mode. See chain_intercon function
......@@ -150,6 +161,13 @@ package fmc516_pkg is
function f_explicitly_clk_data_map(map_chain : t_map_clk_data_chain)
return boolean;
-- Wrapper for generating chain_intercon structure. It will decide
-- between explicitly or implicitly mapping for clock/data chains
function f_generate_chain_intercon(clock_chains : std_logic_vector;
data_chains : std_logic_vector;
map_chain : t_map_clk_data_chain)
return t_chain_intercon;
end fmc516_pkg;
......@@ -195,7 +213,7 @@ package body fmc516_pkg is
i := i + 1;
end loop;
-- If there are remaining data chains unclocked, attribute
-- If there are remaining data chains unclocked, assign
-- them to the last usable clock
for i in data_chain_idx to c_num_chains-1 loop
if data_chains(i) = '1' then
......@@ -224,7 +242,7 @@ package body fmc516_pkg is
variable result : boolean := true;
begin
for i in 0 to c_num_chains-1 loop
if map_chain(i) = -1 then
if map_chain(i) < 0 then
result := false;
exit;
end if;
......@@ -240,5 +258,33 @@ package body fmc516_pkg is
return result;
end f_explicitly_clk_data_map;
function f_generate_chain_intercon(clock_chains : std_logic_vector;
data_chains : std_logic_vector;
map_chain : t_map_clk_data_chain)
return t_chain_intercon
is
constant c_num_chains : natural := clock_chains'length;
variable intercon : t_chain_intercon(c_num_chains-1 downto 0);
variable i : natural := 0;
begin
-- Check for the sizes
assert (clock_chains'length = data_chains'length) report
"Vectors clocks and data have different sizes" severity failure;
assert (data_chains'length = map_chain'length) report
"Vectors data and map_clk have different sizes" severity failure;
-- Trust the user mapping...
if f_explicitly_clk_data_map(map_chain) = true then
for i in 0 to c_num_chains-1 loop
intercon(i) := map_chain(i);
end loop;
else --f_explicitly_clk_data_map(map_chain) = false
-- Fallback to implicit policy in order to map clock to data chains
intercon := f_chain_intercon(clock_chains, data_chains);
end if;
return intercon;
end f_generate_chain_intercon;
end fmc516_pkg;
hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd
View file @ 6a783b36
......@@ -560,6 +560,7 @@ architecture rtl of wb_fmc516 is
-- FMC516 Register Wishbone Interface
component wb_fmc516_regs
port (
<<<<<<< HEAD
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
......@@ -575,6 +576,23 @@ architecture rtl of wb_fmc516 is
--wb_clk_i : in std_logic;
regs_i : in t_fmc516_in_registers;
regs_o : out t_fmc516_out_registers
=======
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
--wb_clk_i : in std_logic;
regs_i : in t_fmc516_in_registers;
regs_o : out t_fmc516_out_registers
>>>>>>> 0caa735... various: bug-fixes: temp-mess 12
);
end component;
......@@ -858,6 +876,15 @@ begin
--adc_dly_out(i).adc_data_dly_pulse <= '0';
end generate;
<<<<<<< HEAD
=======
-- ADC falling edge control signal mangling
gen_adc_dly_ctl : for i in 0 to c_num_adc_channels-1 generate
adc_dly_ctl_in(i).adc_data_fe_d1_en <= adc_dly_ctl(i).adc_data_fe_d1_en;
adc_dly_ctl_in(i).adc_data_fe_d2_en <= adc_dly_ctl(i).adc_data_fe_d2_en;
end generate;
>>>>>>> 0caa735... various: bug-fixes: temp-mess 12
-----------------------------
-- Wishbone Delay Register Interface <-> ADC interface (clock + data delays).
-----------------------------
......@@ -866,16 +893,14 @@ begin
-- Capture delay signals (clock + data chains) coming from the Wishbone
-- Register Interface.
-- Idelay "var_loadable" interface
-- CAUTION WITH THE CKOCKS HERE! FIX! Only trust on the data/clock delay
-- clocked by fs_clk(first_used_clk)
gen_adc_dly_var_loadable : for i in 0 to c_num_adc_channels-1 generate
--p_adc_dly : process (sys_clk_i)
p_adc_dly : process (fs_clk(first_used_clk))
p_adc_dly : process (sys_clk_i)
--p_adc_dly : process (fs_clk(first_used_clk))
begin
--if rising_edge(sys_clk_i) then
if rising_edge(fs_clk(first_used_clk)) then
--if sys_rst_sync_n = '0' then
if fs_rst_sync_n(first_used_clk) = '0' then
if rising_edge(sys_clk_i) then
--if rising_edge(fs_clk(first_used_clk)) then
if sys_rst_sync_n = '0' then
--if fs_rst_sync_n(first_used_clk) = '0' then
adc_dly_reg(i).clk_dly_reg <= (others => '0');
--adc_dly_reg(i).clk_dly_reg <= std_logic_vector(to_unsigned(default_clk_dly(i),
-- adc_dly_reg(i).clk_dly_reg'length));
......@@ -902,16 +927,14 @@ begin
end generate;
-- Idelay "variable" interface
-- CAUTION WITH THE CKOCKS HERE! FIX! Only trust on the data/clock delay
-- clocked by fs_clk(first_used_clk)
gen_adc_dly_variable : for i in 0 to c_num_adc_channels-1 generate
--p_adc_dly : process (sys_clk_i)
p_adc_dly : process (fs_clk(first_used_clk))
p_adc_dly : process (sys_clk_i)
--p_adc_dly : process (fs_clk(first_used_clk))
begin
--if rising_edge(sys_clk_i) then
if rising_edge(fs_clk(first_used_clk)) then
--if sys_rst_sync_n = '0' then
if fs_rst_sync_n(first_used_clk) = '0' then
if rising_edge(sys_clk_i) then
--if rising_edge(fs_clk(first_used_clk)) then
if sys_rst_sync_n = '0' then
--if fs_rst_sync_n(first_used_clk) = '0' then
adc_dly_reg_pulse_clk_int(i) <= '0';
adc_dly_reg_pulse_data_int(i) <= '0';
adc_dly_reg(i).clk_dly_incdec <= '0';
......@@ -1071,9 +1094,6 @@ begin
extended_o => adc_clk_div_rst_int
);
-- DEBUG. Something wrong with the register interface?
--adc_clk_div_rst_int_p <= '0';
-- ADC div resets logic
cmp_clk_div_rst_obufds : obufds
generic map(
......@@ -1082,7 +1102,6 @@ begin
port map (
O => adc_clk_div_rst_p_o,
OB => adc_clk_div_rst_n_o,
--I => adc_clk_div_rst_int_p
I => adc_clk_div_rst_int
);
......@@ -1100,9 +1119,7 @@ begin
extended_o => fmc_reset_adcs_int
);
-- DEBUG ONLY! FIX!
fmc_reset_adcs_n_o <= not fmc_reset_adcs_int;
--fmc_reset_adcs_n_o <= not regs_out.adc_ctl_rst_adcs_o;
end generate;
-----------------------------
......
hdl/modules/custom_wishbone/wb_fmc516/wbgen/build_wb.sh
View file @ 6a783b36
#!/bin/bash
wbgen2 -V wb_fmc516_regs.vhd -H record -p wb_fmc516_regs_pkg.vhd -K ../../../../sim/regs/wb_fmc516_regs.vh -s struct -C fmc516_regs.h -D doc/fmc516_regs_wb.html -f HTML wb_fmc516_regs.wb
wbgen2 -V wb_fmc516_regs.vhd -H record -p wb_fmc516_regs_pkg.vhd -K ../../../../sim/regs/wb_fmc516_regs.vh -s struct -C fmc516_regs.h -f html -D doc/fmc516_regs_wb.html wb_fmc516_regs.wb
hdl/modules/custom_wishbone/wb_fmc516/wbgen/fmc516_regs.h
View file @ 6a783b36
......@@ -3,7 +3,7 @@
* File : fmc516_regs.h
* Author : auto-generated by wbgen2 from wb_fmc516_regs.wb
* Created : Fri Mar 15 10:56:52 2013
* Created : Mon Mar 18 21:51:29 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
......
hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.wb
View file @ 6a783b36
......@@ -257,7 +257,7 @@ peripheral {
prefix = "update_clk_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -271,7 +271,7 @@ peripheral {
prefix = "update_data_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -349,7 +349,7 @@ peripheral {
description = "ADC clock chain delay";
prefix = "clk_chain_dly";
type = SLV;
clock = "fs_clk_i";
--clock = "fs_clk_i";
size = 5;
align = 8;
access_bus = READ_WRITE;
......@@ -373,7 +373,7 @@ peripheral {
description = "ADC data chain delay";
prefix = "data_chain_dly";
type = SLV;
clock = "fs_clk_i";
--clock = "fs_clk_i";
size = 5;
align = 8;
access_bus = READ_WRITE;
......@@ -400,7 +400,7 @@ peripheral {
prefix = "inc_clk_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -415,7 +415,7 @@ peripheral {
prefix = "dec_clk_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -439,7 +439,7 @@ peripheral {
prefix = "inc_data_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -454,7 +454,7 @@ peripheral {
prefix = "dec_data_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -507,7 +507,7 @@ peripheral {
description = "ADC clock chain delay";
prefix = "clk_chain_dly";
type = SLV;
clock = "fs_clk_i";
--clock = "fs_clk_i";
size = 5;
align = 8;
access_bus = READ_WRITE;
......@@ -531,7 +531,7 @@ peripheral {
description = "ADC data chain delay";
prefix = "data_chain_dly";
type = SLV;
clock = "fs_clk_i";
--clock = "fs_clk_i";
size = 5;
align = 8;
access_bus = READ_WRITE;
......@@ -558,7 +558,7 @@ peripheral {
prefix = "inc_clk_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -573,7 +573,7 @@ peripheral {
prefix = "dec_clk_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -597,7 +597,7 @@ peripheral {
prefix = "inc_data_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -612,7 +612,7 @@ peripheral {
prefix = "dec_data_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -665,7 +665,7 @@ peripheral {
description = "ADC clock chain delay";
prefix = "clk_chain_dly";
type = SLV;
clock = "fs_clk_i";
--clock = "fs_clk_i";
size = 5;
align = 8;
access_bus = READ_WRITE;
......@@ -689,7 +689,7 @@ peripheral {
description = "ADC data chain delay";
prefix = "data_chain_dly";
type = SLV;
clock = "fs_clk_i";
--clock = "fs_clk_i";
size = 5;
align = 8;
access_bus = READ_WRITE;
......@@ -716,7 +716,7 @@ peripheral {
prefix = "inc_clk_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -731,7 +731,7 @@ peripheral {
prefix = "dec_clk_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -755,7 +755,7 @@ peripheral {
prefix = "inc_data_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -770,7 +770,7 @@ peripheral {
prefix = "dec_data_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -823,7 +823,7 @@ peripheral {
description = "ADC clock chain delay";
prefix = "clk_chain_dly";
type = SLV;
clock = "fs_clk_i";
--clock = "fs_clk_i";
size = 5;
align = 8;
access_bus = READ_WRITE;
......@@ -847,7 +847,7 @@ peripheral {
description = "ADC data chain delay";
prefix = "data_chain_dly";
type = SLV;
clock = "fs_clk_i";
--clock = "fs_clk_i";
size = 5;
align = 8;
access_bus = READ_WRITE;
......@@ -874,7 +874,7 @@ peripheral {
prefix = "inc_clk_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -889,7 +889,7 @@ peripheral {
prefix = "dec_clk_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -913,7 +913,7 @@ peripheral {
prefix = "inc_data_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -928,7 +928,7 @@ peripheral {
prefix = "dec_data_chain_dly";
-- Pulse to start
type = MONOSTABLE;
clock = "fs_clk_i";
--clock = "fs_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......
hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd
View file @ 6a783b36
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wb_fmc516_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from wb_fmc516_regs.wb
-- Created : Fri Mar 15 10:56:52 2013
-- Created : Mon Mar 18 21:51:29 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
......
hdl/syn/dbe_bpm_fmc516/make_output
View file @ 6a783b36
This diff is collapsed.
hdl/top/ml_605/dbe_bpm_fmc516/chipscope.cpj
View file @ 6a783b36
#ChipScope Pro Analyzer Project File, Version 3.0
#Fri Mar 15 11:37:52 BRT 2013
#Mon Mar 18 12:53:11 BRT 2013
avoidUserRegDevice1=2,3,4
deviceChain.deviceName0=System_ACE_CF
deviceChain.deviceName1=XC6VLX240T
......@@ -145,8 +145,8 @@ unit.1.0.plotBusName1=fmc516_adc_ch2
unit.1.0.plotBusName10=fmc_lmk_lock
unit.1.0.plotBusName11=fmc_mmcm_lock
unit.1.0.plotBusName12=fmc_rst_adcs_n
unit.1.0.plotBusName2=fmc516_ch1_clk_load
unit.1.0.plotBusName3=fmc516_ch1_clk_dly
unit.1.0.plotBusName2=fmc516_ch1_clk_dly
unit.1.0.plotBusName3=fmc516_ch1_clk_load
unit.1.0.plotBusName4=fmc516_ch1_data_dly
unit.1.0.plotBusName5=fmc516_ch1_data_load
unit.1.0.plotBusName6=fmc516_debug_dull
......@@ -157,11 +157,11 @@ unit.1.0.plotBusX=fmc516_debug_dull
unit.1.0.plotBusY=fmc_rst_adcs_n
unit.1.0.plotDataTimeMode=1
unit.1.0.plotDisplayMode=line
unit.1.0.plotMaxX=0.0
unit.1.0.plotMaxY=0.0
unit.1.0.plotMinX=0.0
unit.1.0.plotMinY=0.0
unit.1.0.plotSelectedBus=1
unit.1.0.plotMaxX=503.3853658536585
unit.1.0.plotMaxY=3203.0
unit.1.0.plotMinX=387.52682926829266
unit.1.0.plotMinY=-3031.0
unit.1.0.plotSelectedBus=3
unit.1.0.port.-1.b.0.alias=fmc516_adc_ch1
unit.1.0.port.-1.b.0.channellist=16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
unit.1.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
......@@ -237,7 +237,7 @@ unit.1.0.port.-1.b.2.channellist=37 38 39 40 41
unit.1.0.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.b.2.name=DataPort
unit.1.0.port.-1.b.2.orderindex=-1
unit.1.0.port.-1.b.2.radix=Hex
unit.1.0.port.-1.b.2.radix=Unsigned
unit.1.0.port.-1.b.2.signedOffset=0.0
unit.1.0.port.-1.b.2.signedPrecision=0
unit.1.0.port.-1.b.2.signedScaleFactor=1.0
......@@ -265,7 +265,7 @@ unit.1.0.port.-1.b.4.channellist=32 33 34 35 36
unit.1.0.port.-1.b.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.b.4.name=DataPort
unit.1.0.port.-1.b.4.orderindex=-1
unit.1.0.port.-1.b.4.radix=Hex
unit.1.0.port.-1.b.4.radix=Unsigned
unit.1.0.port.-1.b.4.signedOffset=0.0
unit.1.0.port.-1.b.4.signedPrecision=0
unit.1.0.port.-1.b.4.signedScaleFactor=1.0
......@@ -530,22 +530,22 @@ unit.1.0.port.-1.s.16.alias=
unit.1.0.port.-1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.16.name=DataPort[16]
unit.1.0.port.-1.s.16.orderindex=-1
unit.1.0.port.-1.s.16.visible=0
unit.1.0.port.-1.s.16.visible=1
unit.1.0.port.-1.s.17.alias=
unit.1.0.port.-1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.17.name=DataPort[17]
unit.1.0.port.-1.s.17.orderindex=-1
unit.1.0.port.-1.s.17.visible=0
unit.1.0.port.-1.s.17.visible=1
unit.1.0.port.-1.s.18.alias=
unit.1.0.port.-1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.18.name=DataPort[18]
unit.1.0.port.-1.s.18.orderindex=-1
unit.1.0.port.-1.s.18.visible=0
unit.1.0.port.-1.s.18.visible=1
unit.1.0.port.-1.s.19.alias=
unit.1.0.port.-1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.19.name=DataPort[19]
unit.1.0.port.-1.s.19.orderindex=-1
unit.1.0.port.-1.s.19.visible=0
unit.1.0.port.-1.s.19.visible=1
unit.1.0.port.-1.s.2.alias=
unit.1.0.port.-1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.2.name=DataPort[2]
......@@ -555,52 +555,52 @@ unit.1.0.port.-1.s.20.alias=
unit.1.0.port.-1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.20.name=DataPort[20]
unit.1.0.port.-1.s.20.orderindex=-1
unit.1.0.port.-1.s.20.visible=0
unit.1.0.port.-1.s.20.visible=1
unit.1.0.port.-1.s.21.alias=
unit.1.0.port.-1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.21.name=DataPort[21]
unit.1.0.port.-1.s.21.orderindex=-1
unit.1.0.port.-1.s.21.visible=0
unit.1.0.port.-1.s.21.visible=1
unit.1.0.port.-1.s.22.alias=
unit.1.0.port.-1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.22.name=DataPort[22]
unit.1.0.port.-1.s.22.orderindex=-1
unit.1.0.port.-1.s.22.visible=0
unit.1.0.port.-1.s.22.visible=1
unit.1.0.port.-1.s.23.alias=
unit.1.0.port.-1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.23.name=DataPort[23]
unit.1.0.port.-1.s.23.orderindex=-1
unit.1.0.port.-1.s.23.visible=0
unit.1.0.port.-1.s.23.visible=1
unit.1.0.port.-1.s.24.alias=
unit.1.0.port.-1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.24.name=DataPort[24]
unit.1.0.port.-1.s.24.orderindex=-1
unit.1.0.port.-1.s.24.visible=0
unit.1.0.port.-1.s.24.visible=1
unit.1.0.port.-1.s.25.alias=
unit.1.0.port.-1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.25.name=DataPort[25]
unit.1.0.port.-1.s.25.orderindex=-1
unit.1.0.port.-1.s.25.visible=0
unit.1.0.port.-1.s.25.visible=1
unit.1.0.port.-1.s.26.alias=
unit.1.0.port.-1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.26.name=DataPort[26]
unit.1.0.port.-1.s.26.orderindex=-1
unit.1.0.port.-1.s.26.visible=0
unit.1.0.port.-1.s.26.visible=1
unit.1.0.port.-1.s.27.alias=
unit.1.0.port.-1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.27.name=DataPort[27]
unit.1.0.port.-1.s.27.orderindex=-1
unit.1.0.port.-1.s.27.visible=0
unit.1.0.port.-1.s.27.visible=1
unit.1.0.port.-1.s.28.alias=
unit.1.0.port.-1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.28.name=DataPort[28]
unit.1.0.port.-1.s.28.orderindex=-1
unit.1.0.port.-1.s.28.visible=0
unit.1.0.port.-1.s.28.visible=1
unit.1.0.port.-1.s.29.alias=
unit.1.0.port.-1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.29.name=DataPort[29]
unit.1.0.port.-1.s.29.orderindex=-1
unit.1.0.port.-1.s.29.visible=0
unit.1.0.port.-1.s.29.visible=1
unit.1.0.port.-1.s.3.alias=
unit.1.0.port.-1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.3.name=DataPort[3]
......@@ -610,12 +610,12 @@ unit.1.0.port.-1.s.30.alias=
unit.1.0.port.-1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.30.name=DataPort[30]
unit.1.0.port.-1.s.30.orderindex=-1
unit.1.0.port.-1.s.30.visible=0
unit.1.0.port.-1.s.30.visible=1
unit.1.0.port.-1.s.31.alias=
unit.1.0.port.-1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.31.name=DataPort[31]
unit.1.0.port.-1.s.31.orderindex=-1
unit.1.0.port.-1.s.31.visible=0
unit.1.0.port.-1.s.31.visible=1
unit.1.0.port.-1.s.32.alias=
unit.1.0.port.-1.s.32.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.0.port.-1.s.32.name=DataPort[32]
......@@ -1708,7 +1708,7 @@ unit.1.0.waveform.posn.0.radix=1
unit.1.0.waveform.posn.0.type=bus
unit.1.0.waveform.posn.1.channel=2147483646
unit.1.0.waveform.posn.1.name=fmc516_ch1_clk_dly
unit.1.0.waveform.posn.1.radix=1
unit.1.0.waveform.posn.1.radix=4
unit.1.0.waveform.posn.1.type=bus
unit.1.0.waveform.posn.10.channel=2147483646
unit.1.0.waveform.posn.10.name=fmc_mmcm_lock
......@@ -1795,7 +1795,7 @@ unit.1.0.waveform.posn.123.channel=127
unit.1.0.waveform.posn.123.name=DataP
unit.1.0.waveform.posn.2.channel=2147483646
unit.1.0.waveform.posn.2.name=fmc516_ch1_data_dly
unit.1.0.waveform.posn.2.radix=1
unit.1.0.waveform.posn.2.radix=4
unit.1.0.waveform.posn.2.type=bus
unit.1.0.waveform.posn.3.channel=2147483646
unit.1.0.waveform.posn.3.name=fmc516_adc_ch1
......
hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf
View file @ 6a783b36
......@@ -208,46 +208,46 @@ TIMEGRP "TNM_ADC_DATA_3" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk3_p_i"
# Group all IDELAY-related blocks to use a single IDELAYCTRL
INST "*cmp_fmc516_adc_iface/cmp_idelayctrl" IODELAY_GROUP = adc_idelay;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[?].*.*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IODELAY_GROUP = adc_idelay;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[?].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IODELAY_GROUP = adc_idelay;
INST "*cmp_fmc516_adc_iface/gen_clock_chains[?].*.*/cmp_ibufds_clk_iodelay" IODELAY_GROUP = adc_idelay;
# Overrides default_delay hdl parameter.
# For Virtex-6: Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9;
# Overrides default_delay hdl parameter
INST "*cmp_fmc516_adc_iface/gen_clock_chains[0].*.*/cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5;
......
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