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Beam Positoning Monitor - Gateware
Commits
e0eec4d3
Commit
e0eec4d3
authored
Mar 19, 2013
by
Lucas Russo
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testbench/*/wb_fmc516/*: simple register addressing test
parent
fd63d6f8
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6 changed files
with
680 additions
and
97 deletions
+680
-97
wb_fmc516_regs.vh
hdl/sim/regs/wb_fmc516_regs.vh
+10
-8
wishbone_test_master.v
hdl/sim/wishbone_test_master.v
+7
-6
Makefile
hdl/testbench/wishbone/wb_fmc516_test/verilog/Makefile
+461
-2
isim_cmd
hdl/testbench/wishbone/wb_fmc516_test/verilog/isim_cmd
+1
-1
wave.wcfg
hdl/testbench/wishbone/wb_fmc516_test/verilog/wave.wcfg
+99
-15
wb_fmc516_tb.v
hdl/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v
+102
-65
No files found.
hdl/sim/regs/wb_fmc516_regs.vh
View file @
e0eec4d3
...
...
@@ -41,14 +41,16 @@
`define FMC516_ADC_STA_ADC_PKT_SIZE_OFFSET 16
`define FMC516_ADC_STA_ADC_PKT_SIZE 32'hffff0000
`define ADDR_FMC516_ADC_CTL 6'h10
`define FMC516_ADC_CTL_UPDATE_DLY_OFFSET 0
`define FMC516_ADC_CTL_UPDATE_DLY 32'h00000001
`define FMC516_ADC_CTL_RST_ADCS_OFFSET 1
`define FMC516_ADC_CTL_RST_ADCS 32'h00000002
`define FMC516_ADC_CTL_RST_DIV_ADCS_OFFSET 2
`define FMC516_ADC_CTL_RST_DIV_ADCS 32'h00000004
`define FMC516_ADC_CTL_RESERVED_OFFSET 3
`define FMC516_ADC_CTL_RESERVED 32'hfffffff8
`define FMC516_ADC_CTL_UPDATE_CLK_DLY_OFFSET 0
`define FMC516_ADC_CTL_UPDATE_CLK_DLY 32'h00000001
`define FMC516_ADC_CTL_UPDATE_DATA_DLY_OFFSET 1
`define FMC516_ADC_CTL_UPDATE_DATA_DLY 32'h00000002
`define FMC516_ADC_CTL_RST_ADCS_OFFSET 2
`define FMC516_ADC_CTL_RST_ADCS 32'h00000004
`define FMC516_ADC_CTL_RST_DIV_ADCS_OFFSET 3
`define FMC516_ADC_CTL_RST_DIV_ADCS 32'h00000008
`define FMC516_ADC_CTL_RESERVED_OFFSET 4
`define FMC516_ADC_CTL_RESERVED 32'hfffffff0
`define ADDR_FMC516_CH0_STA 6'h14
`define FMC516_CH0_STA_VAL_OFFSET 0
`define FMC516_CH0_STA_VAL 32'h0000ffff
...
...
hdl/sim/wishbone_test_master.v
View file @
e0eec4d3
...
...
@@ -38,11 +38,11 @@ module WB_TEST_MASTER(
reg
[
`WB_BWSEL_WIDTH
-
1
:
0
]
wb_bwsel
=
0
;
wire
[
`WB_DATA_BUS_WIDTH
-
1
:
0
]
wb_data_i
;
wire
wb_ack_i
;
reg
wb_cyc
=
0
;
reg
wb_stb
=
0
;
reg
wb_we
=
0
;
//reg
wb_rst = 0;
//reg
wb_clk = 1;
reg
wb_cyc
=
0
;
reg
wb_stb
=
0
;
reg
wb_we
=
0
;
//reg
wb_rst = 0;
//reg
wb_clk = 1;
input
wb_clk
;
reg
wb_tb_verbose
=
1
;
...
...
@@ -104,7 +104,8 @@ module WB_TEST_MASTER(
wb_stb
<=
1
;
wb_cyc
<=
1
;
wb_addr
<=
{
2'b00
,
addr
[
31
:
2
]
};
//wb_addr <= {2'b00, addr[31:2]};
wb_addr
<=
addr
;
wb_we
<=
rw
;
if
(
rw
)
begin
...
...
hdl/testbench/wishbone/wb_fmc516_test/verilog/Makefile
View file @
e0eec4d3
This diff is collapsed.
Click to expand it.
hdl/testbench/wishbone/wb_fmc516_test/verilog/isim_cmd
View file @
e0eec4d3
run
5
000 ns
run
10
000 ns
hdl/testbench/wishbone/wb_fmc516_test/verilog/wave.wcfg
View file @
e0eec4d3
...
...
@@ -15,6 +15,7 @@
<top_module
name=
"std_logic_1164"
/>
<top_module
name=
"std_logic_arith"
/>
<top_module
name=
"std_logic_signed"
/>
<top_module
name=
"std_logic_unsigned"
/>
<top_module
name=
"textio"
/>
<top_module
name=
"vcomponents"
/>
<top_module
name=
"vital_primitives"
/>
...
...
@@ -25,10 +26,11 @@
<top_module
name=
"wb_stream_generic_pkg"
/>
<top_module
name=
"wb_stream_pkg"
/>
<top_module
name=
"wishbone_pkg"
/>
<top_module
name=
"wr_fabric_pkg"
/>
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize
size=
"1
49
"
/>
<WVObjectSize
size=
"1
68
"
/>
<wvobject
fp_name=
"divider142"
type=
"divider"
>
<obj_property
name=
"label"
>
wb_fmc516_tb
</obj_property>
<obj_property
name=
"DisplayName"
>
label
</obj_property>
...
...
@@ -47,10 +49,6 @@
<obj_property
name=
"ElementShortName"
>
clk_sys
</obj_property>
<obj_property
name=
"ObjectShortName"
>
clk_sys
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/sys_spi_data_reg"
type=
"logic"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
sys_spi_data_reg
</obj_property>
<obj_property
name=
"ObjectShortName"
>
sys_spi_data_reg
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/sys_spi_data_en"
type=
"logic"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
sys_spi_data_en
</obj_property>
<obj_property
name=
"ObjectShortName"
>
sys_spi_data_en
</obj_property>
...
...
@@ -370,10 +368,6 @@
<obj_property
name=
"ElementShortName"
>
pad_miso_i
</obj_property>
<obj_property
name=
"ObjectShortName"
>
pad_miso_i
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_fmc_spi/pad_miosio_b"
type=
"logic"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
pad_miosio_b
</obj_property>
<obj_property
name=
"ObjectShortName"
>
pad_miosio_b
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/go"
type=
"logic"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
go
</obj_property>
<obj_property
name=
"ObjectShortName"
>
go
</obj_property>
...
...
@@ -659,6 +653,7 @@
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_slave_adapter/sl_adr_i"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
sl_adr_i[31:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
sl_adr_i[31:0]
</obj_property>
<obj_property
name=
"Radix"
>
HEXRADIX
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_slave_adapter/sl_sel_i"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
sl_sel_i[3:0]
</obj_property>
...
...
@@ -704,12 +699,6 @@
<obj_property
name=
"ElementShortName"
>
sl_dat_i[31:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
sl_dat_i[31:0]
</obj_property>
</wvobject>
<wvobject
fp_name=
"divider161"
type=
"divider"
>
<obj_property
name=
"label"
>
interconnect
</obj_property>
<obj_property
name=
"DisplayName"
>
label
</obj_property>
<obj_property
name=
"BkColor"
>
128 128 255
</obj_property>
<obj_property
name=
"TextColor"
>
230 230 230
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_interconnect/slave_i"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
slave_i[0:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
slave_i[0:0]
</obj_property>
...
...
@@ -742,4 +731,99 @@
<obj_property
name=
"ElementShortName"
>
cbar_master_out[6:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
cbar_master_out[6:0]
</obj_property>
</wvobject>
<wvobject
fp_name=
"divider169"
type=
"divider"
>
<obj_property
name=
"label"
>
fmc516_regs
</obj_property>
<obj_property
name=
"DisplayName"
>
label
</obj_property>
<obj_property
name=
"BkColor"
>
128 128 255
</obj_property>
<obj_property
name=
"TextColor"
>
230 230 230
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/adc_dly_reg"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
adc_dly_reg[3:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
adc_dly_reg[3:0]
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/adc_dly_reg_pulse_clk_int"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
adc_dly_reg_pulse_clk_int[3:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
adc_dly_reg_pulse_clk_int[3:0]
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/adc_dly_reg_pulse_data_int"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
adc_dly_reg_pulse_data_int[3:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
adc_dly_reg_pulse_data_int[3:0]
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/adc_out"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
adc_out[3:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
adc_out[3:0]
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/adc_dly_out"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
adc_dly_out[3:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
adc_dly_out[3:0]
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/adc_dly_in"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
adc_dly_in[3:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
adc_dly_in[3:0]
</obj_property>
</wvobject>
<wvobject
fp_name=
"divider207"
type=
"divider"
>
<obj_property
name=
"label"
>
fmc516_regs_in
</obj_property>
<obj_property
name=
"DisplayName"
>
label
</obj_property>
<obj_property
name=
"BkColor"
>
128 128 255
</obj_property>
<obj_property
name=
"TextColor"
>
230 230 230
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/rst_n_i"
type=
"logic"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
rst_n_i
</obj_property>
<obj_property
name=
"ObjectShortName"
>
rst_n_i
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/clk_sys_i"
type=
"logic"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
clk_sys_i
</obj_property>
<obj_property
name=
"ObjectShortName"
>
clk_sys_i
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/wb_adr_i"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
wb_adr_i[3:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
wb_adr_i[3:0]
</obj_property>
<obj_property
name=
"Radix"
>
HEXRADIX
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/wb_dat_i"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
wb_dat_i[31:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
wb_dat_i[31:0]
</obj_property>
<obj_property
name=
"Radix"
>
HEXRADIX
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/wb_dat_o"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
wb_dat_o[31:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
wb_dat_o[31:0]
</obj_property>
<obj_property
name=
"Radix"
>
HEXRADIX
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/wb_cyc_i"
type=
"logic"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
wb_cyc_i
</obj_property>
<obj_property
name=
"ObjectShortName"
>
wb_cyc_i
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/wb_sel_i"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
wb_sel_i[3:0]
</obj_property>
<obj_property
name=
"ObjectShortName"
>
wb_sel_i[3:0]
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/wb_stb_i"
type=
"logic"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
wb_stb_i
</obj_property>
<obj_property
name=
"ObjectShortName"
>
wb_stb_i
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/wb_we_i"
type=
"logic"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
wb_we_i
</obj_property>
<obj_property
name=
"ObjectShortName"
>
wb_we_i
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/wb_ack_o"
type=
"logic"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
wb_ack_o
</obj_property>
<obj_property
name=
"ObjectShortName"
>
wb_ack_o
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/wb_stall_o"
type=
"logic"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
wb_stall_o
</obj_property>
<obj_property
name=
"ObjectShortName"
>
wb_stall_o
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/fs_clk_i"
type=
"logic"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
fs_clk_i
</obj_property>
<obj_property
name=
"ObjectShortName"
>
fs_clk_i
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/regs_i"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
regs_i
</obj_property>
<obj_property
name=
"ObjectShortName"
>
regs_i
</obj_property>
</wvobject>
<wvobject
fp_name=
"/wb_fmc516_tb/cmp_wb_fmc516/cmp_wb_fmc516_port/regs_o"
type=
"array"
db_ref_id=
"1"
>
<obj_property
name=
"ElementShortName"
>
regs_o
</obj_property>
<obj_property
name=
"ObjectShortName"
>
regs_o
</obj_property>
</wvobject>
</wave_config>
hdl/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v
View file @
e0eec4d3
This diff is collapsed.
Click to expand it.
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