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Commit fd63d6f8 authored by Lucas Russo's avatar Lucas Russo
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wb_fmc516/*: various fixes and initial ddr alignment

parent 551131ce
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Showing with 991 additions and 2209 deletions
hdl/modules/custom_wishbone/custom_wishbone_pkg.vhd
View file @ fd63d6f8
......@@ -480,6 +480,8 @@ package custom_wishbone_pkg is
wbs_err_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_rty_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
adc_dly_reg_debug_o : out t_adc_dly_reg_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
......@@ -622,6 +624,8 @@ package custom_wishbone_pkg is
wbs_source_i : in t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
wbs_source_o : out t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
adc_dly_reg_debug_o : out t_adc_dly_reg_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd
View file @ fd63d6f8
......@@ -217,22 +217,22 @@ begin
-- resourses guide page 53, note 2)
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
--DIVCLK_DIVIDE => 4,
DIVCLK_DIVIDE => 1,
--CLKFBOUT_MULT_F => 12.000,
CLKFBOUT_MULT_F => 6.000,
DIVCLK_DIVIDE => 4,
--DIVCLK_DIVIDE => 2,
CLKFBOUT_MULT_F => 12.000,
--CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
-- adc clock
--CLKOUT0_DIVIDE_F => 3.000,
CLKOUT0_DIVIDE_F => 6.000,
CLKOUT0_DIVIDE_F => 3.000,
--CLKOUT0_DIVIDE_F => 4.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
-- 2x adc clock. This should not be 2x. FIX
--CLKOUT1_DIVIDE => 2,
--CLKOUT1_DIVIDE => 3,
CLKOUT1_DIVIDE => 6,
CLKOUT1_DIVIDE => 3,
--CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd
View file @ fd63d6f8
......@@ -100,6 +100,10 @@ architecture rtl of fmc516_adc_data is
signal adc_data_ff_d2 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_bufg_sync : std_logic_vector(c_num_adc_bits-1 downto 0);
-- Delay signals
signal adc_data_re : std_logic_vector(c_num_adc_bits-1 downto 0); -- ADC data rising edge
signal adc_data_fe : std_logic_vector(c_num_adc_bits-1 downto 0); -- ADC data falling edge
-- FIFO signals
signal adc_fifo_full : std_logic;
signal adc_fifo_wr : std_logic;
......@@ -223,14 +227,19 @@ begin
end generate;
-- DDR to SDR. This component is clocked with BUFIO clock for
-- maximum performance
-- maximum performance.
-- Note that the rising and falling edges are inverted to each other
-- as the ISLA216 codes the that in following way:
--
-- ODD1a EVEN1a ODD2a EVEN2a ...
-- ris fal ris fal
cmp_iddr : iddr
generic map(
DDR_CLK_EDGE => "SAME_EDGE_PIPELINED"
)
port map(
q1 => adc_data_sdr(2*i),
q2 => adc_data_sdr(2*i+1),
q1 => adc_data_sdr(2*i+1),--adc_data_re(i),
q2 => adc_data_sdr(2*i),--adc_data_fe(i),
c => adc_clk_bufio_i,
--c => adc_clk_bufr_i,
ce => '1',
......@@ -243,6 +252,10 @@ begin
-- Output a single value to adc_data_dly_val_o
adc_data_dly_val_o <= adc_data_dly_val_int(4 downto 0);
--gen_adc_data_dly_comp : for i in 0 to (c_num_adc_bits/2)-1 generate
--
--end generate;
-- Some FF to solve timing problem
p_adc_data_ff : process(adc_clk_bufr_i)
begin
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_pkg.vhd
View file @ fd63d6f8
......@@ -110,8 +110,10 @@ package fmc516_pkg is
constant default_data_use_chain : t_data_use_chain :=
("1111");
-- Fallback to general conflict resolution mode. See chain_intercon function
--constant default_map_clk_data_chain : t_map_clk_data_chain :=
-- (-1, -1, -1, -1);
constant default_map_clk_data_chain : t_map_clk_data_chain :=
(-1, -1, -1, -1);
(1, 0, 0, 1);
-- dummy values for fmc516_adc_iface generic definitions
-- Warning: all clocks are null here! Should be modified
......
hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd
View file @ fd63d6f8
......@@ -197,7 +197,7 @@ port
wbs_err_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_rty_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
adc_dly_reg_debug_o : out t_adc_dly_array;
adc_dly_reg_debug_o : out t_adc_dly_reg_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
......@@ -239,7 +239,7 @@ architecture rtl of wb_fmc516 is
-- Number of ADC channels
--constant c_num_channels : natural := 4;
-- Numbert of bits in Wishbone register interface
constant c_periph_addr_size : natural := 4;
constant c_periph_addr_size : natural := 6;
constant first_used_clk : natural := f_first_used_clk(g_use_clk_chains);
-----------------------------
......@@ -846,10 +846,10 @@ begin
-- ADC dly signal mangling
gen_adc_dly_in : for i in 0 to c_num_adc_channels-1 generate
adc_dly_in(i).adc_clk_dly_pulse <= regs_out.adc_ctl_update_dly_o or adc_dly_reg_pulse_clk_int(i);
adc_dly_in(i).adc_clk_dly_pulse <= regs_out.adc_ctl_update_clk_dly_o or adc_dly_reg_pulse_clk_int(i);
adc_dly_in(i).adc_clk_dly_val <= adc_dly_reg(i).clk_dly_reg;
adc_dly_in(i).adc_clk_dly_incdec <= adc_dly_reg(i).clk_dly_incdec;
adc_dly_in(i).adc_data_dly_pulse <= regs_out.adc_ctl_update_dly_o or adc_dly_reg_pulse_data_int(i);
adc_dly_in(i).adc_data_dly_pulse <= regs_out.adc_ctl_update_data_dly_o or adc_dly_reg_pulse_data_int(i);
adc_dly_in(i).adc_data_dly_val <= adc_dly_reg(i).data_dly_reg;
adc_dly_in(i).adc_data_dly_incdec <= adc_dly_reg(i).data_dly_incdec;
......@@ -876,12 +876,12 @@ begin
if rising_edge(fs_clk(first_used_clk)) then
--if sys_rst_sync_n = '0' then
if fs_rst_sync_n(first_used_clk) = '0' then
--adc_dly_reg(i).clk_dly_reg <= (others => '0');
adc_dly_reg(i).clk_dly_reg <= std_logic_vector(to_unsigned(default_clk_dly(i),
adc_dly_reg(i).clk_dly_reg'length));
--adc_dly_reg(i).data_dly_reg <= (others => '0');
adc_dly_reg(i).data_dly_reg <= std_logic_vector(to_unsigned(default_data_dly(i),
adc_dly_reg(i).data_dly_reg'length));
adc_dly_reg(i).clk_dly_reg <= (others => '0');
--adc_dly_reg(i).clk_dly_reg <= std_logic_vector(to_unsigned(default_clk_dly(i),
-- adc_dly_reg(i).clk_dly_reg'length));
adc_dly_reg(i).data_dly_reg <= (others => '0');
--adc_dly_reg(i).data_dly_reg <= std_logic_vector(to_unsigned(default_data_dly(i),
-- adc_dly_reg(i).data_dly_reg'length));
else
-- write to clock register delay
if adc_dly_reg(i).clk_load = '1' then
......@@ -993,8 +993,8 @@ begin
generic map(
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device => g_fpga_device,
--g_delay_type => "VAR_LOADABLE",
g_delay_type => "VARIABLE",
g_delay_type => "VAR_LOADABLE",
--g_delay_type => "VARIABLE",
g_adc_clk_period_values => g_adc_clk_period_values,
g_use_clk_chains => g_use_clk_chains,
g_use_data_chains => g_use_data_chains,
......
hdl/modules/custom_wishbone/wb_fmc516/xwb_fmc516.vhd
View file @ fd63d6f8
......@@ -167,7 +167,7 @@ port
wbs_source_i : in t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
wbs_source_o : out t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
adc_dly_reg_debug_o : out t_adc_dly_array;
adc_dly_reg_debug_o : out t_adc_dly_reg_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
......
hdl/syn/dbe_bpm_fmc516/make_output
View file @ fd63d6f8
This diff is collapsed.
hdl/top/ml_605/dbe_bpm_fmc516/chipscope.cpj
View file @ fd63d6f8
This diff is collapsed.
hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd
View file @ fd63d6f8
......@@ -344,7 +344,7 @@ architecture rtl of dbe_bpm_fmc516 is
signal fmc516_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_reg_debug_int : t_adc_dly_array;
signal adc_dly_reg_debug_int : t_adc_dly_reg_array(c_num_adc_channels-1 downto 0);
signal sys_spi_clk_int : std_logic;
--signal sys_spi_data_int : std_logic;
......@@ -1099,10 +1099,11 @@ begin
-- wbs_fmc516_out_array(0).dat;
--TRIG_ILA0_1 <= fmc516_adc_data(15 downto 0) &
-- fmc516_adc_data(47 downto 32);
TRIG_ILA0_1 <= adc_dly_reg_debug_int(1).clk_load &
TRIG_ILA0_1(11 downto 0) <= adc_dly_reg_debug_int(1).clk_load &
adc_dly_reg_debug_int(1).data_load &
adc_dly_reg_debug_int(1).clk_dly_reg &
adc_dly_reg_debug_int(1).data_dly_reg;
TRIG_ILA0_1(31 downto 12) <= (others => '0');
-- FMC516 WBS master output control signals
TRIG_ILA0_2(17 downto 0) <= wbs_fmc516_out_array(1).cyc &
......
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