Commit 741e251e authored by Lucas Russo's avatar Lucas Russo

update initial design 2

parent b985100a
GNU LESSER GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
This version of the GNU Lesser General Public License incorporates
the terms and conditions of version 3 of the GNU General Public
License, supplemented by the additional permissions listed below.
0. Additional Definitions.
As used herein, "this License" refers to version 3 of the GNU Lesser
General Public License, and the "GNU GPL" refers to version 3 of the GNU
General Public License.
"The Library" refers to a covered work governed by this License,
other than an Application or a Combined Work as defined below.
An "Application" is any work that makes use of an interface provided
by the Library, but which is not otherwise based on the Library.
Defining a subclass of a class defined by the Library is deemed a mode
of using an interface provided by the Library.
A "Combined Work" is a work produced by combining or linking an
Application with the Library. The particular version of the Library
with which the Combined Work was made is also called the "Linked
Version".
The "Minimal Corresponding Source" for a Combined Work means the
Corresponding Source for the Combined Work, excluding any source code
for portions of the Combined Work that, considered in isolation, are
based on the Application, and not on the Linked Version.
The "Corresponding Application Code" for a Combined Work means the
object code and/or source code for the Application, including any data
and utility programs needed for reproducing the Combined Work from the
Application, but excluding the System Libraries of the Combined Work.
1. Exception to Section 3 of the GNU GPL.
You may convey a covered work under sections 3 and 4 of this License
without being bound by section 3 of the GNU GPL.
2. Conveying Modified Versions.
If you modify a copy of the Library, and, in your modifications, a
facility refers to a function or data to be supplied by an Application
that uses the facility (other than as an argument passed when the
facility is invoked), then you may convey a copy of the modified
version:
a) under this License, provided that you make a good faith effort to
ensure that, in the event an Application does not supply the
function or data, the facility still operates, and performs
whatever part of its purpose remains meaningful, or
b) under the GNU GPL, with none of the additional permissions of
this License applicable to that copy.
3. Object Code Incorporating Material from Library Header Files.
The object code form of an Application may incorporate material from
a header file that is part of the Library. You may convey such object
code under terms of your choice, provided that, if the incorporated
material is not limited to numerical parameters, data structure
layouts and accessors, or small macros, inline functions and templates
(ten or fewer lines in length), you do both of the following:
a) Give prominent notice with each copy of the object code that the
Library is used in it and that the Library and its use are
covered by this License.
b) Accompany the object code with a copy of the GNU GPL and this license
document.
4. Combined Works.
You may convey a Combined Work under terms of your choice that,
taken together, effectively do not restrict modification of the
portions of the Library contained in the Combined Work and reverse
engineering for debugging such modifications, if you also do each of
the following:
a) Give prominent notice with each copy of the Combined Work that
the Library is used in it and that the Library and its use are
covered by this License.
b) Accompany the Combined Work with a copy of the GNU GPL and this license
document.
c) For a Combined Work that displays copyright notices during
execution, include the copyright notice for the Library among
these notices, as well as a reference directing the user to the
copies of the GNU GPL and this license document.
d) Do one of the following:
0) Convey the Minimal Corresponding Source under the terms of this
License, and the Corresponding Application Code in a form
suitable for, and under terms that permit, the user to
recombine or relink the Application with a modified version of
the Linked Version to produce a modified Combined Work, in the
manner specified by section 6 of the GNU GPL for conveying
Corresponding Source.
1) Use a suitable shared library mechanism for linking with the
Library. A suitable mechanism is one that (a) uses at run time
a copy of the Library already present on the user's computer
system, and (b) will operate properly with a modified version
of the Library that is interface-compatible with the Linked
Version.
e) Provide Installation Information, but only if you would otherwise
be required to provide such information under section 6 of the
GNU GPL, and only to the extent that such information is
necessary to install and execute a modified version of the
Combined Work produced by recombining or relinking the
Application with a modified version of the Linked Version. (If
you use option 4d0, the Installation Information must accompany
the Minimal Corresponding Source and Corresponding Application
Code. If you use option 4d1, you must provide the Installation
Information in the manner specified by section 6 of the GNU GPL
for conveying Corresponding Source.)
5. Combined Libraries.
You may place library facilities that are a work based on the
Library side by side in a single library together with other library
facilities that are not Applications and are not covered by this
License, and convey such a combined library under terms of your
choice, if you do both of the following:
a) Accompany the combined library with a copy of the same work based
on the Library, uncombined with any other library facilities,
conveyed under the terms of this License.
b) Give prominent notice with the combined library that part of it
is a work based on the Library, and explaining where to find the
accompanying uncombined form of the same work.
6. Revised Versions of the GNU Lesser General Public License.
The Free Software Foundation may publish revised and/or new versions
of the GNU Lesser General Public License from time to time. Such new
versions will be similar in spirit to the present version, but may
differ in detail to address new problems or concerns.
Each version is given a distinguishing version number. If the
Library as you received it specifies that a certain numbered version
of the GNU Lesser General Public License "or any later version"
applies to it, you have the option of following the terms and
conditions either of that published version or of any later version
published by the Free Software Foundation. If the Library as you
received it does not specify a version number of the GNU Lesser
General Public License, you may choose any version of the GNU Lesser
General Public License ever published by the Free Software Foundation.
If the Library as you received it specifies that a proxy can decide
whether future versions of the GNU Lesser General Public License shall
apply, that proxy's public statement of acceptance of any version is
permanent authorization for you to choose that version for the
Library.
\ No newline at end of file
==========================================================
Repository containing the Beam Position Monitor FPGA firmware and
software.
==========================================================
Folder Hierarchy organization:
TODO
==========================================================
Folder containing all the BPM FPGA firmware and related tests
==========================================================
Folder containing all o the BPM FPGA firmware, testbenches
and related test software
==========================================================
......@@ -3,5 +3,4 @@ modules = { "local" : [
"fmc150",
"netlist" ] };
files = ["wb_fmc150.vhd", "xwb_fmc150.vhd", "xfmc150_regs_pkg.vhd", "wb_fmc150_port.vhd",
"xwb_fmc150.vhd" ];
files = ["wb_fmc150.vhd", "xwb_fmc150.vhd", "xfmc150_regs_pkg.vhd", "wb_fmc150_port.vhd" ];
......@@ -703,23 +703,6 @@ fmc150_flgs_out_spi_busy_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_pll_status_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_adc_clk_locked_i
......@@ -728,23 +711,6 @@ fmc150_flgs_out_adc_clk_locked_i
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_fmc_prst_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
......@@ -2816,14 +2782,14 @@ FLGS_OUT
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_PRST
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ADC_CLK_LOCKED
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
PLL_STATUS
ADC_CLK_LOCKED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SPI_BUSY
......@@ -2836,17 +2802,9 @@ SPI_BUSY
</b>[<i>read-only</i>]: SPI Busy
<br>read 1: spi busy.<br> read 0: spi idle
<li><b>
PLL_STATUS
</b>[<i>read-only</i>]: CDCE72010 PLL Status
<br>read 1: PLL locked.<br> read 0: PLL not locked
<li><b>
ADC_CLK_LOCKED
</b>[<i>read-only</i>]: FPGA ADC clock locked
<br>read 1: FPGA ADC PLL locked.<br> read 0: FPGA ADC PLL not locked
<li><b>
FMC_PRST
</b>[<i>read-only</i>]: FMC present
<br>read 1: FMC present.<br> read 0: FMC not present
</ul>
......
......@@ -10,6 +10,9 @@ use work.adc_pkg.all;
entity fmc150_adc_if is
generic (
g_sim : boolean := false
);
port
(
clk_200MHz_i : in std_logic;
......@@ -47,18 +50,27 @@ architecture rtl of fmc150_adc_if is
signal s_adc_chb_sdr : std_logic_vector(13 downto 0);
begin
-- ADC data strobe (channel A and B) with adjustable delay
cmp_adc_str: strobe_lvds
port map
(
clk_ctrl_i => clk_100MHz_i,
strobe_p_i => str_p_i,
strobe_n_i => str_n_i,
strobe_o => s_adc_str_dly,
ctrl_delay_update_i => delay_update_i,
ctrl_delay_value_i => str_cntvalue_i,
ctrl_delay_value_o => str_cntvalue_o
);
-- Synthesis Only!
gen_adc_clk : if (g_sim = false) generate
-- ADC data strobe (channel A and B) with adjustable delay
cmp_adc_str: strobe_lvds
port map
(
clk_ctrl_i => clk_100MHz_i,
strobe_p_i => str_p_i,
strobe_n_i => str_n_i,
strobe_o => s_adc_str_dly,
ctrl_delay_update_i => delay_update_i,
ctrl_delay_value_i => str_cntvalue_i,
ctrl_delay_value_o => str_cntvalue_o
);
end generate;
-- Simulation Only!
gen_adc_clk_sim : if (g_sim = true) generate
s_adc_str_dly <= str_p_i and str_n_i;
end generate;
-- s_adc_str_dly is a regional clock driven by BUFR.
-- Must go through a BUFG before other components (BPM DDC)
......@@ -109,4 +121,4 @@ begin
ctrl_delay_value_i => chb_cntvalue_i
);
end rtl;
\ No newline at end of file
end rtl;
......@@ -70,6 +70,9 @@ package fmc150_pkg is
end component;
component fmc150_adc_if is
generic (
g_sim : boolean := false
);
port
(
clk_200MHz_i : in std_logic;
......@@ -386,4 +389,4 @@ package fmc150_pkg is
);
end component;
end fmc150_pkg;
\ No newline at end of file
end fmc150_pkg;
......@@ -8,8 +8,10 @@ use unisim.vcomponents.all;
library work;
use work.fmc150_pkg.all;
entity fmc150_testbench is
generic(
g_sim : boolean := false
);
port
(
rst : in std_logic;
......@@ -28,10 +30,10 @@ port
dac_frame_p : out std_logic;
dac_frame_n : out std_logic;
txenable : out std_logic;
clk_to_fpga_p : in std_logic;
clk_to_fpga_n : in std_logic;
ext_trigger_p : in std_logic;
ext_trigger_n : in std_logic;
--clk_to_fpga_p : in std_logic;
--clk_to_fpga_n : in std_logic;
--ext_trigger_p : in std_logic;
--ext_trigger_n : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
rd_n_wr : in std_logic;
......@@ -113,116 +115,140 @@ architecture rtl of fmc150_testbench is
signal dac_din_d : std_logic_vector(15 downto 0);
signal adc_str_fbin, adc_str_out, adc_str_2x_out, adc_str_fbout : std_logic;
-- simulation only
signal toggle_ff_q : std_logic := '0';
begin
-- I/O delay control
cmp_idelayctrl : idelayctrl
port map
(
rst => rst,
refclk => clk_200MHz,
rdy => open
);
-- Synthesis Only
gen_clk : if (g_sim = false) generate
-- I/O delay control
cmp_idelayctrl : idelayctrl
port map
(
rst => rst,
refclk => clk_200MHz,
rdy => open
);
-- ADC Clock PLL
cmp_mmcm_adc : MMCM_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
--CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
--CLKOUT0_DIVIDE_F => 16.000,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
--CLKOUT1_DIVIDE => 8,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
-- 61.44 MHZ input clock
--CLKIN1_PERIOD => 16.276,
-- 122.88 MHZ input clock
CLKIN1_PERIOD => 8.138,
REF_JITTER1 => 0.010
)
port map
(
-- Output clocks
CLKFBOUT => adc_str_fbout,
CLKFBOUTB => open,
CLKOUT0 => adc_str_out,
CLKOUT0B => open,
CLKOUT1 => adc_str_2x_out,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => adc_str_fbin,
CLKIN1 => adc_str,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_adc_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst
);
-- ADC Clock PLL
cmp_mmcm_adc : MMCM_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
--CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
--CLKOUT0_DIVIDE_F => 16.000,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
--CLKOUT1_DIVIDE => 8,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
-- 61.44 MHZ input clock
--CLKIN1_PERIOD => 16.276,
-- 122.88 MHZ input clock
CLKIN1_PERIOD => 8.138,
REF_JITTER1 => 0.010
)
port map
(
-- Output clocks
CLKFBOUT => adc_str_fbout,
CLKFBOUTB => open,
CLKOUT0 => adc_str_out,
CLKOUT0B => open,
CLKOUT1 => adc_str_2x_out,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => adc_str_fbin,
CLKIN1 => adc_str,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_adc_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst
);
-- Global clock buffers for "cmp_mmcm_adc" instance
cmp_clkf_bufg : BUFG
port map
(
O => adc_str_fbin,
I => adc_str_fbout
);
cmp_adc_str_out_bufg : BUFG
port map
(
O => clk_adc,
I => adc_str_out
);
cmp_adc_str_2x_out_bufg : BUFG
port map
(
O => clk_adc_2x,
I => adc_str_2x_out
);
end generate;
-- Global clock buffers for "cmp_mmcm_adc" instance
cmp_clkf_bufg : BUFG
port map
(
O => adc_str_fbin,
I => adc_str_fbout
);
-- Double clock circuit. only for SIMULATION!
-- See Xilinx "six easy pieces" paper from Peter Alfke
gen_clk_sim : if (g_sim = true) generate
cmp_adc_str_out_bufg : BUFG
port map
(
O => clk_adc,
I => adc_str_out
);
cmp_adc_str_2x_out_bufg : BUFG
port map
(
O => clk_adc_2x,
I => adc_str_2x_out
);
clk_adc <= adc_str;
clk_adc_2x <= adc_str xor not toggle_ff_q;
p_gen_clk2x_sim : process(clk_adc_2x)
begin
if rising_edge(clk_adc_2x) then
toggle_ff_q <= not toggle_ff_q;
end if;
end process;
end generate;
clk_adc_o <= clk_adc;--adc_str;
-- ADC Interface
cmp_adc_if : fmc150_adc_if
generic map(
g_sim => g_sim
)
port map
(
clk_200MHz_i => clk_200MHz,
......@@ -331,4 +357,4 @@ begin
prsnt_m2c_l => prsnt_m2c_l
);
end rtl;
\ No newline at end of file
end rtl;
This diff is collapsed.
......@@ -21,7 +21,7 @@ peripheral {
--prefix = "start";
-- Pulse to start
type = MONOSTABLE;
clock = "clk_100Mhz";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -38,7 +38,7 @@ peripheral {
write 0: read from SPI";
prefix = "spi_rw";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -49,7 +49,7 @@ peripheral {
write 0: internal clock for ADC";
prefix = "ext_clk";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -66,7 +66,7 @@ peripheral {
--prefix = "addr";
type = SLV;
size = 16;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -83,7 +83,7 @@ peripheral {
--prefix = "data";
type = SLV;
size = 32;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -100,7 +100,7 @@ peripheral {
write 0: no effect";
prefix = "cdce72010";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -111,7 +111,7 @@ peripheral {
write 0: no effect";
prefix = "ads62p49";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -122,7 +122,7 @@ peripheral {
write 0: no effect";
prefix = "dac3283";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -133,7 +133,7 @@ peripheral {
write 0: no effect";
prefix = "amc7823";
type = BIT;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -151,7 +151,7 @@ peripheral {
type = SLV;
size = 5;
align = 8;
--clock = "";
clock = "clk_100Mhz_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -163,7 +163,7 @@ peripheral {
type = SLV;
size = 5;
align = 8;