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Commit 9e46e4ab authored by Lucas Russo's avatar Lucas Russo
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wb_fmc516/*: fix ddr alignment

parent 6a783b36
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hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd
View file @ 9e46e4ab
......@@ -70,6 +70,9 @@ port
-- if idelay is in variable or var_loadable mode)
adc_data_dly_pulse_i : in std_logic;
adc_data_fe_d1_en_i : in std_logic;
adc_data_fe_d2_en_i : in std_logic;
-----------------------------
-- ADC output signals
-----------------------------
......@@ -104,8 +107,13 @@ architecture rtl of fmc516_adc_data is
signal adc_data_bufg_sync : std_logic_vector(c_num_adc_bits-1 downto 0);
-- Delay signals
signal adc_data_re : std_logic_vector(c_num_adc_bits-1 downto 0); -- ADC data rising edge
signal adc_data_fe : std_logic_vector(c_num_adc_bits-1 downto 0); -- ADC data falling edge
signal adc_data_re : std_logic_vector(c_num_adc_bits/2-1 downto 0); -- ADC data rising edge
signal adc_data_fe : std_logic_vector(c_num_adc_bits/2-1 downto 0); -- ADC data falling edge
signal adc_data_fe_d1 : std_logic_vector(c_num_adc_bits/2-1 downto 0); -- ADC data falling edge delayed1
signal adc_data_fe_d2 : std_logic_vector(c_num_adc_bits/2-1 downto 0); -- ADC data falling edge delayed2
signal adc_data_d1 : t_adc_data_delay_array(c_num_adc_bits/2-1 downto 0); -- ADC data falling edge delayed1
signal adc_data_d2 : t_adc_data_delay_array(c_num_adc_bits/2-1 downto 0); -- ADC data falling edge delayed2
-- FIFO signals
signal adc_fifo_full : std_logic;
......@@ -124,7 +132,7 @@ architecture rtl of fmc516_adc_data is
signal sys_rst : std_logic;
--attribute IOB : string;
--attribute IOB of adc_data_ff: signal is "TRUE";
--attribute IOB of adc_data_ff: signal is "TRUE";
-- Built-in FIFO, 512-deep, 16-wide
component cdc_fifo
......@@ -241,8 +249,8 @@ begin
DDR_CLK_EDGE => "SAME_EDGE_PIPELINED"
)
port map(
q1 => adc_data_sdr(2*i+1),--adc_data_re(i),
q2 => adc_data_sdr(2*i),--adc_data_fe(i),
q1 => adc_data_re(i),--adc_data_sdr(2*i+1),
q2 => adc_data_fe(i),--adc_data_sdr(2*i),
c => adc_clk_bufio_i,
--c => adc_clk_bufr_i,
ce => '1',
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.vhd
View file @ 9e46e4ab
......@@ -79,6 +79,9 @@ port
adc_dly_i : in t_adc_dly_array(c_num_adc_channels-1 downto 0);
adc_dly_o : out t_adc_dly_array(c_num_adc_channels-1 downto 0);
-- ADC falling edge delay control
adc_dly_ctl_i : in t_adc_dly_ctl_array(c_num_adc_channels-1 downto 0);
-----------------------------
-- ADC output signals.
-----------------------------
......@@ -224,6 +227,9 @@ architecture rtl of fmc516_adc_iface is
-- if idelay is in variable or var_loadable mode)
adc_data_dly_pulse_i : in std_logic;
adc_data_fe_d1_en_i : in std_logic;
adc_data_fe_d2_en_i : in std_logic;
-----------------------------
-- ADC output signals.
-----------------------------
......@@ -360,57 +366,6 @@ begin
adc_data_dly_val_o => adc_dly_o(i).adc_data_dly_val,
adc_data_dly_incdec_i => adc_dly_i(i).adc_data_dly_incdec,
-----------------------------
-- ADC output signals.
-----------------------------
adc_data_o => adc_out_o(i).adc_data,
adc_data_valid_o => adc_out_o(i).adc_data_valid,
adc_clk_o => adc_out_o(i).adc_clk,
adc_clk2x_o => adc_out_o(i).adc_clk2x,
fifo_debug_valid_o => fifo_debug_valid_o(i),
fifo_debug_full_o => fifo_debug_full_o(i),
fifo_debug_empty_o => fifo_debug_empty_o(i)
);
end generate;
gen_explicitly_clk_data_map : if f_explicitly_clk_data_map(g_map_clk_data_chains) = true generate
cmp_fmc516_adc_data : fmc516_adc_data
generic map (
g_default_adc_data_delay => g_data_default_dly(i),
--g_delay_type => "VARIABLE",
g_delay_type => g_delay_type,
g_sim => g_sim
)
port map (
sys_clk_i => sys_clk_i,
sys_clk_200Mhz_i => sys_clk_200Mhz_i,
sys_rst_n_i => adc_in_i(i).adc_rst_n,--sys_rst_n_i,
-----------------------------
-- External ports
-----------------------------
-- DDR ADC data channels.
adc_data_i => adc_in_i(i).adc_data,
-----------------------------
-- Input Clocks from fmc516_adc_clk signals
-----------------------------
adc_clk_bufio_i => adc_clk_chain(g_map_clk_data_chains(i)).adc_clk_bufio,
adc_clk_bufr_i => adc_clk_chain(g_map_clk_data_chains(i)).adc_clk_bufr,
adc_clk_bufg_i => adc_clk_chain(g_map_clk_data_chains(i)).adc_clk_bufg,
adc_clk2x_bufg_i => adc_clk_chain(g_map_clk_data_chains(i)).adc_clk2x_bufg,
--adc_clk_bufg_rst_n_i => adc_in_i(i).adc_rst_n,
-----------------------------
-- ADC Data Delay signals.
-----------------------------
-- Pulse this to update the delay value
adc_data_dly_pulse_i => adc_dly_i(i).adc_data_dly_pulse,
adc_data_dly_val_i => adc_dly_i(i).adc_data_dly_val,
adc_data_dly_val_o => adc_dly_o(i).adc_data_dly_val,
adc_data_dly_incdec_i => adc_dly_i(i).adc_data_dly_incdec,
adc_data_fe_d1_en_i => adc_dly_ctl_i(i).adc_data_fe_d1_en,
adc_data_fe_d2_en_i => adc_dly_ctl_i(i).adc_data_fe_d2_en,
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_pkg.vhd
View file @ 9e46e4ab
......@@ -83,18 +83,15 @@ package fmc516_pkg is
end record;
type t_adc_dly_reg_array is array (natural range<>) of t_adc_dly_reg;
<<<<<<< HEAD
=======
-- ADC falling edge delay control
type t_adc_dly_ctl is record
adc_data_fe_d1_en : std_logic;
adc_data_fe_d2_en : std_logic;
end record;
type t_adc_dly_ctl_array is array (natural range<>) of t_adc_dly_ctl;
>>>>>>> 0caa735... various: bug-fixes: temp-mess 12
type t_adc_out is record
adc_clk : std_logic;
adc_clk2x : std_logic;
......@@ -287,4 +284,3 @@ package body fmc516_pkg is
end f_generate_chain_intercon;
end fmc516_pkg;
hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd
View file @ 9e46e4ab
......@@ -236,10 +236,8 @@ architecture rtl of wb_fmc516 is
-----------------------------
-- Number packet size counter bits
constant c_packet_num_bits : natural := f_packet_num_bits(g_packet_size);
-- Number of ADC channels
--constant c_num_channels : natural := 4;
-- Numbert of bits in Wishbone register interface
constant c_periph_addr_size : natural := 6;
constant c_periph_addr_size : natural := 7;
constant first_used_clk : natural := f_first_used_clk(g_use_clk_chains);
-----------------------------
......@@ -324,6 +322,9 @@ architecture rtl of wb_fmc516 is
-- ADC delay signals.
signal adc_dly_in : t_adc_dly_array(c_num_adc_channels-1 downto 0);
signal adc_dly_out : t_adc_dly_array(c_num_adc_channels-1 downto 0);
-- ADC falling edge control signals
signal adc_dly_ctl : t_adc_dly_ctl_array(c_num_adc_channels-1 downto 0);
signal adc_dly_ctl_in : t_adc_dly_ctl_array(c_num_adc_channels-1 downto 0);
-- ADC output signals.
signal adc_out : t_adc_out_array(c_num_adc_channels-1 downto 0);
......@@ -341,7 +342,7 @@ architecture rtl of wb_fmc516 is
-- ADC Reset signals
signal adc_clk_div_rst_int : std_logic;
signal adc_clk_div_rst_int_p : std_logic;
signal adc_clk_div_rst_int_p : std_logic;
signal fmc_reset_adcs_int : std_logic;
-----------------------------
......@@ -388,13 +389,13 @@ architecture rtl of wb_fmc516 is
-----------------------------
-- Wishbone fanout signals
-----------------------------
--signal wb_out : t_wishbone_master_in_array(0 to c_num_int_slaves-1);
--signal wb_in : t_wishbone_master_out_array(0 to c_num_int_slaves-1);
--signal wb_out : t_wishbone_master_in_array(0 to c_num_int_slaves-1);
--signal wb_in : t_wishbone_master_out_array(0 to c_num_int_slaves-1);
-- Crossbar master/slave arrays
signal cbar_slave_in : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_out : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_in : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_slaves-1 downto 0);
signal cbar_slave_in : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_out : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_in : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_slaves-1 downto 0);
-----------------------------
-- System I2C signals
......@@ -541,6 +542,9 @@ architecture rtl of wb_fmc516 is
adc_dly_i : in t_adc_dly_array(c_num_adc_channels-1 downto 0);
adc_dly_o : out t_adc_dly_array(c_num_adc_channels-1 downto 0);
-- ADC falling edge delay control
adc_dly_ctl_i : in t_adc_dly_ctl_array(c_num_adc_channels-1 downto 0);
-----------------------------
-- ADC output signals.
-----------------------------
......@@ -551,32 +555,15 @@ architecture rtl of wb_fmc516 is
-----------------------------
mmcm_adc_locked_o : out std_logic;
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
);
end component;
-- FMC516 Register Wishbone Interface
component wb_fmc516_regs
port (
<<<<<<< HEAD
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
--wb_clk_i : in std_logic;
regs_i : in t_fmc516_in_registers;
regs_o : out t_fmc516_out_registers
=======
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
......@@ -592,7 +579,6 @@ architecture rtl of wb_fmc516 is
--wb_clk_i : in std_logic;
regs_i : in t_fmc516_in_registers;
regs_o : out t_fmc516_out_registers
>>>>>>> 0caa735... various: bug-fixes: temp-mess 12
);
end component;
......@@ -738,7 +724,7 @@ begin
port map(
rst_n_i => sys_rst_sync_n,
clk_sys_i => sys_clk_i,
wb_adr_i => wb_slv_adp_out.adr(3 downto 0),
wb_adr_i => wb_slv_adp_out.adr(4 downto 0),
wb_dat_i => wb_slv_adp_out.dat,
wb_dat_o => wb_slv_adp_in.dat,
wb_cyc_i => wb_slv_adp_out.cyc,
......@@ -834,6 +820,16 @@ begin
adc_dly_reg(3).clk_dly_dec <= regs_out.ch3_ctl_dec_clk_chain_dly_o;
adc_dly_reg(3).data_dly_dec <= regs_out.ch3_ctl_dec_data_chain_dly_o;
-- ADC delay falling edge control
adc_dly_ctl(0).adc_data_fe_d1_en <= regs_out.ch0_dly_ctl_fe_dly_o(0);
adc_dly_ctl(0).adc_data_fe_d2_en <= regs_out.ch0_dly_ctl_fe_dly_o(1);
adc_dly_ctl(1).adc_data_fe_d1_en <= regs_out.ch1_dly_ctl_fe_dly_o(0);
adc_dly_ctl(1).adc_data_fe_d2_en <= regs_out.ch1_dly_ctl_fe_dly_o(1);
adc_dly_ctl(2).adc_data_fe_d1_en <= regs_out.ch2_dly_ctl_fe_dly_o(0);
adc_dly_ctl(2).adc_data_fe_d2_en <= regs_out.ch2_dly_ctl_fe_dly_o(1);
adc_dly_ctl(3).adc_data_fe_d1_en <= regs_out.ch3_dly_ctl_fe_dly_o(0);
adc_dly_ctl(3).adc_data_fe_d2_en <= regs_out.ch3_dly_ctl_fe_dly_o(1);
-- Wishbone Interface Register output assignments. There are others registers
-- not assigned here.
fmc_clk_sel_o <= regs_out.fmc_ctl_clk_sel_o;
......@@ -876,15 +872,12 @@ begin
--adc_dly_out(i).adc_data_dly_pulse <= '0';
end generate;
<<<<<<< HEAD
=======
-- ADC falling edge control signal mangling
gen_adc_dly_ctl : for i in 0 to c_num_adc_channels-1 generate
adc_dly_ctl_in(i).adc_data_fe_d1_en <= adc_dly_ctl(i).adc_data_fe_d1_en;
adc_dly_ctl_in(i).adc_data_fe_d2_en <= adc_dly_ctl(i).adc_data_fe_d2_en;
end generate;
>>>>>>> 0caa735... various: bug-fixes: temp-mess 12
-----------------------------
-- Wishbone Delay Register Interface <-> ADC interface (clock + data delays).
-----------------------------
......@@ -1042,6 +1035,8 @@ begin
adc_dly_i => adc_dly_in,
adc_dly_o => adc_dly_out,
adc_dly_ctl_i => adc_dly_ctl_in,
-----------------------------
-- ADC output signals
-----------------------------
......
hdl/modules/custom_wishbone/wb_fmc516/wbgen/fmc516_regs.h
View file @ 9e46e4ab
......@@ -3,7 +3,7 @@
* File : fmc516_regs.h
* Author : auto-generated by wbgen2 from wb_fmc516_regs.wb
* Created : Mon Mar 18 21:51:29 2013
* Created : Mon Mar 18 15:23:00 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
......@@ -204,6 +204,20 @@
#define FMC516_CH0_CTL_RESERVED_DATA_INCDEC_DLY_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
#define FMC516_CH0_CTL_RESERVED_DATA_INCDEC_DLY_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
/* definitions for register: Channel 0 delay control register */
/* definitions for field: Falling edge data delay in reg: Channel 0 delay control register */
#define FMC516_CH0_DLY_CTL_FE_DLY_MASK WBGEN2_GEN_MASK(0, 2)
#define FMC516_CH0_DLY_CTL_FE_DLY_SHIFT 0
#define FMC516_CH0_DLY_CTL_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FMC516_CH0_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 0 delay control register */
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
/* definitions for register: Channel 1 status register */
/* definitions for field: Channel 1 current ADC value in reg: Channel 1 status register */
......@@ -268,6 +282,20 @@
#define FMC516_CH1_CTL_RESERVED_DATA_INCDEC_DLY_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
#define FMC516_CH1_CTL_RESERVED_DATA_INCDEC_DLY_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
/* definitions for register: Channel 1 delay control register */
/* definitions for field: Falling edge data delay in reg: Channel 1 delay control register */
#define FMC516_CH1_DLY_CTL_FE_DLY_MASK WBGEN2_GEN_MASK(0, 2)
#define FMC516_CH1_DLY_CTL_FE_DLY_SHIFT 0
#define FMC516_CH1_DLY_CTL_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FMC516_CH1_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 1 delay control register */
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
/* definitions for register: Channel 2 status register */
/* definitions for field: Channel 2 current ADC value in reg: Channel 2 status register */
......@@ -332,6 +360,20 @@
#define FMC516_CH2_CTL_RESERVED_DATA_INCDEC_DLY_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
#define FMC516_CH2_CTL_RESERVED_DATA_INCDEC_DLY_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
/* definitions for register: Channel 2 delay control register */
/* definitions for field: Falling edge data delay in reg: Channel 2 delay control register */
#define FMC516_CH2_DLY_CTL_FE_DLY_MASK WBGEN2_GEN_MASK(0, 2)
#define FMC516_CH2_DLY_CTL_FE_DLY_SHIFT 0
#define FMC516_CH2_DLY_CTL_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FMC516_CH2_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 2 delay control register */
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
/* definitions for register: Channel 3 status register */
/* definitions for field: Channel 3 current ADC value in reg: Channel 3 status register */
......@@ -396,6 +438,20 @@
#define FMC516_CH3_CTL_RESERVED_DATA_INCDEC_DLY_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
#define FMC516_CH3_CTL_RESERVED_DATA_INCDEC_DLY_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
/* definitions for register: Channel 3 delay control register */
/* definitions for field: Falling edge data delay in reg: Channel 3 delay control register */
#define FMC516_CH3_DLY_CTL_FE_DLY_MASK WBGEN2_GEN_MASK(0, 2)
#define FMC516_CH3_DLY_CTL_FE_DLY_SHIFT 0
#define FMC516_CH3_DLY_CTL_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FMC516_CH3_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 3 delay control register */
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
PACKED struct FMC516_WB {
/* [0x0]: REG Status register */
uint32_t FMC_STA;
......@@ -411,18 +467,26 @@ PACKED struct FMC516_WB {
uint32_t CH0_STA;
/* [0x18]: REG Channel 0 control register */
uint32_t CH0_CTL;
/* [0x1c]: REG Channel 1 status register */
/* [0x1c]: REG Channel 0 delay control register */
uint32_t CH0_DLY_CTL;
/* [0x20]: REG Channel 1 status register */
uint32_t CH1_STA;
/* [0x20]: REG Channel 1 control register */
/* [0x24]: REG Channel 1 control register */
uint32_t CH1_CTL;
/* [0x24]: REG Channel 2 status register */
/* [0x28]: REG Channel 1 delay control register */
uint32_t CH1_DLY_CTL;
/* [0x2c]: REG Channel 2 status register */
uint32_t CH2_STA;
/* [0x28]: REG Channel 2 control register */
/* [0x30]: REG Channel 2 control register */
uint32_t CH2_CTL;
/* [0x2c]: REG Channel 3 status register */
/* [0x34]: REG Channel 2 delay control register */
uint32_t CH2_DLY_CTL;
/* [0x38]: REG Channel 3 status register */
uint32_t CH3_STA;
/* [0x30]: REG Channel 3 control register */
/* [0x3c]: REG Channel 3 control register */
uint32_t CH3_CTL;
/* [0x40]: REG Channel 3 delay control register */
uint32_t CH3_DLY_CTL;
};
#endif
hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.wb
View file @ 9e46e4ab
......@@ -470,6 +470,34 @@ peripheral {
};
};
reg {
name = "Channel 0 delay control register";
prefix = "ch0_dly_ctl";
field {
name = "Falling edge data delay";
description = "write 3: delay falling edge data by two.\
write 1: delay falling edge data by one.\
write 0: no effect";
prefix = "fe_dly";
type = SLV;
clock = "fs_clk_i";
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on write, read as 0's";
prefix = "reserved_fe_dly";
type = SLV;
size = 30;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 1 status register";
prefix = "ch1_sta";
......@@ -497,6 +525,7 @@ peripheral {
};
};
reg {
name = "Channel 1 control register";
prefix = "ch1_ctl";
......@@ -628,6 +657,34 @@ peripheral {
};
};
reg {
name = "Channel 1 delay control register";
prefix = "ch1_dly_ctl";
field {
name = "Falling edge data delay";
description = "write 3: delay falling edge data by two.\
write 1: delay falling edge data by one.\
write 0: no effect";
prefix = "fe_dly";
type = SLV;
clock = "fs_clk_i";
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on write, read as 0's";
prefix = "reserved_fe_dly";
type = SLV;
size = 30;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 2 status register";
prefix = "ch2_sta";
......@@ -786,6 +843,34 @@ peripheral {
};
};
reg {
name = "Channel 2 delay control register";
prefix = "ch2_dly_ctl";
field {
name = "Falling edge data delay";
description = "write 3: delay falling edge data by two.\
write 1: delay falling edge data by one.\
write 0: no effect";
prefix = "fe_dly";
type = SLV;
clock = "fs_clk_i";
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on write, read as 0's";
prefix = "reserved_fe_dly";
type = SLV;
size = 30;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 3 status register";
prefix = "ch3_sta";
......@@ -943,4 +1028,32 @@ peripheral {
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 3 delay control register";
prefix = "ch3_dly_ctl";
field {
name = "Falling edge data delay";
description = "write 3: delay falling edge data by two.\
write 1: delay falling edge data by one.\
write 0: no effect";
prefix = "fe_dly";
type = SLV;
clock = "fs_clk_i";
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on write, read as 0's";
prefix = "reserved_fe_dly";
type = SLV;
size = 30;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd
View file @ 9e46e4ab
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wb_fmc516_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from wb_fmc516_regs.wb
-- Created : Mon Mar 18 21:51:29 2013
-- Created : Mon Mar 18 15:23:00 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
......@@ -121,6 +121,8 @@ package fmc516_wbgen2_pkg is
ch0_ctl_inc_data_chain_dly_o : std_logic;
ch0_ctl_dec_data_chain_dly_o : std_logic;
ch0_ctl_reserved_data_incdec_dly_o : std_logic_vector(5 downto 0);
ch0_dly_ctl_fe_dly_o : std_logic_vector(1 downto 0);
ch0_dly_ctl_reserved_fe_dly_o : std_logic_vector(29 downto 0);
ch1_ctl_clk_chain_dly_o : std_logic_vector(4 downto 0);
ch1_ctl_clk_chain_dly_load_o : std_logic;
ch1_ctl_data_chain_dly_o : std_logic_vector(4 downto 0);
......@@ -131,6 +133,8 @@ package fmc516_wbgen2_pkg is
ch1_ctl_inc_data_chain_dly_o : std_logic;
ch1_ctl_dec_data_chain_dly_o : std_logic;
ch1_ctl_reserved_data_incdec_dly_o : std_logic_vector(5 downto 0);
ch1_dly_ctl_fe_dly_o : std_logic_vector(1 downto 0);
ch1_dly_ctl_reserved_fe_dly_o : std_logic_vector(29 downto 0);
ch2_ctl_clk_chain_dly_o : std_logic_vector(4 downto 0);
ch2_ctl_clk_chain_dly_load_o : std_logic;
ch2_ctl_data_chain_dly_o : std_logic_vector(4 downto 0);
......@@ -141,6 +145,8 @@ package fmc516_wbgen2_pkg is
ch2_ctl_inc_data_chain_dly_o : std_logic;
ch2_ctl_dec_data_chain_dly_o : std_logic;
ch2_ctl_reserved_data_incdec_dly_o : std_logic_vector(5 downto 0);
ch2_dly_ctl_fe_dly_o : std_logic_vector(1 downto 0);
ch2_dly_ctl_reserved_fe_dly_o : std_logic_vector(29 downto 0);
ch3_ctl_clk_chain_dly_o : std_logic_vector(4 downto 0);
ch3_ctl_clk_chain_dly_load_o : std_logic;
ch3_ctl_data_chain_dly_o : std_logic_vector(4 downto 0);
......@@ -151,6 +157,8 @@ package fmc516_wbgen2_pkg is
ch3_ctl_inc_data_chain_dly_o : std_logic;
ch3_ctl_dec_data_chain_dly_o : std_logic;
ch3_ctl_reserved_data_incdec_dly_o : std_logic_vector(5 downto 0);
ch3_dly_ctl_fe_dly_o : std_logic_vector(1 downto 0);
ch3_dly_ctl_reserved_fe_dly_o : std_logic_vector(29 downto 0);
end record;
constant c_fmc516_out_registers_init_value: t_fmc516_out_registers := (
......@@ -177,6 +185,8 @@ package fmc516_wbgen2_pkg is
ch0_ctl_inc_data_chain_dly_o => '0',
ch0_ctl_dec_data_chain_dly_o => '0',
ch0_ctl_reserved_data_incdec_dly_o => (others => '0'),
ch0_dly_ctl_fe_dly_o => (others => '0'),
ch0_dly_ctl_reserved_fe_dly_o => (others => '0'),
ch1_ctl_clk_chain_dly_o => (others => '0'),
ch1_ctl_clk_chain_dly_load_o => '0',
ch1_ctl_data_chain_dly_o => (others => '0'),
......@@ -187,6 +197,8 @@ package fmc516_wbgen2_pkg is
ch1_ctl_inc_data_chain_dly_o => '0',
ch1_ctl_dec_data_chain_dly_o => '0',
ch1_ctl_reserved_data_incdec_dly_o => (others => '0'),
ch1_dly_ctl_fe_dly_o => (others => '0'),
ch1_dly_ctl_reserved_fe_dly_o => (others => '0'),
ch2_ctl_clk_chain_dly_o => (others => '0'),
ch2_ctl_clk_chain_dly_load_o => '0',
ch2_ctl_data_chain_dly_o => (others => '0'),
......@@ -197,6 +209,8 @@ package fmc516_wbgen2_pkg is
ch2_ctl_inc_data_chain_dly_o => '0',
ch2_ctl_dec_data_chain_dly_o => '0',
ch2_ctl_reserved_data_incdec_dly_o => (others => '0'),
ch2_dly_ctl_fe_dly_o => (others => '0'),
ch2_dly_ctl_reserved_fe_dly_o => (others => '0'),
ch3_ctl_clk_chain_dly_o => (others => '0'),
ch3_ctl_clk_chain_dly_load_o => '0',
ch3_ctl_data_chain_dly_o => (others => '0'),
......@@ -206,7 +220,9 @@ package fmc516_wbgen2_pkg is
ch3_ctl_reserved_clk_incdec_dly_o => (others => '0'),
ch3_ctl_inc_data_chain_dly_o => '0',
ch3_ctl_dec_data_chain_dly_o => '0',
ch3_ctl_reserved_data_incdec_dly_o => (others => '0')
ch3_ctl_reserved_data_incdec_dly_o => (others => '0'),
ch3_dly_ctl_fe_dly_o => (others => '0'),
ch3_dly_ctl_reserved_fe_dly_o => (others => '0')
);
function "or" (left, right: t_fmc516_in_registers) return t_fmc516_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......
hdl/sim/regs/wb_fmc516_regs.vh
View file @ 9e46e4ab
`define ADDR_FMC516_FMC_STA 6'h0
`define ADDR_FMC516_FMC_STA 7'h0
`define FMC516_FMC_STA_LMK_LOCKED_OFFSET 0
`define FMC516_FMC_STA_LMK_LOCKED 32'h00000001
`define FMC516_FMC_STA_MMCM_LOCKED_OFFSET 1
......@@ -9,7 +9,7 @@
`define FMC516_FMC_STA_PRST 32'h00000008
`define FMC516_FMC_STA_RESERVED_OFFSET 4
`define FMC516_FMC_STA_RESERVED 32'hfffffff0
`define ADDR_FMC516_FMC_CTL 6'h4
`define ADDR_FMC516_FMC_CTL 7'h4
`define FMC516_FMC_CTL_TEST_DATA_EN_OFFSET 0
`define FMC516_FMC_CTL_TEST_DATA_EN 32'h00000001
`define FMC516_FMC_CTL_LED_0_OFFSET 1
......@@ -22,14 +22,14 @@
`define FMC516_FMC_CTL_VCXO_OUT_EN 32'h00000010
`define FMC516_FMC_CTL_RESERVED_OFFSET 5
`define FMC516_FMC_CTL_RESERVED 32'hffffffe0
`define ADDR_FMC516_TRIG_CFG 6'h8
`define ADDR_FMC516_TRIG_CFG 7'h8
`define FMC516_TRIG_CFG_HW_TRIG_POL_OFFSET 0
`define FMC516_TRIG_CFG_HW_TRIG_POL 32'h00000001
`define FMC516_TRIG_CFG_HW_TRIG_EN_OFFSET 1
`define FMC516_TRIG_CFG_HW_TRIG_EN 32'h00000002
`define FMC516_TRIG_CFG_RESERVED_OFFSET 2
`define FMC516_TRIG_CFG_RESERVED 32'hfffffffc
`define ADDR_FMC516_ADC_STA 6'hc
`define ADDR_FMC516_ADC_STA 7'hc
`define FMC516_ADC_STA_CLK_CHAINS_OFFSET 0
`define FMC516_ADC_STA_CLK_CHAINS 32'h0000000f
`define FMC516_ADC_STA_RESERVED_CLK_CHAINS_OFFSET 4
......@@ -40,7 +40,7 @@
`define FMC516_ADC_STA_RESERVED_DATA_CHAINS 32'h0000f000
`define FMC516_ADC_STA_ADC_PKT_SIZE_OFFSET 16
`define FMC516_ADC_STA_ADC_PKT_SIZE 32'hffff0000
`define ADDR_FMC516_ADC_CTL 6'h10
`define ADDR_FMC516_ADC_CTL 7'h10
`define FMC516_ADC_CTL_UPDATE_CLK_DLY_OFFSET 0
`define FMC516_ADC_CTL_UPDATE_CLK_DLY 32'h00000001
`define FMC516_ADC_CTL_UPDATE_DATA_DLY_OFFSET 1
......@@ -51,12 +51,12 @@
`define FMC516_ADC_CTL_RST_DIV_ADCS 32'h00000008
`define FMC516_ADC_CTL_RESERVED_OFFSET 4
`define FMC516_ADC_CTL_RESERVED 32'hfffffff0
`define ADDR_FMC516_CH0_STA 6'h14
`define ADDR_FMC516_CH0_STA 7'h14
`define FMC516_CH0_STA_VAL_OFFSET 0
`define FMC516_CH0_STA_VAL 32'h0000ffff
`define FMC516_CH0_STA_RESERVED_OFFSET 16
`define FMC516_CH0_STA_RESERVED 32'hffff0000
`define ADDR_FMC516_CH0_CTL 6'h18
`define ADDR_FMC516_CH0_CTL 7'h18
`define FMC516_CH0_CTL_CLK_CHAIN_DLY_OFFSET 0
`define FMC516_CH0_CTL_CLK_CHAIN_DLY 32'h0000001f
`define FMC516_CH0_CTL_RESERVED_CLK_CHAIN_DLY_OFFSET 5
......@@ -77,12 +77,17 @@
`define FMC516_CH0_CTL_DEC_DATA_CHAIN_DLY 32'h02000000
`define FMC516_CH0_CTL_RESERVED_DATA_INCDEC_DLY_OFFSET 26
`define FMC516_CH0_CTL_RESERVED_DATA_INCDEC_DLY 32'hfc000000
`define ADDR_FMC516_CH1_STA 6'h1c
`define ADDR_FMC516_CH0_DLY_CTL 7'h1c
`define FMC516_CH0_DLY_CTL_FE_DLY_OFFSET 0
`define FMC516_CH0_DLY_CTL_FE_DLY 32'h00000003
`define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_OFFSET 2
`define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY 32'hfffffffc
`define ADDR_FMC516_CH1_STA 7'h20
`define FMC516_CH1_STA_VAL_OFFSET 0
`define FMC516_CH1_STA_VAL 32'h0000ffff
`define FMC516_CH1_STA_RESERVED_OFFSET 16
`define FMC516_CH1_STA_RESERVED 32'hffff0000
`define ADDR_FMC516_CH1_CTL 6'h20
`define ADDR_FMC516_CH1_CTL 7'h24
`define FMC516_CH1_CTL_CLK_CHAIN_DLY_OFFSET 0
`define FMC516_CH1_CTL_CLK_CHAIN_DLY 32'h0000001f
`define FMC516_CH1_CTL_RESERVED_CLK_CHAIN_DLY_OFFSET 5
......@@ -103,12 +108,17 @@
`define FMC516_CH1_CTL_DEC_DATA_CHAIN_DLY 32'h02000000
`define FMC516_CH1_CTL_RESERVED_DATA_INCDEC_DLY_OFFSET 26
`define FMC516_CH1_CTL_RESERVED_DATA_INCDEC_DLY 32'hfc000000
`define ADDR_FMC516_CH2_STA 6'h24
`define ADDR_FMC516_CH1_DLY_CTL 7'h28
`define FMC516_CH1_DLY_CTL_FE_DLY_OFFSET 0
`define FMC516_CH1_DLY_CTL_FE_DLY 32'h00000003
`define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_OFFSET 2
`define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY 32'hfffffffc
`define ADDR_FMC516_CH2_STA 7'h2c
`define FMC516_CH2_STA_VAL_OFFSET 0
`define FMC516_CH2_STA_VAL 32'h0000ffff
`define FMC516_CH2_STA_RESERVED_OFFSET 16
`define FMC516_CH2_STA_RESERVED 32'hffff0000
`define ADDR_FMC516_CH2_CTL 6'h28
`define ADDR_FMC516_CH2_CTL 7'h30
`define FMC516_CH2_CTL_CLK_CHAIN_DLY_OFFSET 0
`define FMC516_CH2_CTL_CLK_CHAIN_DLY 32'h0000001f
`define FMC516_CH2_CTL_RESERVED_CLK_CHAIN_DLY_OFFSET 5
......@@ -129,12 +139,17 @@
`define FMC516_CH2_CTL_DEC_DATA_CHAIN_DLY 32'h02000000
`define FMC516_CH2_CTL_RESERVED_DATA_INCDEC_DLY_OFFSET 26
`define FMC516_CH2_CTL_RESERVED_DATA_INCDEC_DLY 32'hfc000000
`define ADDR_FMC516_CH3_STA 6'h2c
`define ADDR_FMC516_CH2_DLY_CTL 7'h34
`define FMC516_CH2_DLY_CTL_FE_DLY_OFFSET 0
`define FMC516_CH2_DLY_CTL_FE_DLY 32'h00000003
`define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_OFFSET 2
`define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY 32'hfffffffc
`define ADDR_FMC516_CH3_STA 7'h38
`define FMC516_CH3_STA_VAL_OFFSET 0
`define FMC516_CH3_STA_VAL 32'h0000ffff
`define FMC516_CH3_STA_RESERVED_OFFSET 16
`define FMC516_CH3_STA_RESERVED 32'hffff0000
`define ADDR_FMC516_CH3_CTL 6'h30
`define ADDR_FMC516_CH3_CTL 7'h3c
`define FMC516_CH3_CTL_CLK_CHAIN_DLY_OFFSET 0
`define FMC516_CH3_CTL_CLK_CHAIN_DLY 32'h0000001f
`define FMC516_CH3_CTL_RESERVED_CLK_CHAIN_DLY_OFFSET 5
......@@ -155,3 +170,8 @@
`define FMC516_CH3_CTL_DEC_DATA_CHAIN_DLY 32'h02000000
`define FMC516_CH3_CTL_RESERVED_DATA_INCDEC_DLY_OFFSET 26
`define FMC516_CH3_CTL_RESERVED_DATA_INCDEC_DLY 32'hfc000000
`define ADDR_FMC516_CH3_DLY_CTL 7'h40
`define FMC516_CH3_DLY_CTL_FE_DLY_OFFSET 0
`define FMC516_CH3_DLY_CTL_FE_DLY 32'h00000003
`define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_OFFSET 2
`define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY 32'hfffffffc
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