hdl/platform/artix7/chipscope/*: add chipscope files

a67f12d2 · Lucas Russo · aeded434 · a67f12d2 · a67f12d2 · a67f12d2
Commit a67f12d2 authored Feb 25, 2015 by Lucas Russo
7 changed files
--- a/hdl/platform/artix7/chipscope/Manifest.py
+++ b/hdl/platform/artix7/chipscope/Manifest.py
+files = [
+    "icon_4_port/chipscope_icon_4_port.ngc",
+	"icon_4_port/chipscope_icon_4_port.vhd",
+	"icon_6_port/chipscope_icon_6_port.ngc",
+	"icon_6_port/chipscope_icon_6_port.vhd",
+	"ila/chipscope_ila.ngc",
+	"ila/chipscope_ila.vhd"]
--- a/hdl/platform/artix7/chipscope/icon_4_port/chipscope_icon_4_port.ngc
+++ b/hdl/platform/artix7/chipscope/icon_4_port/chipscope_icon_4_port.ngc
--- a/hdl/platform/artix7/chipscope/icon_4_port/chipscope_icon_4_port.vhd
+++ b/hdl/platform/artix7/chipscope/icon_4_port/chipscope_icon_4_port.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2015 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 14.6
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_icon_4_port.vhd
+-- /___/   /\     Timestamp  : Sex Fev 20 10:39:02 BRST 2015
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_icon_4_port IS
+  port (
+    CONTROL0: inout std_logic_vector(35 downto 0);
+    CONTROL1: inout std_logic_vector(35 downto 0);
+    CONTROL2: inout std_logic_vector(35 downto 0);
+    CONTROL3: inout std_logic_vector(35 downto 0));
+END chipscope_icon_4_port;
+
+ARCHITECTURE chipscope_icon_4_port_a OF chipscope_icon_4_port IS
+BEGIN
+
+END chipscope_icon_4_port_a;
--- a/hdl/platform/artix7/chipscope/icon_6_port/chipscope_icon_6_port.ngc
+++ b/hdl/platform/artix7/chipscope/icon_6_port/chipscope_icon_6_port.ngc
--- a/hdl/platform/artix7/chipscope/icon_6_port/chipscope_icon_6_port.vhd
+++ b/hdl/platform/artix7/chipscope/icon_6_port/chipscope_icon_6_port.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2015 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 14.6
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_icon_6_port.vhd
+-- /___/   /\     Timestamp  : Sex Fev 20 10:29:57 BRST 2015
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_icon_6_port IS
+  port (
+    CONTROL0: inout std_logic_vector(35 downto 0);
+    CONTROL1: inout std_logic_vector(35 downto 0);
+    CONTROL2: inout std_logic_vector(35 downto 0);
+    CONTROL3: inout std_logic_vector(35 downto 0);
+    CONTROL4: inout std_logic_vector(35 downto 0);
+    CONTROL5: inout std_logic_vector(35 downto 0));
+END chipscope_icon_6_port;
+
+ARCHITECTURE chipscope_icon_6_port_a OF chipscope_icon_6_port IS
+BEGIN
+
+END chipscope_icon_6_port_a;
--- a/hdl/platform/artix7/chipscope/ila/chipscope_ila.ngc
+++ b/hdl/platform/artix7/chipscope/ila/chipscope_ila.ngc
--- a/hdl/platform/artix7/chipscope/ila/chipscope_ila.vhd
+++ b/hdl/platform/artix7/chipscope/ila/chipscope_ila.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2015 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 14.6
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_ila.vhd
+-- /___/   /\     Timestamp  : Sex Fev 20 10:37:45 BRST 2015
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_ila IS
+  port (
+    CONTROL: inout std_logic_vector(35 downto 0);
+    CLK: in std_logic;
+    TRIG0: in std_logic_vector(31 downto 0);
+    TRIG1: in std_logic_vector(31 downto 0);
+    TRIG2: in std_logic_vector(31 downto 0);
+    TRIG3: in std_logic_vector(31 downto 0));
+END chipscope_ila;
+
+ARCHITECTURE chipscope_ila_a OF chipscope_ila IS
+BEGIN
+
+END chipscope_ila_a;