hdl/platform/virtex6/*: add chipscope and dds ip cores

ac467485 · Lucas Russo · 892c9cc1 · ac467485 · ac467485 · ac467485
Commit ac467485 authored Sep 26, 2013 by Lucas Russo
20 changed files
--- a/hdl/platform/virtex6/chipscope/Manifest.py
+++ b/hdl/platform/virtex6/chipscope/Manifest.py
-files = ["icon_1_port/chipscope_icon_1_port.ngc", "icon_2_port/chipscope_icon_2_port.ngc", 
-	"icon_4_port/chipscope_icon_4_port.ngc", "icon_7_port/chipscope_icon_7_port.ngc", 
-	"icon_8_port/chipscope_icon_8_port.ngc", "ila/chipscope_ila.ngc", "ila/chipscope_ila_8192.ngc"]
+files = ["icon_1_port/chipscope_icon_1_port.ngc",
+	"icon_1_port/chipscope_icon_1_port.vhd",
+	"icon_2_port/chipscope_icon_2_port.ngc", 
+	"icon_4_port/chipscope_icon_4_port.ngc", 
+	"icon_4_port/chipscope_icon_4_port.vhd",
+	"icon_7_port/chipscope_icon_7_port.ngc", 
+	"icon_7_port/chipscope_icon_7_port.vhd", 
+	"icon_8_port/chipscope_icon_8_port.ngc",
+	"icon_8_port/chipscope_icon_8_port.vhd",
+	"icon_13_port/chipscope_icon_13_port.ngc",
+	"icon_13_port/chipscope_icon_13_port.vhd",
+	"ila/chipscope_ila.ngc", 
+	"ila/chipscope_ila.vhd", 
+	"ila/chipscope_ila_1024.ngc", 
+	"ila/chipscope_ila_1024.vhd", 
+	"ila/chipscope_ila_4096.ngc", 
+	"ila/chipscope_ila_4096.vhd", 
+	"ila/chipscope_ila_8192.ngc",
+	"ila/chipscope_ila_8192.vhd",
+	"ila/chipscope_ila_32768.ngc", 
+	"ila/chipscope_ila_32768.vhd",
+	"ila/chipscope_ila_65536.ngc",
+	"ila/chipscope_ila_65536.vhd",
+	"ila/chipscope_ila_131072.ngc", 
+	"ila/chipscope_ila_131072.vhd",
+	"vio/chipscope_vio_256.ngc",
+	"vio/chipscope_vio_256.vhd"]
--- a/hdl/platform/virtex6/chipscope/icon_13_port/chipscope_icon_13_port.ngc
+++ b/hdl/platform/virtex6/chipscope/icon_13_port/chipscope_icon_13_port.ngc
--- a/hdl/platform/virtex6/chipscope/icon_13_port/chipscope_icon_13_port.vhd
+++ b/hdl/platform/virtex6/chipscope/icon_13_port/chipscope_icon_13_port.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 13.4
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_icon_13_port.vhd
+-- /___/   /\     Timestamp  : Tue Jul 23 14:56:51 BRT 2013
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_icon_13_port IS
+  port (
+    CONTROL0: inout std_logic_vector(35 downto 0);
+    CONTROL1: inout std_logic_vector(35 downto 0);
+    CONTROL2: inout std_logic_vector(35 downto 0);
+    CONTROL3: inout std_logic_vector(35 downto 0);
+    CONTROL4: inout std_logic_vector(35 downto 0);
+    CONTROL5: inout std_logic_vector(35 downto 0);
+    CONTROL6: inout std_logic_vector(35 downto 0);
+    CONTROL7: inout std_logic_vector(35 downto 0);
+    CONTROL8: inout std_logic_vector(35 downto 0);
+    CONTROL9: inout std_logic_vector(35 downto 0);
+    CONTROL10: inout std_logic_vector(35 downto 0);
+    CONTROL11: inout std_logic_vector(35 downto 0);
+    CONTROL12: inout std_logic_vector(35 downto 0));
+END chipscope_icon_13_port;
+
+ARCHITECTURE chipscope_icon_13_port_a OF chipscope_icon_13_port IS
+BEGIN
+
+END chipscope_icon_13_port_a;
--- a/hdl/platform/virtex6/chipscope/ila/chipscope_ila_1024.ngc
+++ b/hdl/platform/virtex6/chipscope/ila/chipscope_ila_1024.ngc
--- a/hdl/platform/virtex6/chipscope/ila/chipscope_ila_1024.vhd
+++ b/hdl/platform/virtex6/chipscope/ila/chipscope_ila_1024.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 13.4
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_ila_1024.vhd
+-- /___/   /\     Timestamp  : Tue Aug 13 15:39:30 BRT 2013
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_ila_1024 IS
+  port (
+    CONTROL: inout std_logic_vector(35 downto 0);
+    CLK: in std_logic;
+    TRIG0: in std_logic_vector(7 downto 0);
+    TRIG1: in std_logic_vector(31 downto 0);
+    TRIG2: in std_logic_vector(31 downto 0);
+    TRIG3: in std_logic_vector(31 downto 0);
+    TRIG4: in std_logic_vector(31 downto 0));
+END chipscope_ila_1024;
+
+ARCHITECTURE chipscope_ila_1024_a OF chipscope_ila_1024 IS
+BEGIN
+
+END chipscope_ila_1024_a;
--- a/hdl/platform/virtex6/chipscope/ila/chipscope_ila_131072.ngc
+++ b/hdl/platform/virtex6/chipscope/ila/chipscope_ila_131072.ngc
--- a/hdl/platform/virtex6/chipscope/ila/chipscope_ila_131072.vhd
+++ b/hdl/platform/virtex6/chipscope/ila/chipscope_ila_131072.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 13.4
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_ila_131072.vhd
+-- /___/   /\     Timestamp  : Mon Jul 22 14:22:39 BRT 2013
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_ila_131072 IS
+  port (
+    CONTROL: inout std_logic_vector(35 downto 0);
+    CLK: in std_logic;
+    TRIG0: in std_logic_vector(7 downto 0);
+    TRIG1: in std_logic_vector(15 downto 0);
+    TRIG2: in std_logic_vector(15 downto 0);
+    TRIG3: in std_logic_vector(15 downto 0);
+    TRIG4: in std_logic_vector(15 downto 0));
+END chipscope_ila_131072;
+
+ARCHITECTURE chipscope_ila_131072_a OF chipscope_ila_131072 IS
+BEGIN
+
+END chipscope_ila_131072_a;
--- a/hdl/platform/virtex6/chipscope/ila/chipscope_ila_32768.ngc
+++ b/hdl/platform/virtex6/chipscope/ila/chipscope_ila_32768.ngc
--- a/hdl/platform/virtex6/chipscope/ila/chipscope_ila_32768.vhd
+++ b/hdl/platform/virtex6/chipscope/ila/chipscope_ila_32768.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 13.4
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_ila_32768.vhd
+-- /___/   /\     Timestamp  : Fri Jul 19 12:11:29 BRT 2013
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_ila_32768 IS
+  port (
+    CONTROL: inout std_logic_vector(35 downto 0);
+    CLK: in std_logic;
+    TRIG0: in std_logic_vector(7 downto 0);
+    TRIG1: in std_logic_vector(31 downto 0);
+    TRIG2: in std_logic_vector(31 downto 0);
+    TRIG3: in std_logic_vector(31 downto 0);
+    TRIG4: in std_logic_vector(31 downto 0));
+END chipscope_ila_32768;
+
+ARCHITECTURE chipscope_ila_32768_a OF chipscope_ila_32768 IS
+BEGIN
+
+END chipscope_ila_32768_a;
--- a/hdl/platform/virtex6/chipscope/ila/chipscope_ila_4096.ngc
+++ b/hdl/platform/virtex6/chipscope/ila/chipscope_ila_4096.ngc
--- a/hdl/platform/virtex6/chipscope/ila/chipscope_ila_4096.vhd
+++ b/hdl/platform/virtex6/chipscope/ila/chipscope_ila_4096.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 13.4
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_ila_4096.vhd
+-- /___/   /\     Timestamp  : Fri Jul 19 11:58:51 BRT 2013
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_ila_4096 IS
+  port (
+    CONTROL: inout std_logic_vector(35 downto 0);
+    CLK: in std_logic;
+    TRIG0: in std_logic_vector(7 downto 0);
+    TRIG1: in std_logic_vector(31 downto 0);
+    TRIG2: in std_logic_vector(31 downto 0);
+    TRIG3: in std_logic_vector(31 downto 0);
+    TRIG4: in std_logic_vector(31 downto 0));
+END chipscope_ila_4096;
+
+ARCHITECTURE chipscope_ila_4096_a OF chipscope_ila_4096 IS
+BEGIN
+
+END chipscope_ila_4096_a;
--- a/hdl/platform/virtex6/chipscope/ila/chipscope_ila_65536.ngc
+++ b/hdl/platform/virtex6/chipscope/ila/chipscope_ila_65536.ngc
--- a/hdl/platform/virtex6/chipscope/ila/chipscope_ila_65536.vhd
+++ b/hdl/platform/virtex6/chipscope/ila/chipscope_ila_65536.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 13.4
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_ila_65536.vhd
+-- /___/   /\     Timestamp  : Wed Aug 14 09:32:58 BRT 2013
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_ila_65536 IS
+  port (
+    CONTROL: inout std_logic_vector(35 downto 0);
+    CLK: in std_logic;
+    TRIG0: in std_logic_vector(7 downto 0);
+    TRIG1: in std_logic_vector(31 downto 0);
+    TRIG2: in std_logic_vector(31 downto 0);
+    TRIG3: in std_logic_vector(31 downto 0);
+    TRIG4: in std_logic_vector(31 downto 0));
+END chipscope_ila_65536;
+
+ARCHITECTURE chipscope_ila_65536_a OF chipscope_ila_65536 IS
+BEGIN
+
+END chipscope_ila_65536_a;
--- a/hdl/platform/virtex6/chipscope/vio/chipscope_vio_256.ngc
+++ b/hdl/platform/virtex6/chipscope/vio/chipscope_vio_256.ngc
--- a/hdl/platform/virtex6/chipscope/vio/chipscope_vio_256.vhd
+++ b/hdl/platform/virtex6/chipscope/vio/chipscope_vio_256.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 13.4
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_vio_256.vhd
+-- /___/   /\     Timestamp  : Mon Jul 22 09:04:51 BRT 2013
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_vio_256 IS
+  port (
+    CONTROL: inout std_logic_vector(35 downto 0);
+    ASYNC_OUT: out std_logic_vector(255 downto 0));
+END chipscope_vio_256;
+
+ARCHITECTURE chipscope_vio_256_a OF chipscope_vio_256 IS
+BEGIN
+
+END chipscope_vio_256_a;
--- a/hdl/platform/virtex6/chipscope/vio/chipscope_vio_64.ngc
+++ b/hdl/platform/virtex6/chipscope/vio/chipscope_vio_64.ngc
--- a/hdl/platform/virtex6/chipscope/vio/chipscope_vio_64.vhd
+++ b/hdl/platform/virtex6/chipscope/vio/chipscope_vio_64.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 13.4
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_vio_64.vhd
+-- /___/   /\     Timestamp  : Fri Jul 19 12:28:22 BRT 2013
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_vio_64 IS
+  port (
+    CONTROL: inout std_logic_vector(35 downto 0);
+    ASYNC_OUT: out std_logic_vector(63 downto 0));
+END chipscope_vio_64;
+
+ARCHITECTURE chipscope_vio_64_a OF chipscope_vio_64 IS
+BEGIN
+
+END chipscope_vio_64_a;
--- a/hdl/platform/virtex6/ip_cores/Manifest.py
+++ b/hdl/platform/virtex6/ip_cores/Manifest.py
+files = ["dds_adc_input.ngc",
+	"dds_adc_input.v"
+	]
--- a/hdl/platform/virtex6/ip_cores/dds_adc_input.ngc
+++ b/hdl/platform/virtex6/ip_cores/dds_adc_input.ngc
--- a/hdl/platform/virtex6/ip_cores/dds_adc_input.v
+++ b/hdl/platform/virtex6/ip_cores/dds_adc_input.v