modules/*/wb_acq_core/*fc_fifo*: add assertion to detect fifo_fc_mux_cnt signal error

This is related to github issue #52, in that the fifo_fc_mux_cnt signal is different than 0, after the transaction ends. This points to an alignment problem in the acquisition (typically trigger acquisitions) and subsequent transactions could be wrong (first sample belonging to the previous transaction).

modules//wb_acq_core/fc_fifo*: add assertion to detect fifo_fc_mux_cnt signal error
This is related to github issue #52, in that the fifo_fc_mux_cnt signal is different than 0, after the transaction ends. This points to an alignment problem in the acquisition (typically trigger acquisitions) and subsequent transactions could be wrong (first sample belonging to the previous transaction).
c2d45a3a · Lucas Russo · 4c360e95 · c2d45a3a
Commit c2d45a3a authored Jan 13, 2016 by Lucas Russo
Hide whitespace changes
Inline Side-by-side

Showing with 9 additions and 0 deletions

acq_fc_fifo.vhd hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd +9 -0

No files found.
--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd
@@ -442,6 +442,15 @@ begin
    end if;
  end process;

+  -- FOR SIMULATION ONLY
+  -- Assert error if fifo_fc_mux_cnt signal is anything different than zero after the
+  -- end of transaction
+  assert (not(fs_rst_n_i = '1' and ext_rst_n_i = '1') or ((fifo_fc_all_trans_done_lvl = '1' and
+            fifo_fc_mux_cnt = to_unsigned(0, fifo_fc_mux_cnt'length)) or -- end of transaction case
+            (fifo_fc_all_trans_done_sync = '0'))) -- every other case
+  report "[acq_fc_fifo] fifo_fc_mux_cnt signal is not 0 after the end of the transaction!"
+  severity failure;
+
  fifo_fc_mux_inc <= fifo_fc_wr_en when passthrough_en_i = '1' else fifo_fc_dpram_wr_en;

  -- We read the ID FIFO synchronized with the data FIFOs. So, we only need