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Beam Positoning Monitor - Gateware
Commit d1f890a6 authored by Lucas Russo's avatar Lucas Russo
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hdl/modules/*/pcie_a7*: add artix7 debug pins

parent a67f12d2
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Showing with 95 additions and 27 deletions
hdl/modules/dbe_wishbone/wb_pcie/bpm_pcie_a7_pkg.vhd
View file @ d1f890a6
...@@ -14,6 +14,7 @@ package bpm_pcie_a7_pkg is ...@@ -14,6 +14,7 @@ package bpm_pcie_a7_pkg is
generic ( generic (
g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED; g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_ma_address_granularity : t_wishbone_address_granularity := BYTE; g_ma_address_granularity : t_wishbone_address_granularity := BYTE;
g_ext_rst_pin : boolean := true;
g_sim_bypass_init_cal : string := "FAST" g_sim_bypass_init_cal : string := "FAST"
); );
port ( port (
...@@ -109,6 +110,7 @@ package bpm_pcie_a7_pkg is ...@@ -109,6 +110,7 @@ package bpm_pcie_a7_pkg is
generic ( generic (
g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED; g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_ma_address_granularity : t_wishbone_address_granularity := BYTE; g_ma_address_granularity : t_wishbone_address_granularity := BYTE;
g_ext_rst_pin : boolean := true;
g_sim_bypass_init_cal : string := "FAST" g_sim_bypass_init_cal : string := "FAST"
); );
port ( port (
......
hdl/modules/dbe_wishbone/wb_pcie/wb_bpm_pcie_a7.vhd
View file @ d1f890a6
...@@ -29,6 +29,7 @@ entity wb_bpm_pcie_a7 is ...@@ -29,6 +29,7 @@ entity wb_bpm_pcie_a7 is
generic ( generic (
g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED; g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_ma_address_granularity : t_wishbone_address_granularity := BYTE; g_ma_address_granularity : t_wishbone_address_granularity := BYTE;
g_ext_rst_pin : boolean := true;
g_sim_bypass_init_cal : string := "FAST" g_sim_bypass_init_cal : string := "FAST"
); );
port ( port (
...@@ -150,7 +151,8 @@ begin ...@@ -150,7 +151,8 @@ begin
---------------------------------- ----------------------------------
cmp_bpm_pcie_a7 : bpm_pcie_a7 cmp_bpm_pcie_a7 : bpm_pcie_a7
generic map ( generic map (
SIM_BYPASS_INIT_CAL => g_sim_bypass_init_cal SIM_BYPASS_INIT_CAL => g_sim_bypass_init_cal,
EXT_RST_PIN => g_ext_rst_pin
) )
port map ( port map (
--DDR3 memory pins --DDR3 memory pins
...@@ -212,27 +214,27 @@ begin ...@@ -212,27 +214,27 @@ begin
sel_o => wb_ma_pcie_sel_out, sel_o => wb_ma_pcie_sel_out,
cyc_o => wb_ma_pcie_cyc_out, cyc_o => wb_ma_pcie_cyc_out,
-- Additional exported signals for instantiation -- Additional exported signals for instantiation
ext_rst_o => wb_ma_pcie_rst_o ext_rst_o => wb_ma_pcie_rst_o,
);
-- BPM A7 does not have debug signals -- Debug signals
dbg_app_addr_o <= (others => '0'); dbg_app_addr_o => dbg_app_addr_o,
dbg_app_cmd_o <= (others => '0'); dbg_app_cmd_o => dbg_app_cmd_o,
dbg_app_en_o <= '0'; dbg_app_en_o => dbg_app_en_o,
dbg_app_wdf_data_o <= (others => '0'); dbg_app_wdf_data_o => dbg_app_wdf_data_o,
dbg_app_wdf_end_o <= '0'; dbg_app_wdf_end_o => dbg_app_wdf_end_o,
dbg_app_wdf_wren_o <= '0'; dbg_app_wdf_wren_o => dbg_app_wdf_wren_o,
dbg_app_wdf_mask_o <= (others => '0'); dbg_app_wdf_mask_o => dbg_app_wdf_mask_o,
dbg_app_rd_data_o <= (others => '0'); dbg_app_rd_data_o => dbg_app_rd_data_o,
dbg_app_rd_data_end_o <= '0'; dbg_app_rd_data_end_o => dbg_app_rd_data_end_o,
dbg_app_rd_data_valid_o <= '0'; dbg_app_rd_data_valid_o => dbg_app_rd_data_valid_o,
dbg_app_rdy_o <= '0'; dbg_app_rdy_o => dbg_app_rdy_o,
dbg_app_wdf_rdy_o <= '0'; dbg_app_wdf_rdy_o => dbg_app_wdf_rdy_o,
dbg_ddr_ui_clk_o <= '0'; dbg_ddr_ui_clk_o => dbg_ddr_ui_clk_o,
dbg_ddr_ui_reset_o <= '0'; dbg_ddr_ui_reset_o => dbg_ddr_ui_reset_o,
dbg_arb_req_o <= (others => '0'); dbg_arb_req_o => dbg_arb_req_o,
dbg_arb_gnt_o <= (others => '0'); dbg_arb_gnt_o => dbg_arb_gnt_o
);
-- Connect PCIe to the Wishbone Crossbar -- Connect PCIe to the Wishbone Crossbar
wb_ma_sladp_pcie_addr_out(wb_ma_sladp_pcie_addr_out'left downto wb_ma_pcie_addr_out'left+1) wb_ma_sladp_pcie_addr_out(wb_ma_sladp_pcie_addr_out'left downto wb_ma_pcie_addr_out'left+1)
......
hdl/modules/dbe_wishbone/wb_pcie/xwb_bpm_pcie_a7.vhd
View file @ d1f890a6
...@@ -29,6 +29,7 @@ entity xwb_bpm_pcie_a7 is ...@@ -29,6 +29,7 @@ entity xwb_bpm_pcie_a7 is
generic ( generic (
g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED; g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_ma_address_granularity : t_wishbone_address_granularity := BYTE; g_ma_address_granularity : t_wishbone_address_granularity := BYTE;
g_ext_rst_pin : boolean := true;
g_sim_bypass_init_cal : string := "FAST" g_sim_bypass_init_cal : string := "FAST"
); );
port ( port (
...@@ -119,6 +120,7 @@ begin ...@@ -119,6 +120,7 @@ begin
generic map ( generic map (
g_ma_interface_mode => g_ma_interface_mode, g_ma_interface_mode => g_ma_interface_mode,
g_ma_address_granularity => g_ma_address_granularity, g_ma_address_granularity => g_ma_address_granularity,
g_ext_rst_pin => g_ext_rst_pin,
g_sim_bypass_init_cal => g_sim_bypass_init_cal g_sim_bypass_init_cal => g_sim_bypass_init_cal
) )
port map ( port map (
......
hdl/modules/pcie/bpm_pcie_a7.vhd
View file @ d1f890a6
...@@ -39,6 +39,7 @@ use UNISIM.VComponents.all; ...@@ -39,6 +39,7 @@ use UNISIM.VComponents.all;
entity bpm_pcie_a7 is entity bpm_pcie_a7 is
generic ( generic (
SIMULATION : string := "FALSE"; SIMULATION : string := "FALSE";
EXT_RST_PIN : boolean := true;
-- **** -- ****
-- PCIe core parameters -- PCIe core parameters
-- **** -- ****
...@@ -127,7 +128,26 @@ entity bpm_pcie_a7 is ...@@ -127,7 +128,26 @@ entity bpm_pcie_a7 is
CYC_O : out std_logic; CYC_O : out std_logic;
--/ Wishbone interface --/ Wishbone interface
-- Additional exported signals for instantiation -- Additional exported signals for instantiation
ext_rst_o : out std_logic ext_rst_o : out std_logic;
-- Debug signals
dbg_app_addr_o : out std_logic_vector(31 downto 0);
dbg_app_cmd_o : out std_logic_vector(2 downto 0);
dbg_app_en_o : out std_logic;
dbg_app_wdf_data_o : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
dbg_app_wdf_end_o : out std_logic;
dbg_app_wdf_wren_o : out std_logic;
dbg_app_wdf_mask_o : out std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
dbg_app_rd_data_o : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
dbg_app_rd_data_end_o : out std_logic;
dbg_app_rd_data_valid_o : out std_logic;
dbg_app_rdy_o : out std_logic;
dbg_app_wdf_rdy_o : out std_logic;
dbg_ddr_ui_clk_o : out std_logic;
dbg_ddr_ui_reset_o : out std_logic;
dbg_arb_req_o : out std_logic_vector(1 downto 0);
dbg_arb_gnt_o : out std_logic_vector(1 downto 0)
); );
end entity bpm_pcie_a7; end entity bpm_pcie_a7;
...@@ -902,11 +922,18 @@ architecture Behavioral of bpm_pcie_a7 is ...@@ -902,11 +922,18 @@ architecture Behavioral of bpm_pcie_a7 is
begin begin
sys_reset_c <= not sys_reset_n_c; sys_reset_c <= not sys_reset_n_c;
sys_reset_n_ibuf : IBUF
port map ( External_Rst_Pin_On : if (EXT_RST_PIN) generate
O => sys_reset_n_c, sys_reset_n_ibuf : IBUF
I => sys_rst_n port map (
); O => sys_reset_n_c,
I => sys_rst_n
);
end generate;
External_Rst_Pin_Off : if (not EXT_RST_PIN) generate
sys_reset_n_c <= sys_rst_n;
end generate;
pcieclk_ibuf : IBUFDS_GTE2 pcieclk_ibuf : IBUFDS_GTE2
port map ( port map (
...@@ -1547,4 +1574,19 @@ begin ...@@ -1547,4 +1574,19 @@ begin
ddr_sys_reset_i <= ddr_core_rst; ddr_sys_reset_i <= ddr_core_rst;
memc_ui_rst <= ddr_ui_reset; memc_ui_rst <= ddr_ui_reset;
dbg_app_addr_o <= "00" & app_addr;
dbg_app_cmd_o <= app_cmd;
dbg_app_en_o <= app_en;
dbg_app_wdf_data_o <= app_wdf_data;
dbg_app_wdf_end_o <= app_wdf_end;
dbg_app_wdf_wren_o <= app_wdf_wren;
dbg_app_wdf_mask_o <= app_wdf_mask;
dbg_app_rd_data_o <= app_rd_data;
dbg_app_rd_data_end_o <= app_rd_data_end;
dbg_app_rd_data_valid_o <= app_rd_data_valid;
dbg_app_rdy_o <= app_rdy;
dbg_app_wdf_rdy_o <= app_wdf_rdy;
dbg_ddr_ui_clk_o <= ddr_ui_clk;
dbg_ddr_ui_reset_o <= ddr_ui_reset;
end Behavioral; end Behavioral;
hdl/modules/pcie/bpm_pcie_a7_priv_pkg.vhd
View file @ d1f890a6
...@@ -13,6 +13,7 @@ package bpm_pcie_a7_priv_pkg is ...@@ -13,6 +13,7 @@ package bpm_pcie_a7_priv_pkg is
component bpm_pcie_a7 component bpm_pcie_a7
generic ( generic (
SIMULATION : string := "FALSE"; SIMULATION : string := "FALSE";
EXT_RST_PIN : boolean := true;
-- **** -- ****
-- PCIe core parameters -- PCIe core parameters
-- **** -- ****
...@@ -101,7 +102,26 @@ package bpm_pcie_a7_priv_pkg is ...@@ -101,7 +102,26 @@ package bpm_pcie_a7_priv_pkg is
CYC_O : out std_logic; CYC_O : out std_logic;
--/ Wishbone interface --/ Wishbone interface
-- Additional exported signals for instantiation -- Additional exported signals for instantiation
ext_rst_o : out std_logic ext_rst_o : out std_logic;
-- Debug signals
dbg_app_addr_o : out std_logic_vector(31 downto 0);
dbg_app_cmd_o : out std_logic_vector(2 downto 0);
dbg_app_en_o : out std_logic;
dbg_app_wdf_data_o : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
dbg_app_wdf_end_o : out std_logic;
dbg_app_wdf_wren_o : out std_logic;
dbg_app_wdf_mask_o : out std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
dbg_app_rd_data_o : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
dbg_app_rd_data_end_o : out std_logic;
dbg_app_rd_data_valid_o : out std_logic;
dbg_app_rdy_o : out std_logic;
dbg_app_wdf_rdy_o : out std_logic;
dbg_ddr_ui_clk_o : out std_logic;
dbg_ddr_ui_reset_o : out std_logic;
dbg_arb_req_o : out std_logic_vector(1 downto 0);
dbg_arb_gnt_o : out std_logic_vector(1 downto 0)
); );
end component; end component;
......
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