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Beam Positoning Monitor - Gateware
Commit d7bfa3cf authored by Adrian Byszuk's avatar Adrian Byszuk
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Initial upload for the PCIe FPGA firmware

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hdl/README
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......@@ -27,3 +27,20 @@ Modified hdl-make tool in order to allow simulation with ISim Xilinx Simulator
hdl-make2:
https://github.com/lerwys/hdl-make2
===================================
PCIe firmware
===================================
All cores were updated & regenerated with a ISE 14.3 software.
Synthesis and simulation were tested with ISE 14.3.
1. Synthesis
Go to syn/pcie/ directory. Run 'hdlmake' followed with 'make'.
2. Simulation
Go to testbench/pcie/ directory.
Set HOST_PLATFORM, in case of Linux it's either 'lin' or 'lin64'.
Run 'hdlmake'.
In generated Makefile, set TOP_MODULE to 'tf64_pcie_axi'.
Run 'make && make fuse'.
To get ISim window, run generated simulation with 'isim_proj -gui'
hdl/ip_cores/pcie/7k325ffg900/.gitignore 0 → 100644
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#editor temporary files
*~
#Coregen stuff
*.log
*.txt
*.asy
*.vho
*.gise
*.tcl
*.ncf
*.sym
*/example_design/
*/implement/
*/simulation/
hdl/ip_cores/pcie/7k325ffg900/Manifest.py 0 → 100644
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if (action == "synthesis"):
modules = {"local" : ["pcie_core/source"]}
files = ["bram_x64.ngc",
"eb_fifo_counted_resized.ngc",
"mbuf_128x72.ngc",
"prime_FIFO_plain.ngc",
"sfifo_15x128.ngc"]
else:
files = ["bram_x64.vhd",
"eb_fifo_counted_resized.vhd",
"mbuf_128x72.vhd",
"prime_FIFO_plain.vhd",
"sfifo_15x128.vhd"]
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##############################################################
#
# Xilinx Core Generator version 14.3
# Date: Wed Oct 24 16:07:51 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=8
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=bram_x64
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_32bit_address=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET mem_file=no_Mem_file_loaded
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=64
CSET read_width_b=64
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=true
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_bram_block=Stand_Alone
CSET use_byte_write_enable=true
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=4096
CSET write_width_a=64
CSET write_width_b=64
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-09-17T22:14:36Z
# END Extra information
GENERATE
# CRC: bc5af042
hdl/ip_cores/pcie/7k325ffg900/bram_x64.xise 0 → 100644
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# Date: Mon Oct 15 15:11:05 2012
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/
# CRC: fec58bbf
hdl/ip_cores/pcie/7k325ffg900/eb_fifo_counted_resized.ngc 0 → 100644
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##############################################################
#
# Xilinx Core Generator version 14.3
# Date: Wed Oct 24 16:10:21 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=eb_fifo_counted_resized
CSET data_count=false
CSET data_count_width=15
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4096
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=4097
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=28761
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=28760
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=64
CSET input_depth=32768
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=64
CSET output_depth=32768
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=true
CSET read_data_count_width=15
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=true
CSET write_data_count_width=15
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-07-25T18:11:59Z
# END Extra information
GENERATE
# CRC: 8b97417a
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##############################################################
#
# Xilinx Core Generator version 14.3
# Date: Wed Oct 24 16:17:53 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=mbuf_128x72
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=3
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Builtin_FIFO
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=128
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=127
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=72
CSET input_depth=512
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=72
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=9
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=false
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=9
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-07-25T18:11:59Z
# END Extra information
GENERATE
# CRC: e30e9b9c
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##############################################################
#
# Xilinx Core Generator version 14.3
# Date: Wed Oct 24 16:37:55 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:pcie_7x:1.7
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT 7_Series_Integrated_Block_for_PCI_Express xilinx.com:ip:pcie_7x:1.7
# END Select
# BEGIN Parameters
CSET acceptable_l0s_latency=Maximum_of_64_ns
CSET acceptable_l1_latency=No_limit
CSET ack_nak_timeout_func=Absolute
CSET ack_nak_timeout_value=0000
CSET aer_acs_violation=false
CSET aer_atomicop_egress_blocked=false
CSET aer_completer_abort=false
CSET aer_completion_timeout=false
CSET aer_correctable_internal_error=false
CSET aer_ecrc_check_capable=false
CSET aer_ecrc_error=false
CSET aer_enabled=false
CSET aer_flow_control_protocol_error=false
CSET aer_header_log_overflow=false
CSET aer_mc_blocked_tlp=false
CSET aer_multiheader=false
CSET aer_permit_root_error_update=false
CSET aer_receiver_error=false
CSET aer_receiver_overflow=false
CSET aer_surprise_down=false
CSET aer_tlp_prefix_blocked=false
CSET aer_uncorrectable_internal_error=false
CSET ari_forwarding_supported=false
CSET aspm_optionality=false
CSET atomicop32_completer_supported=false
CSET atomicop64_completer_supported=false
CSET atomicop_routing_supported=false
CSET bar0_64bit=false
CSET bar0_enabled=true
CSET bar0_prefetchable=false
CSET bar0_scale=Kilobytes
CSET bar0_size=1
CSET bar0_size_vector=1M
CSET bar0_type=Memory
CSET bar1_64bit=false
CSET bar1_enabled=true
CSET bar1_prefetchable=false
CSET bar1_scale=Megabytes
CSET bar1_size=256
CSET bar1_size_vector=1M
CSET bar1_type=Memory
CSET bar2_64bit=false
CSET bar2_enabled=true
CSET bar2_prefetchable=false
CSET bar2_scale=Megabytes
CSET bar2_size=1
CSET bar2_size_vector=1M
CSET bar2_type=Memory
CSET bar3_64bit=false
CSET bar3_enabled=false
CSET bar3_prefetchable=false
CSET bar3_scale=Kilobytes
CSET bar3_size=2
CSET bar3_size_vector=1M
CSET bar3_type=N/A
CSET bar4_64bit=false
CSET bar4_enabled=false
CSET bar4_prefetchable=false
CSET bar4_scale=Kilobytes
CSET bar4_size=2
CSET bar4_size_vector=1M
CSET bar4_type=N/A
CSET bar5_enabled=false
CSET bar5_prefetchable=false
CSET bar5_scale=Kilobytes
CSET bar5_size=2
CSET bar5_size_vector=1M
CSET bar5_type=N/A
CSET bar_index_value0=0
CSET bar_index_value1=0
CSET bar_index_value2=0
CSET bar_index_value3=0
CSET bar_index_value4=0
CSET bar_index_value5=0
CSET base_class_menu=Data_acquisition_and_signal_processing_controllers
CSET buf_opt_bma=false
CSET cardbus_cis_pointer=00000000
CSET cas128_completer_supported=false
CSET class_code_base=05
CSET class_code_interface=00
CSET class_code_sub=80
CSET component_name=pcie_core
CSET cost_table=1
CSET cpl_finite=false
CSET cpl_timeout_disable_sup=false
CSET cpl_timeout_range=Range_B
CSET d0_pme_support=true
CSET d0_power_consumed=0
CSET d0_power_consumed_factor=0
CSET d0_power_dissipated=0
CSET d0_power_dissipated_factor=0
CSET d1_pme_support=true
CSET d1_power_consumed=0
CSET d1_power_consumed_factor=0
CSET d1_power_dissipated=0
CSET d1_power_dissipated_factor=0
CSET d1_support=false
CSET d2_pme_support=true
CSET d2_power_consumed=0
CSET d2_power_consumed_factor=0
CSET d2_power_dissipated=0
CSET d2_power_dissipated_factor=0
CSET d2_support=false
CSET d3_power_consumed=0
CSET d3_power_consumed_factor=0
CSET d3_power_dissipated=0
CSET d3_power_dissipated_factor=0
CSET d3cold_pme_support=false
CSET d3hot_pme_support=true
CSET de_emph=0
CSET device_id=7021
CSET device_port_type=PCI_Express_Endpoint_device
CSET device_specific_initialization=false
CSET disable_rx_poisoned_resp=false
CSET disable_tx_aspm_l0s=false
CSET dll_link_active_cap=false
CSET downstream_link_num=00
CSET dsn_enabled=true
CSET en_route_err_cor=false
CSET en_route_err_ftl=false
CSET en_route_err_nfl=false
CSET en_route_inta=false
CSET en_route_intb=false
CSET en_route_intc=false
CSET en_route_intd=false
CSET en_route_pm_pme=false
CSET en_route_pme_to=false
CSET en_route_pme_to_ack=false
CSET en_route_unlock=false
CSET enable_ack_nak_timer=false
CSET enable_lane_reversal=false
CSET enable_replay_timer=false
CSET enable_slot_clock_cfg=true
CSET expansion_rom_enabled=false
CSET expansion_rom_scale=Kilobytes
CSET expansion_rom_size=2
CSET ext_pci_cfg_space=false
CSET ext_pci_cfg_space_addr=3FF
CSET extended_tag_default=false
CSET extended_tag_field=false
CSET force_no_scrambling=false
CSET hw_auton_spd_disable=false
CSET interface_width=64_bit
CSET intx_generation=true
CSET io_base_limit_registers=Disabled
CSET legacy_interrupt=INTA
CSET link_speed=5.0_GT/s
CSET max_payload_size=512_bytes
CSET maximum_link_width=X1
CSET mode_selection=Basic
CSET msi_64b=true
CSET msi_enabled=true
CSET msi_vec_mask=false
CSET msix_enabled=false
CSET msix_pba_bir=BAR_0
CSET msix_pba_offset=0
CSET msix_table_bir=BAR_0
CSET msix_table_offset=0
CSET msix_table_size=1
CSET multiple_message_capable=1_vector
CSET no_soft_reset=true
CSET optional_error_support=000000
CSET pci_cfg_space=false
CSET pci_cfg_space_addr=3F
CSET pcie_blk_locn=X0Y0
CSET pcie_cap_slot_implemented=false
CSET pcie_debug_ports=false
CSET pcie_fast_config=None
CSET perf_level=High
CSET phantom_functions=No_function_number_bits_used
CSET pipe_sim=false
CSET prefetchable_memory_base_limit_registers=Disabled
CSET rbar_enabled=false
CSET rbar_initial_value0=0
CSET rbar_initial_value1=0
CSET rbar_initial_value2=0
CSET rbar_initial_value3=0
CSET rbar_initial_value4=0
CSET rbar_initial_value5=0
CSET rbar_num=0
CSET rcb=64_byte
CSET receive_np_request=true
CSET recrc_check=0
CSET recrc_check_trim=false
CSET ref_clk_freq=100_MHz
CSET replay_timeout_func=Add
CSET replay_timeout_value=0000
CSET revision_id=00
CSET root_cap_crs=false
CSET silicon_rev=General_ES
CSET slot_cap_attn_butn=false
CSET slot_cap_attn_ind=false
CSET slot_cap_elec_interlock=false
CSET slot_cap_hotplug_cap=false
CSET slot_cap_hotplug_surprise=false
CSET slot_cap_mrl=false
CSET slot_cap_no_cmd_comp_sup=false
CSET slot_cap_physical_slot_num=0
CSET slot_cap_pwr_ctrl=false
CSET slot_cap_pwr_ind=false
CSET slot_cap_pwr_limit_scale=0
CSET slot_cap_pwr_limit_value=0
CSET sub_class_interface_menu=Other_data_acquisition/signal_processing_controllers
CSET subsystem_id=0007
CSET subsystem_vendor_id=10EE
CSET tph_completer_supported=00
CSET trans_buf_pipeline=None
CSET trgt_link_speed=4'h2
CSET upconfigure_capable=true
CSET ur_atomic=true
CSET ur_inv_req=true
CSET ur_prs_response=true
CSET use_class_code_lookup_assistant=false
CSET user_clk_freq=62.5
CSET vc_cap_enabled=false
CSET vc_cap_reject_snoop=false
CSET vendor_id=10EE
CSET vsec_enabled=false
CSET xlnx_ref_board=None
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-09-21T16:21:42Z
# END Extra information
GENERATE
# CRC: 44793fbc
hdl/ip_cores/pcie/7k325ffg900/pcie_core.xise 0 → 100644
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hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core.vhd 0 → 100755
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hdl/ip_cores/pcie/7k325ffg900/prime_FIFO_plain.ngc 0 → 100644
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hdl/ip_cores/pcie/7k325ffg900/prime_FIFO_plain.vhd 0 → 100644
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hdl/ip_cores/pcie/7k325ffg900/prime_FIFO_plain.xco 0 → 100644
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hdl/ip_cores/pcie/7k325ffg900/prime_FIFO_plain.xise 0 → 100644
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hdl/ip_cores/pcie/7k325ffg900/sfifo_15x128.ngc 0 → 100644
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hdl/ip_cores/pcie/7k325ffg900/sfifo_15x128.vhd 0 → 100644
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hdl/ip_cores/pcie/7k325ffg900/sfifo_15x128.xco 0 → 100644
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hdl/ip_cores/pcie/7k325ffg900/sfifo_15x128.xise 0 → 100644
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hdl/modules/pcie/Manifest.py 0 → 100644
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modules = {"local" : ["common"] }
hdl/modules/pcie/common/.gitignore 0 → 100644
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#editor temporary files
*~
\#*#
*.md
hdl/modules/pcie/common/DDR_Blinker.vhd 0 → 100644
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hdl/modules/pcie/common/DMA_Calculate.vhd 0 → 100644
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hdl/modules/pcie/common/DMA_FSM.vhd 0 → 100644
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hdl/modules/pcie/common/FF_tagram64x36.vhd 0 → 100644
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hdl/modules/pcie/common/FIFO_Wrapper.vhd 0 → 100644
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hdl/modules/pcie/common/FIFO_Wrapper_Loopback.vhd 0 → 100644
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hdl/modules/pcie/common/Interrupts.vhd 0 → 100644
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hdl/modules/pcie/common/Manifest.py 0 → 100644
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files = ["v6abb64Package_efifo_elink.vhd",
"DDR_Blinker.vhd",
"DMA_Calculate.vhd",
"DMA_FSM.vhd",
"FF_tagram64x36.vhd",
"FIFO_Wrapper.vhd",
"FIFO_Wrapper_Loopback.vhd",
"Interrupts.vhd",
"PCIe_UserLogic_00.vhd",
"Registers.vhd",
"RxIn_Delays.vhd",
"Tx_Output_Arbitor.vhd",
"bram_DDRs_Control.vhd",
"bram_DDRs_Control_Loopback.vhd",
"rx_CplD_Channel.vhd",
"rx_MRd_Channel.vhd",
"rx_MWr_Channel.vhd",
"rx_Transact.vhd",
"rx_dsDMA_Channel.vhd",
"rx_usDMA_Channel.vhd",
"tlpControl.vhd",
"tx_Mem_Reader.vhd",
"tx_Transact.vhd"]
hdl/modules/pcie/common/PCIe_UserLogic_00.vhd 0 → 100644
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hdl/modules/pcie/common/Registers.vhd 0 → 100644
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hdl/modules/pcie/common/RxIn_Delays.vhd 0 → 100644
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hdl/modules/pcie/common/Tx_Output_Arbitor.vhd 0 → 100644
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hdl/modules/pcie/common/bram_DDRs_Control.vhd 0 → 100644
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hdl/modules/pcie/common/bram_DDRs_Control_Loopback.vhd 0 → 100644
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hdl/modules/pcie/common/rx_CplD_Channel.vhd 0 → 100644
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hdl/modules/pcie/common/rx_MRd_Channel.vhd 0 → 100644
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hdl/modules/pcie/common/rx_MWr_Channel.vhd 0 → 100644
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hdl/modules/pcie/common/rx_Transact.vhd 0 → 100644
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hdl/modules/pcie/common/rx_dsDMA_Channel.vhd 0 → 100644
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hdl/modules/pcie/common/rx_usDMA_Channel.vhd 0 → 100644
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hdl/modules/pcie/common/tlpControl.vhd 0 → 100644
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hdl/modules/pcie/common/tx_Mem_Reader.vhd 0 → 100644
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hdl/modules/pcie/common/tx_Transact.vhd 0 → 100644
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hdl/modules/pcie/common/v6abb64Package_efifo_elink.vhd 0 → 100644
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hdl/syn/pcie/.gitignore 0 → 100644
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#editor temporary files
*~
#html reports
*.html
#generated bitstream & report
*.bit
*.bgn
hdl/syn/pcie/Manifest.py 0 → 100644
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target = "xilinx"
action = "synthesis"
syn_device = "xc7k325t"
syn_grade = "-2"
syn_package = "ffg900"
syn_top = "bpm_pcie_k7"
syn_project = "bpm_pcie_k7.xise"
modules = {"local" : ["../../top/pcie",
"../../modules/pcie",
"../../ip_cores/pcie/7k325ffg900"]}
files = "xc7k325ffg900.ucf"
hdl/syn/pcie/bpm_pcie_k7.xise 0 → 100644
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hdl/syn/pcie/xc7k325ffg900.ucf 0 → 100644
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hdl/testbench/pcie/.gitignore 0 → 100644
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#ignore temporary editor files
*~
hdl/testbench/pcie/Manifest.py 0 → 100644
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target = "xilinx"
action = "simulation"
syn_project = "bpm_pcie_sim.xise"
#top_module = "tf64_pcie_axi"
modules = {"local" : ["../../modules/pcie",
"../../ip_cores/pcie/7k325ffg900"]}
files = "tf64_pcie_axi.v"
hdl/testbench/pcie/Test01.wcfg 0 → 100644
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hdl/testbench/pcie/tf64_pcie_axi.v 0 → 100644
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hdl/top/pcie/.gitignore 0 → 100644
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hdl/top/pcie/Manifest.py 0 → 100644
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files = "bpm_pcie_k7.vhd"
hdl/top/pcie/bpm_pcie_k7.vhd 0 → 100644
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