modules/dbe_common/*: add heartbeat module

d85f086f · Lucas Russo · 189d2cde · d85f086f · d85f086f · d85f086f
Commit d85f086f authored Jun 06, 2016 by Lucas Russo
4 changed files
--- a/hdl/modules/dbe_common/Manifest.py
+++ b/hdl/modules/dbe_common/Manifest.py
@@ -2,6 +2,7 @@ modules = { "local" : ["reset_synch",
                       "pulse2level",
                       "trigger_rcv",
                       "counter_simple",
-               	       "extend_pulse_dyn"] };
+               	       "extend_pulse_dyn",
+                       "heartbeat"] };

 files = [ "dbe_common_pkg.vhd" ];
--- a/hdl/modules/dbe_common/dbe_common_pkg.vhd
+++ b/hdl/modules/dbe_common/dbe_common_pkg.vhd
@@ -74,5 +74,21 @@ package dbe_common_pkg is
      count_o : out std_logic_vector(g_output_width-1 downto 0));
  end component counter_simple;

+  component heartbeat
+  generic
+  (
+    -- number of system clock cycles to count before blinking
+    g_clk_counts                             : natural := 100000000
+  );
+  port
+  (
+    -- 100 MHz system clock
+    clk_i                                    : in std_logic;
+    rst_n_i                                  : in std_logic;
+
+    -- Heartbeat pulse output
+    heartbeat_o                              : out std_logic
+  );
+  end component;

 end dbe_common_pkg;
--- a/hdl/modules/dbe_common/hearbeat/Manifest.py
+++ b/hdl/modules/dbe_common/hearbeat/Manifest.py
+files = [ "heartbeat.vhd" ];
--- a/hdl/modules/dbe_common/hearbeat/heartbeat.vhd
+++ b/hdl/modules/dbe_common/hearbeat/heartbeat.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Common cores
+use work.genram_pkg.all;
+
+entity heartbeat is
+generic
+(
+  -- number of system clock cycles to count before blinking
+  g_clk_counts                             : natural := 100000000
+);
+port
+(
+  -- 100 MHz system clock
+  clk_i                                    : in std_logic;
+  rst_n_i                                  : in std_logic;
+
+  -- Heartbeat pulse output
+  heartbeat_o                              : out std_logic
+);
+end heartbeat;
+
+architecture rtl of heartbeat is
+
+  constant c_pps_counter_width             : natural := f_log2_size(g_clk_counts);
+  signal hb                                : std_logic := '0';
+  signal pps_counter                       : unsigned(c_pps_counter_width-1 downto 0) :=
+                                               (others => '0');
+begin
+
+  p_heartbeat : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        pps_counter <= to_unsigned(0, pps_counter'length);
+        hb <= '0';
+      else
+        if pps_counter = g_clk_counts-1 then
+          pps_counter <= to_unsigned(0, pps_counter'length);
+          hb <= not hb;
+        else
+         pps_counter <= pps_counter + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  heartbeat_o <= hb;
+
+end rtl;
+