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Commit e5e7e560 authored by Lucas Russo's avatar Lucas Russo
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wb_fmc150_test/verilog: prettier simulation output

parent e7e716e0
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Showing with 365 additions and 70 deletions
general-cores @ d5e1ba04
Subproject commit f7419e91a23aacb3a6675ef28f29267e59b01567
Subproject commit d5e1ba047fa69d2a293deff9ee80131cf77f5f13
hdl/sim/wishbone_test_master.v
View file @ e5e7e560
......@@ -29,7 +29,9 @@
`define WB_BWSEL_WIDTH ((`WB_DATA_BUS_WIDTH + 7) / 8)
module WB_TEST_MASTER;
module WB_TEST_MASTER(
wb_clk
);
// these signals make the WB bus, which can be accessed from outside the module
reg [`WB_ADDRESS_BUS_WIDTH - 1 : 0] wb_addr = 0;
reg [`WB_DATA_BUS_WIDTH - 1 : 0] wb_data_o = 0;
......@@ -39,9 +41,9 @@ module WB_TEST_MASTER;
reg wb_cyc = 0;
reg wb_stb = 0;
reg wb_we = 0;
reg wb_rst = 0;
reg wb_clk = 1;
//reg wb_rst = 0;
//reg wb_clk = 1;
input wb_clk;
reg wb_tb_verbose = 1;
reg wb_monitor_bus = 1;
......@@ -51,12 +53,13 @@ module WB_TEST_MASTER;
// ready signal. 1 indicates that WB_TEST unit is initialized and ready for commands
reg ready = 0;
// Generated outside this module
// generate the WB bus clock
always #(`WB_CLOCK_PERIOD/2) wb_clk <= ~wb_clk;
//always #(`WB_CLOCK_PERIOD/2) wb_clk <= ~wb_clk;
// generate the reset and ready signals
initial begin
#(`WB_RESET_DELAY) wb_rst <= 1;
//#(`WB_RESET_DELAY) wb_rst <= 1;
#(`WB_CLOCK_PERIOD*2) ready <= 1;
end
......@@ -90,8 +93,8 @@ module WB_TEST_MASTER;
$time, (size==1?"byte":((size==2)?"short":"int")),
addr, data_i);
else // !rw
$display("@%0d: WB read %s: addr %x",
$time, (size==1?"byte":((size==2)?"short":"int")),
$display("@%0d: WB read %s: addr %x",
$time, (size==1?"byte":((size==2)?"short":"int")),
addr);
end // wb_tb_verbose
......
hdl/testbench/wishbone/wb_fmc150_test/verilog/Makefile
View file @ e5e7e560
......@@ -76,6 +76,11 @@ VHDL_SRC := ../../../../modules/custom_wishbone/custom_wishbone_pkg.vhd \
../../../../modules/custom_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd \
../../../../modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd \
../../../../modules/custom_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd \
../../../../modules/custom_wishbone/wb_fmc150/sim/ads62p49_init_mem.vhd \
../../../../modules/custom_wishbone/wb_fmc150/sim/amc7823_init_mem.vhd \
../../../../modules/custom_wishbone/wb_fmc150/sim/cdce72010_init_mem_ext.vhd \
../../../../modules/custom_wishbone/wb_fmc150/sim/cdce72010_init_mem_int.vhd \
../../../../modules/custom_wishbone/wb_fmc150/sim/dac3283_init_mem.vhd \
../../../../modules/custom_common/reset_synch/reset_synch.vhd \
../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
......@@ -170,6 +175,11 @@ work/fmc150_spi_ctrl/.fmc150_spi_ctrl_vhd \
work/fmc150_stellar_cmd/.fmc150_stellar_cmd_vhd \
work/fmc150_testbench/.fmc150_testbench_vhd \
work/pulse2pulse/.pulse2pulse_vhd \
work/ads62p49_init_mem/.ads62p49_init_mem_vhd \
work/amc7823_init_mem/.amc7823_init_mem_vhd \
work/cdce72010_init_mem_ext/.cdce72010_init_mem_ext_vhd \
work/cdce72010_init_mem_int/.cdce72010_init_mem_int_vhd \
work/dac3283_init_mem/.dac3283_init_mem_vhd \
work/reset_synch/.reset_synch_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/gc_crc_gen/.gc_crc_gen_vhd \
......@@ -563,6 +573,46 @@ work/pulse2pulse/.pulse2pulse_vhd: ../../../../modules/custom_wishbone/wb_fmc150
work/pulse2pulse/.pulse2pulse:
@mkdir -p $(dir $@) && touch $@
work/ads62p49_init_mem/.ads62p49_init_mem_vhd: ../../../../modules/custom_wishbone/wb_fmc150/sim/ads62p49_init_mem.vhd work/ads62p49_init_mem/.ads62p49_init_mem
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/ads62p49_init_mem/.ads62p49_init_mem:
@mkdir -p $(dir $@) && touch $@
work/amc7823_init_mem/.amc7823_init_mem_vhd: ../../../../modules/custom_wishbone/wb_fmc150/sim/amc7823_init_mem.vhd work/amc7823_init_mem/.amc7823_init_mem
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/amc7823_init_mem/.amc7823_init_mem:
@mkdir -p $(dir $@) && touch $@
work/cdce72010_init_mem_ext/.cdce72010_init_mem_ext_vhd: ../../../../modules/custom_wishbone/wb_fmc150/sim/cdce72010_init_mem_ext.vhd work/cdce72010_init_mem_ext/.cdce72010_init_mem_ext
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/cdce72010_init_mem_ext/.cdce72010_init_mem_ext:
@mkdir -p $(dir $@) && touch $@
work/cdce72010_init_mem_int/.cdce72010_init_mem_int_vhd: ../../../../modules/custom_wishbone/wb_fmc150/sim/cdce72010_init_mem_int.vhd work/cdce72010_init_mem_int/.cdce72010_init_mem_int
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/cdce72010_init_mem_int/.cdce72010_init_mem_int:
@mkdir -p $(dir $@) && touch $@
work/dac3283_init_mem/.dac3283_init_mem_vhd: ../../../../modules/custom_wishbone/wb_fmc150/sim/dac3283_init_mem.vhd work/dac3283_init_mem/.dac3283_init_mem
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/dac3283_init_mem/.dac3283_init_mem:
@mkdir -p $(dir $@) && touch $@
work/reset_synch/.reset_synch_vhd: ../../../../modules/custom_common/reset_synch/reset_synch.vhd work/reset_synch/.reset_synch
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
......
hdl/testbench/wishbone/wb_fmc150_test/verilog/wb_fmc150_tb.v
View file @ e5e7e560
......@@ -28,16 +28,18 @@ module wb_fmc150_tb;
reg s_adc_data_valid;
// Wishbone signals
//reg
// Local definitions
localparam adc_data_max = (2**`ADC_DATA_WIDTH)-1;
localparam adc_gen_threshold = 0.5;
// Word (32-bit) granularity
localparam g_granularity = 4;
// After reset delay
localparam g_after_reset_delay = 4;
// Internal registers
reg zero_bit = 1'b0;
reg spi_busy;
reg [`WB_ADDRESS_BUS_WIDTH-1:0] data_out;
// Clock and Reset
......@@ -63,10 +65,10 @@ module wb_fmc150_tb;
//reg wb_clk = 1;
// Wiswhbone Master
WB_TEST_MASTER cmp_wb_master();
WB_TEST_MASTER cmp_wb_master(.wb_clk(s_clk_sys));
// Enable cmp_wb_master verbosity and bus monitoring
initial begin
// Enable cmp_wb_master verbosity and bus monitoring
// Enable verbose mode
wb_fmc150_tb.cmp_wb_master.verbose(1);
// Enable monitor bus
......@@ -77,15 +79,55 @@ module wb_fmc150_tb;
s_adc_chb_data <= 'h0;
s_adc_data_valid <= 'h0;
#(`CLK_SYS_PERIOD);
// Wait next clock cycle
@(posedge s_clk_sys);
// Wait until reset is done
while (!rstn) begin
$display("@%0d: Waiting for reset completion.", $time);
@(posedge s_clk_sys);
end
$display("@%0d: Reset done!", $time);
// wait a few cycles before stimulus. Synchronizer chains needs to
// update...
//#(g_after_reset_delay * `CLK_SYS_PERIOD);
repeat (g_after_reset_delay) begin
@(posedge s_clk_sys);
end
$display("@%0d: Initializing FMC150 chips...", $time);
// Waits until FMC150 chips are done initializing
fmc150_spi_busy(spi_busy);
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
while (spi_busy) begin
fmc150_spi_busy(spi_busy);
// Wait for chips to be initialized...
repeat (128) begin
@(posedge s_clk_sys);
end
//$display(".");
end
$display("@%0d, FMC150 chips initialized!", $time);
// Wait next clock cycle
@(posedge s_clk_sys);
// Write some values to FMC150 registers
$display("----------------------------------");
$display("@%0d, Writing 32'h682C0290 to FMC150_CS_CDCE72010...", $time);
$display("----------------------------------");
write_fmc150_reg(`FMC150_CS_CDCE72010, 32'h0, 32'h682C0290);
// Long Delay as the cores have a "long" delay to output the data
#(128 * `CLK_SYS_PERIOD);
// Wait next clock cycle
@(posedge s_clk_sys);
// Read some values to FMC150 registers
$display("----------------------------------");
$display("@%0d, Reading FMC150_CS_CDCE72010...", $time);
$display("----------------------------------");
read_fmc150_reg(`FMC150_CS_CDCE72010, 32'h0, data_out);
end
......@@ -260,16 +302,19 @@ module wb_fmc150_tb;
wb_fmc150_tb.cmp_wb_master.read32(`ADDR_FMC150_FLGS_IN, aux_val);
// This bits do not make sense for this register
//aux_val[`WB_DATA_BUS_WIDTH - 1 : 2] = 'h0;
#(`CLK_SYS_PERIOD);
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
// Write SPI RW bit to write op
wb_fmc150_tb.cmp_wb_master.write32(`ADDR_FMC150_FLGS_IN,
aux_val & ~`FMC150_FLGS_IN_SPI_RW);
// Write internal chip addr
wb_fmc150_tb.cmp_wb_master.write32(`ADDR_FMC150_ADDR, addr_i);
#(`CLK_SYS_PERIOD);
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
// Write internal chip data
wb_fmc150_tb.cmp_wb_master.write32(`ADDR_FMC150_DATA_IN, data_i);
#(`CLK_SYS_PERIOD);
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
// Read currently CS field
wb_fmc150_tb.cmp_wb_master.read32(`ADDR_FMC150_CS, aux_val);
......@@ -277,10 +322,12 @@ module wb_fmc150_tb;
//aux_val[`WB_DATA_BUS_WIDTH - 1 : 4] = 'h0;
// Toggle Chipselect field
aux_val = aux_val ^ cs_i;
#(`CLK_SYS_PERIOD);
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
// Write chipselect to correspondent field
wb_fmc150_tb.cmp_wb_master.write32(`ADDR_FMC150_CS, aux_val);
#(`CLK_SYS_PERIOD);
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
end
endtask // write_fmc150_reg
......@@ -319,52 +366,75 @@ module wb_fmc150_tb;
output [`WB_DATA_BUS_WIDTH - 1 : 0] data_o;
begin : read_fmc150_reg_body
reg [`WB_DATA_BUS_WIDTH - 1 : 0] aux_val;
reg spi_busy;
// Verify if busy bit is set
wb_fmc150_tb.cmp_wb_master.read32(`ADDR_FMC150_FLGS_OUT, aux_val);
aux_val = aux_val & `FMC150_FLGS_OUT_SPI_BUSY;
#(`CLK_SYS_PERIOD);
// Busy loop until spi is not busy
//while (aux_val) begin
// wb_fmc150_tb.cmp_wb_master.read32(`ADDR_FMC150_FLGS_OUT, aux_val);
// aux_val = aux_val & `FMC150_FLGS_OUT_SPI_BUSY;
// #(`CLK_SYS_PERIOD);
//end
if (aux_val) begin
$display("SPI is busy!");
$finish;
end
//wb_fmc150_tb.cmp_wb_master.read32(`ADDR_FMC150_FLGS_OUT, aux_val);
//aux_val = aux_val & `FMC150_FLGS_OUT_SPI_BUSY;
//#(`CLK_SYS_PERIOD);
// Verify if busy bit is set
fmc150_spi_busy(spi_busy);
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
// Busy loop until spi is not busy
//while (aux_val) begin
// wb_fmc150_tb.cmp_wb_master.read32(`ADDR_FMC150_FLGS_OUT, aux_val);
// aux_val = aux_val & `FMC150_FLGS_OUT_SPI_BUSY;
// #(`CLK_SYS_PERIOD);
//end
if (spi_busy) begin
$display("SPI is busy!");
$finish;
end
// Read SPI RW bit
wb_fmc150_tb.cmp_wb_master.read32(`ADDR_FMC150_FLGS_IN, aux_val);
#(`CLK_SYS_PERIOD);
// Write SPI RW bit to read op
wb_fmc150_tb.cmp_wb_master.write32(`ADDR_FMC150_FLGS_IN,
aux_val | `FMC150_FLGS_IN_SPI_RW);
// Write internal chip addr
wb_fmc150_tb.cmp_wb_master.write32(`ADDR_FMC150_ADDR, addr_i);
#(`CLK_SYS_PERIOD);
// Read currently CS field
wb_fmc150_tb.cmp_wb_master.read32(`ADDR_FMC150_CS, aux_val);
// This bits do not make sense for this register
//aux_val[`WB_DATA_BUS_WIDTH - 1 : 4] = 'h0;
// Toggle Chipselect field
aux_val = aux_val ^ cs_i;
#(`CLK_SYS_PERIOD);
// Write chipselect to correspondent field
wb_fmc150_tb.cmp_wb_master.write32(`ADDR_FMC150_CS, aux_val);
#(`CLK_SYS_PERIOD);
// Read SPI RW bit
wb_fmc150_tb.cmp_wb_master.read32(`ADDR_FMC150_FLGS_IN, aux_val);
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
// Write SPI RW bit to read op
wb_fmc150_tb.cmp_wb_master.write32(`ADDR_FMC150_FLGS_IN,
aux_val | `FMC150_FLGS_IN_SPI_RW);
// Read data
wb_fmc150_tb.cmp_wb_master.write32(`ADDR_FMC150_DATA_OUT, aux_val);
#(`CLK_SYS_PERIOD);
data_o = aux_val;
end
// Write internal chip addr
wb_fmc150_tb.cmp_wb_master.write32(`ADDR_FMC150_ADDR, addr_i);
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
// Read currently CS field
wb_fmc150_tb.cmp_wb_master.read32(`ADDR_FMC150_CS, aux_val);
// This bits do not make sense for this register
//aux_val[`WB_DATA_BUS_WIDTH - 1 : 4] = 'h0;
// Toggle Chipselect field
aux_val = aux_val ^ cs_i;
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
// Write chipselect to correspondent field
wb_fmc150_tb.cmp_wb_master.write32(`ADDR_FMC150_CS, aux_val);
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
// Read data
wb_fmc150_tb.cmp_wb_master.read32(`ADDR_FMC150_DATA_OUT, aux_val);
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
data_o = aux_val;
end
endtask
task fmc150_spi_busy;
output reg spi_busy;
begin : fmc150_spi_busy_body
reg [`WB_DATA_BUS_WIDTH - 1 : 0] aux_val;
// Verify if busy bit is set
wb_fmc150_tb.cmp_wb_master.read32(`ADDR_FMC150_FLGS_OUT, aux_val);
//aux_val = aux_val & `FMC150_FLGS_OUT_SPI_BUSY;
//#(`CLK_SYS_PERIOD);
@(posedge s_clk_sys);
// output spi busy bit
spi_busy = aux_val[`FMC150_FLGS_OUT_SPI_BUSY_OFFSET];
end
endtask
endmodule
......
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