hdl/modules/fmc_adc_common/*: add option to use an external referece clock

Add option to use an external supplied clock (usually from another PLL or global clock buffer inside the FPGA) to clock the data to downstream FPGA logic. This implies the ASYNC FIFO after the first ADC acquisition and the synchronization betweem multiple ADC channels. This is useful when instantiating more than one ADC module, as we don't need two reference clocks and more than one reference would only make things harder.

hdl/modules/fmc_adc_common/*: add option to use an external referece clock
Add option to use an external supplied clock (usually from another PLL or global clock buffer inside the FPGA) to clock the data to downstream FPGA logic. This implies the ASYNC FIFO after the first ADC acquisition and the synchronization betweem multiple ADC channels. This is useful when instantiating more than one ADC module, as we don't need two reference clocks and more than one reference would only make things harder.
ff801040 · Lucas Russo · 57aa80c4 · ff801040 · ff801040
Commit ff801040 authored May 05, 2014 by Lucas Russo
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Showing with 27 additions and 3 deletions

fmc_adc_iface.vhd hdl/modules/fmc_adc_common/fmc_adc_iface.vhd +20 -2

fmc_adc_pkg.vhd hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd +7 -1

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--- a/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd
+++ b/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd
@@ -84,6 +84,11 @@ port
  -- ADC clock + data single ended inputs (from the top module)
  adc_in_sdr_i                              : in t_adc_sdr_in_array(c_num_adc_channels-1 downto 0);

+  -----------------------------
+  -- Optional external reference clock port
+  -----------------------------
+  adc_ext_glob_clk_i                        : in t_adc_clk_chain_glob;
+
  -----------------------------
  -- ADC Delay signals
  -----------------------------
@@ -148,6 +153,8 @@ architecture rtl of fmc_adc_iface is
  --signal adc_data_chain_out                 : t_adc_int_array(c_num_adc_channels-1 downto 0);

  --type t_adc_fn_dly_val_array is array (natural range <>) of std_logic_vector(4 downto 0);
+  -- Optional external global clock
+  signal adc_clk_chain_glob_int             : t_adc_clk_chain_glob;

  -- ADC fine delay internal signal
  signal adc_data_dly_sel_int               : std_logic_vector(c_num_in_adc_pins-1 downto 0);
@@ -200,6 +207,7 @@ begin
        g_delay_type                        => g_delay_type,
        g_adc_clock_period                  => g_adc_clk_period_values(i),
        g_default_adc_clk_delay             => g_clk_default_dly(i),
+        -- This will always fail if we use an external clock, as expected
        g_with_ref_clk                      => f_with_ref_clk(i, g_ref_clk),
        g_mmcm_param                        => g_mmcm_param,
        g_with_fn_dly_select                => g_with_fn_dly_select,
@@ -234,6 +242,16 @@ begin

    end generate;

+    -- Give the user the possibility to use an external clock for
+    -- as the global clocks
+    gen_ext_adc_glob_clk : if g_ref_clk = c_num_adc_channels generate
+      adc_clk_chain_glob_int <= adc_ext_glob_clk_i;
+    end generate;
+
+    gen_without_ext_adc_glob_clk : if g_ref_clk /= c_num_adc_channels generate
+      adc_clk_chain_glob_int <= adc_clk_chain_glob(g_ref_clk);
+    end generate;
+
    -- Default mmcm_locked signals to 1 is this chain is not used
    gen_mmcm_locked_clock_chains : if (g_use_clk_chains(i) = '0') generate
      adc_clk_chain_glob(i).mmcm_adc_locked <= '1';
@@ -283,7 +301,7 @@ begin
            -- Input Clocks from fmc_adc_clk signals
            -----------------------------
            adc_clk_chain_priv_i                => adc_clk_chain_priv(chain_intercon(i)),
-            adc_clk_chain_glob_i                => adc_clk_chain_glob(g_ref_clk),
+            adc_clk_chain_glob_i                => adc_clk_chain_glob_int,

            -----------------------------
            -- ADC Data Delay signals.
@@ -332,7 +350,7 @@ begin
    adc_out_i                              => adc_out_int,

    -- Reference clock for synchronization with all data chains
-    adc_refclk_i                            => adc_clk_chain_glob(g_ref_clk),
+    adc_refclk_i                            => adc_clk_chain_glob_int,

    -----------------------------
    -- ADC output signals. Synchronous to a single clock

--- a/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd
+++ b/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd
@@ -204,7 +204,8 @@ package fmc_adc_pkg is
  subtype t_clk_use_bufio_chain is std_logic_vector(c_num_adc_channels-1 downto 0);
  subtype t_clk_use_bufr_chain is std_logic_vector(c_num_adc_channels-1 downto 0);
  subtype t_map_clk_data_chain is t_integer_array(c_num_adc_channels-1 downto 0);
-  subtype t_ref_adc_clk is natural range 0 to c_num_adc_channels-1;
+  -- The last channel is reserved for an external clock
+  subtype t_ref_adc_clk is natural range 0 to c_num_adc_channels;

  -- Constant default values.
  constant default_adc_clk_period : real := 4.0; -- 250 MHz
@@ -475,6 +476,11 @@ package fmc_adc_pkg is
    -- ADC clock + data single ended inputs (from the top module)
    adc_in_sdr_i                              : in t_adc_sdr_in_array(c_num_adc_channels-1 downto 0);

+    -----------------------------
+    -- Optional external reference clock port
+    -----------------------------
+    adc_ext_glob_clk_i                        : in t_adc_clk_chain_glob;
+
    -----------------------------
    -- ADC Delay signals.
    -----------------------------