This is for safety until we export these
signals to wishbone.

Using VHDL dor DDR core issues an error.
No idea when that happens, unless re-target
my project for Verilog and regenerate the DDR
core.

This is needed as dsp-cores changed
xwb_position_calc_core interface.

This is a simple fix, just selecting a single
channel to server as a valid reference.

Now, we have the option to use a valid
bit in the ACQ core for ADC that are very
slow compared to the input clock frequency,
such as the FMCPICO_1M.

We are still missing position_calc_core
ADC/ADCSWAP valid bits.

We were instantiating the FMCPICO inside
the FMC250 generate statement.

This is just a commit fixing typos.

This eases the addition of new ADCs with
width larger than 16-bits, like the FMCPICO_1M.

We were using this so to simplify
the assignments in acquisition core,
but this came with extra VHDL complexity.

Better to leave as is and deal with this in
software later.

To use the FMC2 EEPROM we must use the FMC1
I2C.

Previously we were not sign-extending
the FMCPICO_1M ADC bits, but zero-padding.

These signals are connected through an
external MUX. So, we must use the FMC1
ports to access the FMC2.

The board supports from 1.8 to 3.3.
So we are safe.

As a workaround we can finish the TCL
constraint command with ";".