Add driver & board tests. testDMA.cpp tests real hardware, while the rest of units test driver/library functionality.

Conflicts:
	hdl/ip_cores/general-cores
	hdl/syn/pcie/.gitignore
	scripts/jtag_comm.tcl
	scripts/jtag_main

Add Wishbone endpoint support: 64 bit data width, no granularity, 29 bit address width. Also, fix some SDRAM data issues.

Now we specify which adc clock will serve as a reference
for all adc data paths

In this way, we can transmit the raw adc data through all FPGA logic,
safely. Be aware though, that one must be careful with this simple
"trick". If the driving clocks are too different, in frequency, from
one another we could have some inconsistencies. This, however, should
not be the case as, by default, we work with the same clocks
for all channels (chains).

The xwb_spi interface was changed and will be referenced in the next
commit (update submodule)