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Lucas Russo authored
Using VHDL dor DDR core issues an error. No idea when that happens, unless re-target my project for Verilog and regenerate the DDR core.
2d242771
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pcie_core.xci |
Using VHDL dor DDR core issues an error. No idea when that happens, unless re-target my project for Verilog and regenerate the DDR core.
Name |
Last commit
|
Last update |
---|---|---|
.. | ||
Manifest.py | Loading commit data... | |
pcie_core.xci | Loading commit data... |