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Lucas Russo authored
Using VHDL dor DDR core issues an error. No idea when that happens, unless re-target my project for Verilog and regenerate the DDR core.
2d242771
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| .. | ||
| axi_datamover_0 | ||
| axi_datamover_bpm | ||
| axi_interconnect | ||
| axi_interconnect_bpm | ||
| ddr_core | ||
| pcie_core | ||
| .gitignore | ||
| Manifest.py | ||
| ipcores_pkg.vhd |