hdl/testbench/wishbone/wb_acq_core_test/verilog/virtex6 · 5ec1cba36b4fd6f378888f75d14814189899a6b0 · Projects / Beam Positoning Monitor - Gateware · Open Hardware Repository

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hdl/testbench/*/*_acq_core_test/*: move virtex6 sim to specific folder · 65d8c401
Lucas Russo authored Sep 08, 2014
```
This will allow adding more wb_acq_core simulations more easily
and for different FPGA families.
```
65d8c401

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