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Lucas Russo authored
This will allow adding more wb_acq_core simulations more easily and for different FPGA families.
65d8c401
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Makefile | ||
Manifest.py | ||
clk_rst.v | ||
defines.v | ||
run.do | ||
timescale.v | ||
wave_compl.do | ||
wb_acq_core_tb.v |