-
Lucas Russo authored
Using VHDL dor DDR core issues an error. No idea when that happens, unless re-target my project for Verilog and regenerate the DDR core.
2d242771
Name |
Last commit
|
Last update |
---|---|---|
.. | ||
Manifest.py | ||
axi_datamover_bpm.xci | ||
axi_datamover_bpm.xml |