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Conv TTL Blocking
Commit 62b1c43a authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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i2c documentation up-to-date. Added .gitignore in the i2c_slave_wb_master… 

i2c documentation up-to-date. Added .gitignore in the i2c_slave_wb_master folder. Everything is correctly synched in this folder.
parent a8566fda
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hdl/ctdah_lib/test/wishbone_driver.vhd
View file @ 62b1c43a
...@@ -24,7 +24,7 @@ entity wishbone_driver is ...@@ -24,7 +24,7 @@ entity wishbone_driver is
wb_rty_i : in STD_LOGIC; wb_rty_i : in STD_LOGIC;
wb_err_i : in STD_LOGIC; wb_err_i : in STD_LOGIC;
data_i : in STD_LOGIC_VECTOR(g_WB_DATA_O_LENGTH - 1 downto 0); data_i : in STD_LOGIC_VECTOR(g_WB_DATA_O_LENGTH - 1 downto 0);
data_o : out STD_LOGIC_VECTOR(g_WB_DATA_I_LENGTH - 1 downto 0); data_o : out STD_LOGIC_VECTOR(g_WB_DATA_I_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0); addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0);
...@@ -34,7 +34,7 @@ entity wishbone_driver is ...@@ -34,7 +34,7 @@ entity wishbone_driver is
read_done_o : out STD_LOGIC); read_done_o : out STD_LOGIC);
end wishbone_driver; end wishbone_driver;
architecture Behavioral of wishbone_driver is architecture Behavioral of wishbone_driver is
begin begin
...@@ -74,15 +74,15 @@ begin ...@@ -74,15 +74,15 @@ begin
wb_sel_o <= (others => '0'); wb_sel_o <= (others => '0');
write_done_o <= '1'; write_done_o <= '1';
else else
wb_stb_o <= '0'; wb_stb_o <= '0';
wb_cyc_o <= '0'; wb_cyc_o <= '0';
wb_sel_o <= (others => '0'); wb_sel_o <= (others => '0');
wb_we_o <= '0'; wb_we_o <= '0';
wb_data_o <= (others => '0'); wb_data_o <= (others => '0');
wb_addr_o <= (others => '0'); wb_addr_o <= (others => '0');
data_o <= (others => '0'); data_o <= (others => '0');
write_done_o <= '0'; write_done_o <= '0';
read_done_o <= '0'; read_done_o <= '0';
end if; end if;
wait until rising_edge(wb_clk_i); wait until rising_edge(wb_clk_i);
end process; end process;
......
hdl/ctdah_lib/test/wishbone_driver_pkg.vhd
View file @ 62b1c43a
...@@ -11,7 +11,7 @@ package wishbone_driver_pkg is ...@@ -11,7 +11,7 @@ package wishbone_driver_pkg is
g_WB_CLK_PERIOD : TIME := 50 ns); g_WB_CLK_PERIOD : TIME := 50 ns);
port(wb_clk_i : in STD_LOGIC; port(wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC; wb_rst_i : in STD_LOGIC;
wb_stb_o : out STD_LOGIC; wb_stb_o : out STD_LOGIC;
wb_cyc_o : out STD_LOGIC; wb_cyc_o : out STD_LOGIC;
wb_sel_o : out STD_LOGIC_VECTOR(3 downto 0); wb_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
...@@ -22,11 +22,11 @@ package wishbone_driver_pkg is ...@@ -22,11 +22,11 @@ package wishbone_driver_pkg is
wb_ack_i : in STD_LOGIC; wb_ack_i : in STD_LOGIC;
wb_rty_i : in STD_LOGIC; wb_rty_i : in STD_LOGIC;
wb_err_i : in STD_LOGIC; wb_err_i : in STD_LOGIC;
data_i : in STD_LOGIC_VECTOR(g_WB_DATA_O_LENGTH - 1 downto 0); data_i : in STD_LOGIC_VECTOR(g_WB_DATA_O_LENGTH - 1 downto 0);
data_o : out STD_LOGIC_VECTOR(g_WB_DATA_I_LENGTH - 1 downto 0); data_o : out STD_LOGIC_VECTOR(g_WB_DATA_I_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0); addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0);
write_i : in STD_LOGIC; write_i : in STD_LOGIC;
write_done_o : out STD_LOGIC; write_done_o : out STD_LOGIC;
read_i : in STD_LOGIC; read_i : in STD_LOGIC;
......
hdl/i2c_slave_wb_master/.gitignore 0 → 100644
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#Ignore LaTeX trash
./doc/.*
./doc/.*.swo
./doc/.*.swp
./doc/Figures/*.eps
#Ignore autotrash from ISE
./project/
!/project/project.gise
!/project/project.xise
!/project/waveform/
#Ignore swap files at rtl/ and test/ folders
./rtl/.*.swo
./rtl/.*.swp
./test/.*.swo
./test/.*.swp
hdl/i2c_slave_wb_master/doc/Figures/clk_fsm.svg 0 → 100644
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hdl/i2c_slave_wb_master/doc/i2cSpecs.pdf 100755 → 100644
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hdl/i2c_slave_wb_master/doc/i2cSpecs.tex 100755 → 100644
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hdl/i2c_slave_wb_master/project/modelsim/wave.do deleted 100755 → 0
View file @ a8566fda
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /i2c_slave_top_tb/wb_clk
add wave -noupdate /i2c_slave_top_tb/wb_rst_i
add wave -noupdate -group I2C /i2c_slave_top_tb/uut/sda_oen
add wave -noupdate -group I2C /i2c_slave_top_tb/uut/sda_o
add wave -noupdate -group I2C /i2c_slave_top_tb/uut/sda_i
add wave -noupdate -group I2C /i2c_slave_top_tb/uut/scl_i
add wave -noupdate -group i2c_bit -height 16 /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/i2c_bit_fsm
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/s_sda_dGLITCH_d1
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/s_scl_dGLITCH_d1
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/s_scl_rising
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/s_scl_falling
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/done
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_done_d1
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_done_d2
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/start_o
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/pause_o
add wave -noupdate -group i2c_bit /i2c_slave_top_tb/uut/inst_i2c_slave_core/inst_i2c_bit/rcved_o
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/pf_wb_addr_o
add wave -noupdate -group wishbone_MASTER -height 16 /i2c_slave_top_tb/uut/inst_i2c_regs/i2c_master_WB_BASIC_fsm
add wave -noupdate -group wishbone_MASTER /i2c_slave_top_tb/uut/wb_master_cyc_o
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_stb_o
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_sel_o
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_we_o
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_data_i
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_data_o
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_addr_o
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_ack_i
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_rty_i
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_err_i
add wave -noupdate -group wishbone_MASTER -radix hexadecimal /i2c_slave_top_tb/wb_master_cyc_o
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_cyc_i
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_stb_i
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_sel_i
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_we_i
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_data_i
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_data_o
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_addr_i
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_ack_o
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_rty_o
add wave -noupdate -group wishbone_SLAVE -radix hexadecimal /i2c_slave_top_tb/wb_slave_err_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/PRE_i
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/CTR0_i
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/CTR1_i
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/STA_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX0_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX1_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX2_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX3_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX4_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DRX5_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DTX0_i
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DTX1_i
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DTX2_i
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/DTX3_i
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm_next
add wave -noupdate -height 16 /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm_previous
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm_previous_start
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_byte_cnt
add wave -noupdate -group {gc ff0} /i2c_slave_top_tb/uut/inst_i2c_slave_core/ff_i2c_bit0/Q
add wave -noupdate -group {gc ff0} /i2c_slave_top_tb/uut/inst_i2c_slave_core/ff_i2c_bit0/C
add wave -noupdate -group {gc ff0} /i2c_slave_top_tb/uut/inst_i2c_slave_core/ff_i2c_bit0/CLR
add wave -noupdate -group {gc ff0} /i2c_slave_top_tb/uut/inst_i2c_slave_core/ff_i2c_bit0/D
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_rx_fifo_flush
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_i2c_addr
add wave -noupdate -radix binary /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_rx_fifo_din
add wave -noupdate -group {bit count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/clk_i
add wave -noupdate -group {bit count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/rst_i
add wave -noupdate -group {bit count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/en_i
add wave -noupdate -group {bit count} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/bit_counter_8/cnt_o
add wave -noupdate -expand -group {byte count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/clk_i
add wave -noupdate -expand -group {byte count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/rst_i
add wave -noupdate -expand -group {byte count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/en_i
add wave -noupdate -expand -group {byte count} /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/cnt_o
add wave -noupdate -group {rx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/reg_i
add wave -noupdate -group {rx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/clk
add wave -noupdate -group {rx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/push
add wave -noupdate -group {rx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/flush
add wave -noupdate -group {rx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/reg_o
add wave -noupdate -group {rx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/rx_fifo_i2c/reg_int
add wave -noupdate -group {tx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/reg_i
add wave -noupdate -group {tx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/clk
add wave -noupdate -group {tx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/load
add wave -noupdate -group {tx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/flush
add wave -noupdate -group {tx fifo} /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/oen_i
add wave -noupdate -group {tx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/reg_o
add wave -noupdate -group {tx fifo} -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/tx_fifo_i2c/reg_int
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/rd_done_o
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/wr_done_o
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_rcved_o
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_tx_fifo_reg_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {471826715 ps} 0}
configure wave -namecolwidth 193
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {455785207 ps} {503379726 ps}
hdl/i2c_slave_wb_master/project/project.gise 0 → 100644
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hdl/i2c_slave_wb_master/project/waveform/i2c_slave_top_wv.wcfg 100755 → 100644
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File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd 100755 → 100644
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File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/rtl/i2c_debounce.vhd 100755 → 100644
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File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd 100755 → 100644
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File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd 100755 → 100644
View file @ 62b1c43a
...@@ -557,7 +557,8 @@ begin ...@@ -557,7 +557,8 @@ begin
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if s_watchdog_cnt >= c_WATCHDOG_END_VALUE then if rst_i = '1'
or s_watchdog_cnt >= c_WATCHDOG_END_VALUE then
i2c_SLA_fsm <= R0_RESET; i2c_SLA_fsm <= R0_RESET;
else else
case i2c_SLA_fsm is case i2c_SLA_fsm is
...@@ -673,6 +674,7 @@ begin ...@@ -673,6 +674,7 @@ begin
if s_bit_cnt = 7 then if s_bit_cnt = 7 then
i2c_SLA_fsm <= S5W2A_WRITE_SDA_ACK; i2c_SLA_fsm <= S5W2A_WRITE_SDA_ACK;
end if; end if;
--! It can be removed, never reached
check_start_stop; check_start_stop;
end if; end if;
when S5W2A_WRITE_SDA_ACK => when S5W2A_WRITE_SDA_ACK =>
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd 100755 → 100644
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File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/test/i2c_bit_tb.vhd 100755 → 100644
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File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd 100755 → 100644
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File mode changed from 100755 to 100644
hdl/i2c_slave_wb_master/test/log/i2c_master_driver.txt 0 → 100644
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1 OK WRITE [ADDRESS|0]
1 OK WRITE WISHBONE HIGH
1 OK WRITE WISHBONE LOW
1 OK WRITE READ DATA 0
1 OK WRITE READ DATA 1
1 OK WRITE READ DATA 2
1 OK WRITE READ DATA 3
2 OK READ [ADDRESS|0]
2 OK READ WISHBONE HIGH
2 OK READ WISHBONE LOW
2 OK READ [ADDRESS|0]
hdl/multiboot/project/multiboot.xise
View file @ 62b1c43a
...@@ -16,33 +16,41 @@ ...@@ -16,33 +16,41 @@
<files> <files>
<file xil_pn:name="../rtl/multiboot_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/multiboot_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="../rtl/multiboot_top.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/multiboot_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="../rtl/multiboot_regs.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="../test/multiboot_top_tb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../test/multiboot_top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="../test/multiboot_core_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../rtl/multiboot_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/multiboot_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="../test/multiboot_pkg_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ctdah_lib/test/wishbone_driver_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../ctdah_lib/test/wishbone_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
</files> </files>
<properties> <properties>
...@@ -80,7 +88,7 @@ ...@@ -80,7 +88,7 @@
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
...@@ -301,8 +309,8 @@ ...@@ -301,8 +309,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/multiboot_core_tb" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/multiboot_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.multiboot_core_tb" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.multiboot_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
...@@ -325,7 +333,7 @@ ...@@ -325,7 +333,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.multiboot_core_tb" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.multiboot_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
...@@ -387,7 +395,7 @@ ...@@ -387,7 +395,7 @@
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|multiboot_core_tb|behavior" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|multiboot_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="multiboot" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="multiboot" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
......
hdl/multiboot/project/wave.do deleted 100644 → 0
View file @ a8566fda
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -radix hexadecimal /multiboot_core_tb/rst
add wave -noupdate -radix hexadecimal /multiboot_core_tb/clk
add wave -noupdate -radix hexadecimal /multiboot_core_tb/CTRL0_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/CTRL1_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/STAT_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL1_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL2_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL3_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL4_i
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL1_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL2_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL3_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/GENERAL4_ICAP_o
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/multiboot_fsm
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/readback_fsm
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_busy_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_o_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_ce_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_i_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/icap_write_s
add wave -noupdate -radix hexadecimal /multiboot_core_tb/uut/op_cycles
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1750000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {1057409 ps} {1887747 ps}
hdl/multiboot/project/waveform/wave.do 0 → 100644
View file @ 62b1c43a
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group {wb driver} -radix hexadecimal /multiboot_tb/wb_driver/addr_i
add wave -noupdate -expand -group {wb driver} -radix hexadecimal /multiboot_tb/wb_driver/data_i
add wave -noupdate -expand -group {wb driver} -radix hexadecimal /multiboot_tb/wb_driver/data_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/read_i
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/read_done_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/write_i
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/write_done_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_sel_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_stb_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_cyc_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_we_o
add wave -noupdate -expand -group {wb driver} -radix hexadecimal /multiboot_tb/wb_driver/wb_addr_o
add wave -noupdate -expand -group {wb driver} -radix hexadecimal /multiboot_tb/wb_driver/wb_data_i
add wave -noupdate -expand -group {wb driver} -radix hexadecimal /multiboot_tb/wb_driver/wb_data_o
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_ack_i
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_err_i
add wave -noupdate -expand -group {wb driver} /multiboot_tb/wb_driver/wb_rty_i
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_rst_i
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_clk
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_we_i
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_stb_i
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_cyc_i
add wave -noupdate -expand -group {multiboot top} -radix hexadecimal /multiboot_tb/uut/wb_sel_i
add wave -noupdate -expand -group {multiboot top} -radix hexadecimal /multiboot_tb/uut/wb_data_i
add wave -noupdate -expand -group {multiboot top} -radix hexadecimal /multiboot_tb/uut/wb_data_o
add wave -noupdate -expand -group {multiboot top} -radix hexadecimal /multiboot_tb/uut/wb_addr_i
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_ack_o
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_rty_o
add wave -noupdate -expand -group {multiboot top} /multiboot_tb/uut/wb_err_o
add wave -noupdate -divider Registers
add wave -noupdate /multiboot_tb/wb_driver/wb_clk_i
add wave -noupdate /multiboot_tb/wb_driver/wb_rst_i
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_CTR0
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_CTR1
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_STAT
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_MBA
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_GBA
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_MBA_addr
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/s_GBA_addr
add wave -noupdate -radix hexadecimal -subitemconfig {/multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(15) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(14) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(13) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(12) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(11) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(10) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(9) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(8) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(7) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(6) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(5) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(4) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(3) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(2) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(1) {-radix hexadecimal} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA(0) {-radix hexadecimal}} /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regA
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/multiboot_core_inst/s_rd_ICAP_regB
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/multiboot_core_inst/s_wr_ICAP_gen1
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/multiboot_core_inst/s_wr_ICAP_gen2
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/multiboot_core_inst/s_wr_ICAP_gen3
add wave -noupdate -radix hexadecimal /multiboot_tb/uut/multiboot_core_inst/s_wr_ICAP_gen4
add wave -noupdate -divider multiboot_core
add wave -noupdate /multiboot_tb/uut/multiboot_core_inst/s_ICAP_fsm
add wave -noupdate /multiboot_tb/uut/multiboot_core_inst/s_multiboot_fsm
add wave -noupdate /multiboot_tb/uut/multiboot_core_inst/s_readback_fsm
add wave -noupdate /multiboot_tb/uut/multiboot_core_inst/s_CTR0_core
add wave -noupdate /multiboot_tb/uut/multiboot_core_inst/MBA_ICAP_o
add wave -noupdate /multiboot_tb/uut/multiboot_core_inst/GBA_ICAP_o
add wave -noupdate -divider SignalSpy
add wave -noupdate -expand -group ICAP /multiboot_tb/uut/multiboot_core_inst/ICAP_SPARTAN6_inst/CE
add wave -noupdate -expand -group ICAP /multiboot_tb/uut/multiboot_core_inst/ICAP_SPARTAN6_inst/CLK
add wave -noupdate -expand -group ICAP -radix hexadecimal /multiboot_tb/uut/multiboot_core_inst/ICAP_SPARTAN6_inst/I
add wave -noupdate -expand -group ICAP /multiboot_tb/uut/multiboot_core_inst/ICAP_SPARTAN6_inst/WRITE
add wave -noupdate -expand -group ICAP /multiboot_tb/uut/multiboot_core_inst/ICAP_SPARTAN6_inst/BUSY
add wave -noupdate -expand -group ICAP /multiboot_tb/uut/multiboot_core_inst/ICAP_SPARTAN6_inst/O
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1751210191 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {1750252160 ps} {1751578414 ps}
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