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Conv TTL Blocking
Commit a6b105fd authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Switching branches to compare trigger cores. Compiled image1 project, repetition not working.

parent b9e138fd
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hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ a6b105fd
...@@ -8,14 +8,16 @@ ...@@ -8,14 +8,16 @@
NET "RST_N" LOC = N20; NET "RST_N" LOC = N20;
NET "RST_N" IOSTANDARD = "LVTTL";
#NET "FPGA_SYSRESET_N" LOC = L20; #NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22; NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = "LVTTL";
NET "CLK20_VCXO" LOC = E16; NET "CLK20_VCXO" LOC = E16;
TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%; TIMESPEC TS_clk_i = PERIOD "CLK20_VCXO" 20 MHz HIGH 50%;
NET "FPGA_CLK_N" LOC = H11; NET "FPGA_CLK_P" LOC = H12;
NET "FPGA_CLK_P" LOC = G11; NET "FPGA_CLK_N" LOC = G11;
##====================================== ##======================================
...@@ -26,15 +28,34 @@ NET "FPGA_CLK_P" LOC = G11; ...@@ -26,15 +28,34 @@ NET "FPGA_CLK_P" LOC = G11;
##-- + UBT: LVTTL input ##-- + UBT: LVTTL input
##------------------- ##-------------------
NET "LED_CTRL0" LOC = M18; NET "LED_CTRL0" LOC = M18;
NET "LED_CTRL0" IOSTANDARD = "LVTTL";
NET "LED_CTRL0_OEN" LOC = T20; NET "LED_CTRL0_OEN" LOC = T20;
NET "LED_CTRL0_OEN" IOSTANDARD = "LVTTL";
NET "LED_CTRL1" LOC = M17; NET "LED_CTRL1" LOC = M17;
NET "LED_CTRL1" IOSTANDARD = "LVTTL";
NET "LED_CTRL1_OEN" LOC = U19; NET "LED_CTRL1_OEN" LOC = U19;
NET "LED_CTRL1_OEN" IOSTANDARD = "LVTTL";
NET "LED_MULTICAST_2_0" LOC = P16; NET "LED_MULTICAST_2_0" LOC = P16;
NET "LED_MULTICAST_2_0" IOSTANDARD = "LVTTL";
NET "LED_MULTICAST_3_1" LOC = P17; NET "LED_MULTICAST_3_1" LOC = P17;
NET "LED_MULTICAST_3_1" IOSTANDARD = "LVTTL";
NET "LED_WR_GMT_TTL_TTLN" LOC = N16; NET "LED_WR_GMT_TTL_TTLN" LOC = N16;
NET "LED_WR_GMT_TTL_TTLN" IOSTANDARD = "LVTTL";
NET "LED_WR_LINK_SYSERROR" LOC = R15; NET "LED_WR_LINK_SYSERROR" LOC = R15;
NET "LED_WR_LINK_SYSERROR" IOSTANDARD = "LVTTL";
NET "LED_WR_OK_SYSPW" LOC = R16; NET "LED_WR_OK_SYSPW" LOC = R16;
NET "LED_WR_OK_SYSPW" IOSTANDARD = "LVTTL";
NET "LED_WR_OWNADDR_I2C" LOC = N15; NET "LED_WR_OWNADDR_I2C" LOC = N15;
NET "LED_WR_OWNADDR_I2C" IOSTANDARD = "LVTTL";
##------------------- ##-------------------
##-- Front channel LEDs ##-- Front channel LEDs
##-- ##--
......
hdl/IMAGES/image1/project/image1.gise
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hdl/IMAGES/image1/project/image1.xise
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hdl/IMAGES/image1/top/image1_top.vhd
View file @ a6b105fd
...@@ -155,33 +155,33 @@ begin ...@@ -155,33 +155,33 @@ begin
port map (O => s_clk_125MHz, I => FPGA_CLK_P, port map (O => s_clk_125MHz, I => FPGA_CLK_P,
IB => FPGA_CLK_N); IB => FPGA_CLK_N);
LED_CTRL0 <= s_led_array.CTRL0; LED_CTRL0 <= s_led_array.CTRL0;
LED_CTRL0_OEN <= s_led_array.CTRL0_OEN; LED_CTRL0_OEN <= s_led_array.CTRL0_OEN;
LED_CTRL1 <= s_led_array.CTRL1; LED_CTRL1 <= s_led_array.CTRL1;
LED_CTRL1_OEN <= s_led_array.CTRL1_OEN; LED_CTRL1_OEN <= s_led_array.CTRL1_OEN;
LED_MULTICAST_2_0 <= s_led_array.MULTICAST_2_0; LED_MULTICAST_2_0 <= s_led_array.MULTICAST_2_0;
LED_MULTICAST_3_1 <= s_led_array.MULTICAST_3_1; LED_MULTICAST_3_1 <= s_led_array.MULTICAST_3_1;
LED_WR_GMT_TTL_TTLN <= s_led_array.WR_GMT_TTL_TTLN; LED_WR_GMT_TTL_TTLN <= s_led_array.WR_GMT_TTL_TTLN;
LED_WR_LINK_SYSERROR <= s_led_array.WR_LINK_SYSERROR; LED_WR_LINK_SYSERROR <= s_led_array.WR_LINK_SYSERROR;
LED_WR_OK_SYSPW <= s_led_array.WR_OK_SYSPW; LED_WR_OK_SYSPW <= s_led_array.WR_OK_SYSPW;
LED_WR_OWNADDR_I2C <= s_led_array.WR_OWNADDR_I2C; LED_WR_OWNADDR_I2C <= s_led_array.WR_OWNADDR_I2C;
s_i2c_slave_i.SCL_I <= SCL_I; s_i2c_slave_i.SCL_I <= SCL_I;
s_i2c_slave_i.SDA_I <= SDA_I; s_i2c_slave_i.SDA_I <= SDA_I;
SCL_O <= s_i2c_slave_o.SCL_O; SCL_O <= s_i2c_slave_o.SCL_O;
SCL_OE <= s_i2c_slave_o.SCL_OE; SCL_OE <= s_i2c_slave_o.SCL_OE;
SDA_O <= s_i2c_slave_o.SDA_O; SDA_O <= s_i2c_slave_o.SDA_O;
SDA_OE <= s_i2c_slave_o.SDA_OE; SDA_OE <= s_i2c_slave_o.SDA_OE;
s_spi_master_i.DIN <= FPGA_PROM_DIN; s_spi_master_i.DIN <= FPGA_PROM_DIN;
FPGA_PROM_CCLK <= s_spi_master_o.CCLK; FPGA_PROM_CCLK <= s_spi_master_o.CCLK;
FPGA_PROM_CSO_B_N <= s_spi_master_o.CSO_B_N; FPGA_PROM_CSO_B_N <= s_spi_master_o.CSO_B_N;
FPGA_PROM_MOSI <= s_spi_master_o.MOSI; FPGA_PROM_MOSI <= s_spi_master_o.MOSI;
s_rtm_i.RTMM_N <= FPGA_RTMM_N; s_rtm_i.RTMM_N <= FPGA_RTMM_N;
s_rtm_i.RTMP_N <= fpga_rtmp_n; s_rtm_i.RTMP_N <= fpga_rtmp_n;
s_switch_i <= EXTRA_SWITCH; s_switch_i <= EXTRA_SWITCH;
inst_image1_core: image1_core inst_image1_core: image1_core
generic map(g_NUMBER_OF_CHANNELS => 6) generic map(g_NUMBER_OF_CHANNELS => 6)
......
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