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Commit a9e62b25 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Committed last modification on IP cores for remote programming before merging:… 

Committed last modification on IP cores for remote programming before merging: ctdah_lib, i2c_slave_wb_master, m25p32, multiboot, spi_master_multifield
parent 078498ba
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hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd
View file @ a9e62b25
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT -- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano -- Engineer: Carlos Gil Soriano
-- --
-- Create Date: 00:47:34 10/26/2011 -- Create Date: 00:47:34 10/26/2011
-- Design Name: i2c bit recognition fsm -- Design Name: i2c bit recognition fsm
-- Module Name: i2c_bit - Behavioral -- Module Name: i2c_bit - Behavioral
-- Project Name: Level Conversion Circuits -- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6 -- Target Devices: Spartan 6
-- Tool versions: -- Tool versions:
-- Description: This is the fsm for the recognition of a bit. It offers some -- Description: This is the fsm for the recognition of a bit. It offers some
-- interrupting lines to the upper level (i2c_slave_core.vhd) -- interrupting lines to the upper level (i2c_slave_core.vhd)
-- which is responsible for managing byte level transactions -- which is responsible for managing byte level transactions
-- --
-- Dependencies: The inputs should be debounced: i2c_debouncer.vhd -- Dependencies: The inputs should be debounced: i2c_debouncer.vhd
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- 0.1 - Module works with no reported issues. -- 0.1 - Module works with no reported issues.
-- 1.0 - Code revamped. Now is clearer and easier to read. -- 1.0 - Code revamped. Now is clearer and easier to read.
-- Additional Comments: -- Additional Comments:
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
library IEEE; library IEEE;
...@@ -57,7 +57,7 @@ architecture Behavioral of i2c_bit is ...@@ -57,7 +57,7 @@ architecture Behavioral of i2c_bit is
--! It specifies the maximum number of stages that will be employed for --! It specifies the maximum number of stages that will be employed for
--! deglitching. Clocked with wb_clk_i --! deglitching. Clocked with wb_clk_i
constant c_MAX_GLITCH_DELAY : NATURAL := 6; constant c_MAX_GLITCH_DELAY : NATURAL := 6;
--! Three delay stages out of six --! Three delay stages out of six
constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111"; constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111";
...@@ -126,8 +126,8 @@ begin ...@@ -126,8 +126,8 @@ begin
s_scl_rising <= '1'; s_scl_rising <= '1';
end if; end if;
else else
s_scl_rising <= '0'; s_scl_rising <= '0';
s_scl_falling <= '0'; s_scl_falling <= '0';
end if; end if;
else else
end if; end if;
......
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ a9e62b25
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT -- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano -- Engineer: Carlos Gil Soriano
-- --
-- Create Date: 11:56:55 10/25/2011 -- Create Date: 11:56:55 10/25/2011
-- Design Name: I2C slave register HDL -- Design Name: I2C slave register HDL
-- Module Name: i2c_regs - Behavioral -- Module Name: i2c_regs - Behavioral
-- Project Name: Level Conversion Circuits -- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6 -- Target Devices: Spartan 6
-- Tool versions: -- Tool versions:
-- Description: This is the HDL that holds all the register of the I2C slave -- Description: This is the HDL that holds all the register of the I2C slave
-- core -- core
-- --
...@@ -15,10 +15,10 @@ ...@@ -15,10 +15,10 @@
-- 1.- CTR0 Sets up the control register: enable, start, i2c address -- 1.- CTR0 Sets up the control register: enable, start, i2c address
-- 2.- CTR1 Sets up the threshold for detection signals in RX and TX buffers -- 2.- CTR1 Sets up the threshold for detection signals in RX and TX buffers
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- 1.0 - Stable version -- 1.0 - Stable version
-- Additional Comments: -- Additional Comments:
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
library IEEE; library IEEE;
...@@ -129,7 +129,7 @@ begin ...@@ -129,7 +129,7 @@ begin
if rising_edge(wb_clk) then if rising_edge(wb_clk) then
if i2c_master_WB_BASIC_fsm = S3_WB_ACK then if i2c_master_WB_BASIC_fsm = S3_WB_ACK then
s_wb_master_ack_retries(0) <= '1'; s_wb_master_ack_retries(0) <= '1';
for i in 1 to c_RETRY_LENGTH - 1 loop for i in 1 to c_RETRY_LENGTH - 1 loop
s_wb_master_ack_retries(i) <= s_wb_master_ack_retries(i-1); s_wb_master_ack_retries(i) <= s_wb_master_ack_retries(i-1);
end loop; end loop;
else else
...@@ -147,11 +147,11 @@ begin ...@@ -147,11 +147,11 @@ begin
--! @param i2c_master_WB_BASIC_fsm fsm of the wishone master interface --! @param i2c_master_WB_BASIC_fsm fsm of the wishone master interface
wbmaster_comb_proc: process(i2c_master_WB_BASIC_fsm) wbmaster_comb_proc: process(i2c_master_WB_BASIC_fsm)
begin begin
s_wb_master_we_o <= '0'; s_wb_master_we_o <= '0';
wb_master_stb_o <= '0'; wb_master_stb_o <= '0';
wb_master_cyc_o <= '0'; wb_master_cyc_o <= '0';
wb_master_sel_o <= (others => '0'); wb_master_sel_o <= (others => '0');
wb_master_data_o <= (others => '0'); wb_master_data_o <= (others => '0');
wb_master_addr_o <= (others => '0'); wb_master_addr_o <= (others => '0');
-- s_DRXA <= (others => '0'); -- s_DRXA <= (others => '0');
-- s_DRXB <= (others => '0'); -- s_DRXB <= (others => '0');
...@@ -224,7 +224,7 @@ begin ...@@ -224,7 +224,7 @@ begin
and s_wb_slave_ack = '0' and s_wb_slave_ack = '0'
and s_wb_slave_rty = '0' and s_wb_slave_rty = '0'
and s_wb_slave_err = '0' then and s_wb_slave_err = '0' then
case wb_slave_we_i is case wb_slave_we_i is
when '1' => when '1' =>
s_wb_slave_ack <= '1'; s_wb_slave_ack <= '1';
case s_wb_slave_addr is case s_wb_slave_addr is
...@@ -278,7 +278,7 @@ begin ...@@ -278,7 +278,7 @@ begin
when S0_IDLE => when S0_IDLE =>
if pf_wb_addr_i = '1' then if pf_wb_addr_i = '1' then
i2c_master_WB_BASIC_fsm <= S1P_WB_RD_RQT; i2c_master_WB_BASIC_fsm <= S1P_WB_RD_RQT;
elsif rd_done_i = '1' then elsif rd_done_i = '1' then
i2c_master_WB_BASIC_fsm <= S2P_WB_WR_RQT; i2c_master_WB_BASIC_fsm <= S2P_WB_WR_RQT;
end if; end if;
when S1P_WB_RD_RQT => when S1P_WB_RD_RQT =>
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
View file @ a9e62b25
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT -- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano -- Engineer: Carlos Gil Soriano
-- --
-- Create Date: 11:29:56 10/25/2011 -- Create Date: 11:29:56 10/25/2011
-- Design Name: I2C Slave to Wishbone bridge -- Design Name: I2C Slave to Wishbone bridge
-- Module Name: i2c_slave_core - Behavioral -- Module Name: i2c_slave_core - Behavioral
-- Project Name: Level Conversion Circuits -- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6 -- Target Devices: Spartan 6
-- Tool versions: -- Tool versions:
-- Description: This is a bridge from I2C to Wishbone. -- Description: This is a bridge from I2C to Wishbone.
-- The module consist on the following interfaces: -- The module consist on the following interfaces:
-- - I2C interface -- - I2C interface
...@@ -37,17 +37,17 @@ ...@@ -37,17 +37,17 @@
-- Both the Wishbone master and slave interface access control -- Both the Wishbone master and slave interface access control
-- and all configuration registers can be found in: -- and all configuration registers can be found in:
-- --> ./i2c_regs.vhd -- --> ./i2c_regs.vhd
-- --
-- Dependencies: i2c_bit.vhd, FIFO_stack.vhd, FIFO_dispatcher.vhd, gc_ff.vhd -- Dependencies: i2c_bit.vhd, FIFO_stack.vhd, FIFO_dispatcher.vhd, gc_ff.vhd
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- 0.1 - Initial submission. I2C instructions for Read and Write work. -- 0.1 - Initial submission. I2C instructions for Read and Write work.
-- 1.0 - Code completely revamped. Code tested with a code coverage of -- 1.0 - Code completely revamped. Code tested with a code coverage of
-- 81.5% with the testbench provided in: -- 81.5% with the testbench provided in:
-- ../test/i2c_slave_test_top_tb.vhd -- ../test/i2c_slave_test_top_tb.vhd
-- --
-- Additional Comments: -- Additional Comments:
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
library IEEE; library IEEE;
...@@ -142,7 +142,7 @@ signal s_i2c_addr_ctr0 : STD_LOGIC_VECTOR(7 downto 0); ...@@ -142,7 +142,7 @@ signal s_i2c_addr_ctr0 : STD_LOGIC_VECTOR(7 downto 0);
signal s_i2c_addr : STD_LOGIC_VECTOR(7 downto 0); signal s_i2c_addr : STD_LOGIC_VECTOR(7 downto 0);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- i2c signals -- i2c signals
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
signal s_sda_o : STD_LOGIC; signal s_sda_o : STD_LOGIC;
signal s_sda_oen : STD_LOGIC; signal s_sda_oen : STD_LOGIC;
...@@ -164,7 +164,7 @@ signal s_byte_cnt_en : STD_LOGIC := '0'; ...@@ -164,7 +164,7 @@ signal s_byte_cnt_en : STD_LOGIC := '0';
signal s_tx_fifo_load_TX : STD_LOGIC; signal s_tx_fifo_load_TX : STD_LOGIC;
signal s_tx_fifo_flush : STD_LOGIC; signal s_tx_fifo_flush : STD_LOGIC;
signal s_tx_fifo_oen : STD_LOGIC; signal s_tx_fifo_oen : STD_LOGIC;
signal s_tx_fifo_reg_o : STD_LOGIC_VECTOR (c_DATA_WIDTH -1 downto 0); signal s_tx_fifo_reg_o : STD_LOGIC_VECTOR (c_DATA_WIDTH -1 downto 0);
-- Interrupting signals (i2c_bit.vhd) -- Interrupting signals (i2c_bit.vhd)
signal s_start_o : STD_LOGIC; signal s_start_o : STD_LOGIC;
...@@ -281,9 +281,9 @@ begin ...@@ -281,9 +281,9 @@ begin
procedure shift_DRX is procedure shift_DRX is
begin begin
s_DRX_slv(s_DRX_slv'length - 1) <= s_rcved_o; s_DRX_slv(s_DRX_slv'length - 1) <= s_rcved_o;
for i in 1 to s_DRX_slv'length - 1 loop for i in 1 to s_DRX_slv'length - 1 loop
s_DRX_slv(i-1) <= s_DRX_slv(i); s_DRX_slv(i-1) <= s_DRX_slv(i);
end loop; end loop;
end procedure; end procedure;
...@@ -315,7 +315,7 @@ begin ...@@ -315,7 +315,7 @@ begin
s_i2c_addr_ctr0(7 downto 1) <= STD_LOGIC_VECTOR(s_CTR0.I2C_ADDR); s_i2c_addr_ctr0(7 downto 1) <= STD_LOGIC_VECTOR(s_CTR0.I2C_ADDR);
s_i2c_addr(0) <= '0'; s_i2c_addr(0) <= '0';
gen_i2c: for i in 1 to 7 generate gen_i2c: for i in 1 to 7 generate
s_i2c_addr(8-i) <= s_i2c_addr_ctr0(i); s_i2c_addr(8-i) <= s_i2c_addr_ctr0(i);
end generate gen_i2c; end generate gen_i2c;
...@@ -360,7 +360,7 @@ begin ...@@ -360,7 +360,7 @@ begin
begin begin
if rising_edge(clk) then if rising_edge(clk) then
wr_done_o <= '0'; wr_done_o <= '0';
if i2c_SLA_fsm = S6_WAIT_START_PAUSE if i2c_SLA_fsm = S6_WAIT_START_PAUSE
and i2c_SLA_fsm_d0 = S5W3_NACK then and i2c_SLA_fsm_d0 = S5W3_NACK then
wr_done_o <= '1'; wr_done_o <= '1';
end if; end if;
...@@ -474,7 +474,7 @@ begin ...@@ -474,7 +474,7 @@ begin
end if; end if;
when S7_PAUSE_DETECT => when S7_PAUSE_DETECT =>
null; null;
when others => when others =>
s_bit_cnt_rst <= '1'; s_bit_cnt_rst <= '1';
s_byte_cnt_rst <= '1'; s_byte_cnt_rst <= '1';
end case; end case;
...@@ -614,7 +614,7 @@ begin ...@@ -614,7 +614,7 @@ begin
check_start_stop; check_start_stop;
end if; end if;
end if; end if;
when S4_DETECT_OPERATION => when S4_DETECT_OPERATION =>
if s_bit_done = '1' then if s_bit_done = '1' then
if s_start_o = '1' then if s_start_o = '1' then
i2c_SLA_fsm <= S5W0_RESTART; i2c_SLA_fsm <= S5W0_RESTART;
...@@ -668,7 +668,7 @@ begin ...@@ -668,7 +668,7 @@ begin
i2c_SLA_fsm <= S6_WAIT_START_PAUSE; i2c_SLA_fsm <= S6_WAIT_START_PAUSE;
check_start_stop; check_start_stop;
end if; end if;
when S5W2_WRITE_SDA => when S5W2_WRITE_SDA =>
if s_bit_done = '1' then if s_bit_done = '1' then
if s_bit_cnt = 7 then if s_bit_cnt = 7 then
i2c_SLA_fsm <= S5W2A_WRITE_SDA_ACK; i2c_SLA_fsm <= S5W2A_WRITE_SDA_ACK;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
View file @ a9e62b25
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- --
-- Company: CERN, BE-CO-HT -- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano -- Engineer: Carlos Gil Soriano
-- --
-- Create Date: 11:03:11 06/19/2012 -- Create Date: 11:03:11 06/19/2012
-- Design Name: -- Design Name:
-- Module Name: i2c_slave_pkg - Behavioral -- Module Name: i2c_slave_pkg - Behavioral
-- Project Name: CTDAH/SVEC -- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6 -- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4 -- Tool versions: Xilinx ISE 13.4
-- Description: Package for the i2c_slave -- Description: Package for the i2c_slave
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: 0.1 -- Revision: 0.1
-- 0.01 + File Created -- 0.01 + File Created
-- Additional Comments: -- Additional Comments:
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
...@@ -38,10 +38,10 @@ package i2c_slave_pkg is ...@@ -38,10 +38,10 @@ package i2c_slave_pkg is
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- This is the declaration area of the constants used in other components: -- This is the declaration area of the constants used in other components:
-- c_COUNTER_WIDTH bit length of the gc_counter -- c_COUNTER_WIDTH bit length of the gc_counter
-- c_DATA_WIDTH width of the data to be stored in FIFO_stack -- c_DATA_WIDTH width of the data to be stored in FIFO_stack
-- and FIFO_dispatchers. -- and FIFO_dispatchers.
-- c_RX_STACK_DEPTH depth of FIFO_stack -- c_RX_STACK_DEPTH depth of FIFO_stack
-- c_TX_STACK_DEPTH depth of FIFO_dispatch -- c_TX_STACK_DEPTH depth of FIFO_dispatch
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
constant c_COUNTER_WIDTH : NATURAL := 8; constant c_COUNTER_WIDTH : NATURAL := 8;
constant c_DATA_WIDTH : NATURAL := 8; constant c_DATA_WIDTH : NATURAL := 8;
...@@ -76,7 +76,7 @@ package i2c_slave_pkg is ...@@ -76,7 +76,7 @@ package i2c_slave_pkg is
type r_CTR0 is type r_CTR0 is
record record
I2C_OP : STD_LOGIC; I2C_OP : STD_LOGIC;
I2C_ADDR : UNSIGNED( 7 downto 1); I2C_ADDR : UNSIGNED( 7 downto 1);
BIA : UNSIGNED(11 downto 8); BIA : UNSIGNED(11 downto 8);
BRD : UNSIGNED(19 downto 12); BRD : UNSIGNED(19 downto 12);
BWR : UNSIGNED(27 downto 20); BWR : UNSIGNED(27 downto 20);
...@@ -89,7 +89,7 @@ package i2c_slave_pkg is ...@@ -89,7 +89,7 @@ package i2c_slave_pkg is
-- LT register -- LT register
------------------------------------- -------------------------------------
-- 32 bits -- 32 bits
-- Wishbone access: Read-only -- Wishbone access: Read-only
------------------------------------ ------------------------------------
-- BIT NAME Description -- BIT NAME Description
-- 7-0 WBCP WishBone Clock Period -- 7-0 WBCP WishBone Clock Period
...@@ -282,7 +282,7 @@ package body i2c_slave_pkg is ...@@ -282,7 +282,7 @@ package body i2c_slave_pkg is
variable v_return : STD_LOGIC_VECTOR(31 downto 0); variable v_return : STD_LOGIC_VECTOR(31 downto 0);
begin begin
v_return(7 downto 0) := STD_LOGIC_VECTOR(r_register.WBCP); v_return(7 downto 0) := STD_LOGIC_VECTOR(r_register.WBCP);
v_return(31 downto 8) := STD_LOGIC_VECTOR(r_register.SCLP); v_return(31 downto 8) := STD_LOGIC_VECTOR(r_register.SCLP);
return v_return; return v_return;
end function; end function;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
View file @ a9e62b25
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT CHANGED -- Company: CERN, BE-CO-HT CHANGED
-- Engineer: Carlos Gil Soriano -- Engineer: Carlos Gil Soriano
-- --
-- Create Date: 18:15:56 11/09/2011 -- Create Date: 18:15:56 11/09/2011
-- Design Name: A I2C slave with wishbone slave output and interrupt for MCU -- Design Name: A I2C slave with wishbone slave output and interrupt for MCU
-- Module Name: i2c_slave_top - Behavioral -- Module Name: i2c_slave_top - Behavioral
-- Project Name: CTDAH -- Project Name: CTDAH
-- Target Devices: -- Target Devices:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
library IEEE; library IEEE;
...@@ -120,21 +120,21 @@ begin ...@@ -120,21 +120,21 @@ begin
port map(pf_wb_addr_i => s_pf_wb_addr, port map(pf_wb_addr_i => s_pf_wb_addr,
pf_wb_data_o => s_pf_wb_data, pf_wb_data_o => s_pf_wb_data,
rd_done_i => s_rd_done, rd_done_i => s_rd_done,
wr_done_i => s_wr_done, wr_done_i => s_wr_done,
wb_rst_i => wb_rst_i, wb_rst_i => wb_rst_i,
wb_clk => wb_clk, wb_clk => wb_clk,
wb_master_we_o => wb_master_we_o, wb_master_we_o => wb_master_we_o,
wb_master_stb_o => wb_master_stb_o, wb_master_stb_o => wb_master_stb_o,
wb_master_cyc_o => wb_master_cyc_o, wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o, wb_master_sel_o => wb_master_sel_o,
wb_master_data_i => wb_master_data_i, wb_master_data_i => wb_master_data_i,
wb_master_data_o => wb_master_data_o, wb_master_data_o => wb_master_data_o,
wb_master_addr_o => wb_master_addr_o, wb_master_addr_o => wb_master_addr_o,
wb_master_ack_i => wb_master_ack_i, wb_master_ack_i => wb_master_ack_i,
wb_master_rty_i => wb_master_rty_i, wb_master_rty_i => wb_master_rty_i,
wb_master_err_i => wb_master_err_i, wb_master_err_i => wb_master_err_i,
wb_slave_we_i => wb_slave_we_i, wb_slave_we_i => wb_slave_we_i,
wb_slave_stb_i => wb_slave_stb_i, wb_slave_stb_i => wb_slave_stb_i,
......
hdl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
View file @ a9e62b25
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT -- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano -- Engineer: Carlos Gil Soriano
-- --
-- Create Date: 12:07:51 10/26/2011 -- Create Date: 12:07:51 10/26/2011
...@@ -7,22 +7,22 @@ ...@@ -7,22 +7,22 @@
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_bit_tb.vhd -- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
-- Project Name: CTDAH -- Project Name: CTDAH
-- Target Device: Spartan 6 -- Target Device: Spartan 6
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- VHDL Test Bench Created by ISE for module: i2c_bit -- VHDL Test Bench Created by ISE for module: i2c_bit
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-- Notes: -- Notes:
-- This testbench has been automatically generated using types std_logic and -- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends -- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order -- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation -- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model. -- simulation model.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
LIBRARY ieee; LIBRARY ieee;
...@@ -30,18 +30,18 @@ library work; ...@@ -30,18 +30,18 @@ library work;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_1164.ALL;
USE work.i2c_slave_pkg.ALL; USE work.i2c_slave_pkg.ALL;
-- Uncomment the following library declaration if using -- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values -- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL; --USE ieee.numeric_std.ALL;
ENTITY i2c_bit_tb IS ENTITY i2c_bit_tb IS
END i2c_bit_tb; END i2c_bit_tb;
ARCHITECTURE behavior OF i2c_bit_tb IS ARCHITECTURE behavior OF i2c_bit_tb IS
-- Component Declaration for the Unit Under Test (UUT) -- Component Declaration for the Unit Under Test (UUT)
component i2c_bit component i2c_bit
port( port(
rst_i : IN std_logic; rst_i : IN std_logic;
...@@ -56,7 +56,7 @@ ARCHITECTURE behavior OF i2c_bit_tb IS ...@@ -56,7 +56,7 @@ ARCHITECTURE behavior OF i2c_bit_tb IS
rcved_o : OUT std_logic rcved_o : OUT std_logic
); );
end component; end component;
--Inputs --Inputs
signal rst_i : std_logic := '0'; signal rst_i : std_logic := '0';
signal wb_clk_i : std_logic := '0'; signal wb_clk_i : std_logic := '0';
...@@ -70,12 +70,12 @@ ARCHITECTURE behavior OF i2c_bit_tb IS ...@@ -70,12 +70,12 @@ ARCHITECTURE behavior OF i2c_bit_tb IS
signal rcved_o : std_logic; signal rcved_o : std_logic;
signal done_o : std_logic; signal done_o : std_logic;
-- No clocks detected in port list. Replace <clock> below with -- No clocks detected in port list. Replace <clock> below with
-- appropriate port name -- appropriate port name
constant wb_clk_i_period : time := 50 ns; -- @ 20 MHz constant wb_clk_i_period : time := 50 ns; -- @ 20 MHz
constant scl_i_period : time := 2500 ns; -- @ 400 KHz constant scl_i_period : time := 2500 ns; -- @ 400 KHz
BEGIN BEGIN
-- Instantiate the Unit Under Test (UUT) -- Instantiate the Unit Under Test (UUT)
uut: i2c_bit uut: i2c_bit
PORT MAP (rst_i => rst_i, PORT MAP (rst_i => rst_i,
...@@ -104,7 +104,7 @@ BEGIN ...@@ -104,7 +104,7 @@ BEGIN
scl_i <= '0'; scl_i <= '0';
wait for scl_i_period/2; wait for scl_i_period/2;
end process; end process;
-- Stimulus process -- Stimulus process
stim_proc: process stim_proc: process
procedure init_cond is procedure init_cond is
...@@ -140,7 +140,7 @@ BEGIN ...@@ -140,7 +140,7 @@ BEGIN
end loop; end loop;
end addr_send; end addr_send;
procedure pause is procedure pause is
begin begin
sda_i <= '0'; sda_i <= '0';
wait until rising_edge(scl_i); wait until rising_edge(scl_i);
...@@ -150,7 +150,7 @@ BEGIN ...@@ -150,7 +150,7 @@ BEGIN
wait for scl_i_period/4; wait for scl_i_period/4;
end pause; end pause;
begin begin
init_cond; init_cond;
rst; rst;
......
hdl/i2c_slave_wb_master/test/i2c_master_driver.vhd
View file @ a9e62b25
...@@ -16,11 +16,11 @@ entity i2c_master_driver is ...@@ -16,11 +16,11 @@ entity i2c_master_driver is
g_WB_ADDR_LENGTH : NATURAL := 16; g_WB_ADDR_LENGTH : NATURAL := 16;
g_SCL_PERIOD : TIME := 250 us); g_SCL_PERIOD : TIME := 250 us);
port(tb_clk : in STD_LOGIC; port(tb_clk : in STD_LOGIC;
sda_master_i : in STD_LOGIC; sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC; sda_master_o : out STD_LOGIC;
scl_master_o : out STD_LOGIC; scl_master_o : out STD_LOGIC;
i2c_addr_op_i : in STD_LOGIC_VECTOR(7 downto 0); i2c_addr_op_i : in STD_LOGIC_VECTOR(7 downto 0);
wishbone_addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0); wishbone_addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0);
wr_data_i : in STD_LOGIC_VECTOR(g_WR_DATA_LENGTH - 1 downto 0); wr_data_i : in STD_LOGIC_VECTOR(g_WR_DATA_LENGTH - 1 downto 0);
...@@ -36,7 +36,7 @@ entity i2c_master_driver is ...@@ -36,7 +36,7 @@ entity i2c_master_driver is
read_done_o : out STD_LOGIC); read_done_o : out STD_LOGIC);
end i2c_master_driver; end i2c_master_driver;
architecture Behavioral of i2c_master_driver is architecture Behavioral of i2c_master_driver is
type i2c_byte_field is (ADDRESS_0, type i2c_byte_field is (ADDRESS_0,
ADDRESS_1, ADDRESS_1,
...@@ -76,7 +76,7 @@ begin ...@@ -76,7 +76,7 @@ begin
start_done_o <= s_start_done; start_done_o <= s_start_done;
pause_done_o <= s_pause_done; pause_done_o <= s_pause_done;
write_done_o <= s_write_done; write_done_o <= s_write_done;
read_done_o <= s_read_done; read_done_o <= s_read_done;
scl_clk_process: process scl_clk_process: process
begin begin
...@@ -91,7 +91,7 @@ begin ...@@ -91,7 +91,7 @@ begin
--! @brief Function that returns strings for the acked field to be --! @brief Function that returns strings for the acked field to be
--! logged. --! logged.
--! @param byte_type i2c_byte_field type to be translated into a string --! @param byte_type i2c_byte_field type to be translated into a string
function get_field(byte_type : i2c_byte_field) return STRING is function get_field(byte_type : i2c_byte_field) return STRING is
variable v_return : STRING (16 downto 1) := (others => ' '); variable v_return : STRING (16 downto 1) := (others => ' ');
begin begin
...@@ -234,7 +234,7 @@ begin ...@@ -234,7 +234,7 @@ begin
variable v_bit_rcv : STD_LOGIC; variable v_bit_rcv : STD_LOGIC;
begin begin
wait until rising_edge(s_scl_clk); wait until rising_edge(s_scl_clk);
v_bit_rcv := sda_master_i; v_bit_rcv := sda_master_i;
for i in 0 to (g_SCL_PERIOD/2)/(1 ns) - 1 loop for i in 0 to (g_SCL_PERIOD/2)/(1 ns) - 1 loop
if v_bit_rcv /= sda_master_i then if v_bit_rcv /= sda_master_i then
--! Here we report an error --! Here we report an error
...@@ -292,10 +292,10 @@ begin ...@@ -292,10 +292,10 @@ begin
v_i2c_addr_op(0) := '0'; v_i2c_addr_op(0) := '0';
send_byte(order_i2c_addr_op(v_i2c_addr_op)); send_byte(order_i2c_addr_op(v_i2c_addr_op));
check_ack(s_test_id, "WRITE", ADDRESS_0); check_ack(s_test_id, "WRITE", ADDRESS_0);
--! 2.- Send wishbone address high --! 2.- Send wishbone address high
send_byte(wishbone_addr_i(15 downto 8)); send_byte(wishbone_addr_i(15 downto 8));
check_ack(s_test_id, "WRITE", WISHBONE_HIGH); check_ack(s_test_id, "WRITE", WISHBONE_HIGH);
--! 3.- Send wishbone address low --! 3.- Send wishbone address low
send_byte(wishbone_addr_i(7 downto 0)); send_byte(wishbone_addr_i(7 downto 0));
check_ack(s_test_id, "WRITE", WISHBONE_LOW); check_ack(s_test_id, "WRITE", WISHBONE_LOW);
--! 4.- Send DATA0 --! 4.- Send DATA0
...@@ -322,10 +322,10 @@ begin ...@@ -322,10 +322,10 @@ begin
v_i2c_addr_op(0) := '0'; v_i2c_addr_op(0) := '0';
send_byte(order_i2c_addr_op(v_i2c_addr_op)); send_byte(order_i2c_addr_op(v_i2c_addr_op));
check_ack(s_test_id, " READ", ADDRESS_0); check_ack(s_test_id, " READ", ADDRESS_0);
--! 2.- Send wishbone address high --! 2.- Send wishbone address high
send_byte(wishbone_addr_i(15 downto 8)); send_byte(wishbone_addr_i(15 downto 8));
check_ack(s_test_id, " READ", WISHBONE_HIGH); check_ack(s_test_id, " READ", WISHBONE_HIGH);
--! 3.- Send wishbone address low --! 3.- Send wishbone address low
send_byte(wishbone_addr_i(7 downto 0)); send_byte(wishbone_addr_i(7 downto 0));
check_ack(s_test_id, " READ", WISHBONE_LOW); check_ack(s_test_id, " READ", WISHBONE_LOW);
--! 4.- We have to place a start condition --! 4.- We have to place a start condition
......
hdl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd
View file @ a9e62b25
...@@ -3,27 +3,27 @@ ...@@ -3,27 +3,27 @@
-- Engineer: Carlos Gil Soriano -- Engineer: Carlos Gil Soriano
-- --
-- Create Date: 10:59:15 10/31/2011 -- Create Date: 10:59:15 10/31/2011
-- Design Name: -- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd -- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd
-- Project Name: i2c_slave_wb_master -- Project Name: i2c_slave_wb_master
-- Target Device: Spartan 6 -- Target Device: Spartan 6
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- VHDL Test Bench Created by ISE for module: i2c_slave_top -- VHDL Test Bench Created by ISE for module: i2c_slave_top
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Revision 0.1 - File Modified. Now the sda_i line is more acurately accessed. -- Revision 0.1 - File Modified. Now the sda_i line is more acurately accessed.
-- Additional Comments: -- Additional Comments:
-- --
-- Notes: -- Notes:
-- This testbench has been automatically generated using types std_logic and -- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends -- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order -- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation -- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model. -- simulation model.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
library IEEE; library IEEE;
...@@ -34,11 +34,11 @@ use IEEE.NUMERIC_STD.ALl; ...@@ -34,11 +34,11 @@ use IEEE.NUMERIC_STD.ALl;
use std.textio.ALL; use std.textio.ALL;
use work.i2c_tb_pkg.ALL; use work.i2c_tb_pkg.ALL;
use work.wishbone_driver_pkg.ALL; use work.wishbone_driver_pkg.ALL;
entity i2c_slave_top_tb is entity i2c_slave_top_tb is
end i2c_slave_top_tb; end i2c_slave_top_tb;
architecture behavior of i2c_slave_top_tb is architecture behavior of i2c_slave_top_tb is
--! Connections for i2c_slave_top --! Connections for i2c_slave_top
signal sda_slave_oen : STD_LOGIC; signal sda_slave_oen : STD_LOGIC;
...@@ -95,13 +95,13 @@ architecture behavior of i2c_slave_top_tb is ...@@ -95,13 +95,13 @@ architecture behavior of i2c_slave_top_tb is
signal s_wb_driver_data_i : STD_LOGIC_VECTOR(31 downto 0) signal s_wb_driver_data_i : STD_LOGIC_VECTOR(31 downto 0)
:= (others => '0'); := (others => '0');
signal s_wb_driver_data_o : STD_LOGIC_VECTOR(31 downto 0); signal s_wb_driver_data_o : STD_LOGIC_VECTOR(31 downto 0);
signal s_wb_driver_addr_i : STD_LOGIC_VECTOR(3 downto 0) signal s_wb_driver_addr_i : STD_LOGIC_VECTOR(3 downto 0)
:= (others => '0'); := (others => '0');
signal s_wb_driver_write_i : STD_LOGIC := '0'; signal s_wb_driver_write_i : STD_LOGIC := '0';
signal s_wb_driver_write_done_o : STD_LOGIC; signal s_wb_driver_write_done_o : STD_LOGIC;
signal s_wb_driver_read_i : STD_LOGIC := '0'; signal s_wb_driver_read_i : STD_LOGIC := '0';
signal s_wb_driver_read_done_o : STD_LOGIC; signal s_wb_driver_read_done_o : STD_LOGIC;
signal s_i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0) signal s_i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0)
...@@ -127,7 +127,7 @@ architecture behavior of i2c_slave_top_tb is ...@@ -127,7 +127,7 @@ architecture behavior of i2c_slave_top_tb is
type i2c_start_op is (S0_READ, type i2c_start_op is (S0_READ,
S1_WRITE); S1_WRITE);
begin begin
...@@ -147,16 +147,16 @@ begin ...@@ -147,16 +147,16 @@ begin
wb_clk => wb_clk, wb_clk => wb_clk,
wb_rst_i => wb_rst_i, wb_rst_i => wb_rst_i,
wb_master_stb_o => wb_master_stb_o, wb_master_stb_o => wb_master_stb_o,
wb_master_cyc_o => wb_master_cyc_o, wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o, wb_master_sel_o => wb_master_sel_o,
wb_master_we_o => wb_master_we_o, wb_master_we_o => wb_master_we_o,
wb_master_data_i => wb_master_data_i, wb_master_data_i => wb_master_data_i,
wb_master_data_o => wb_master_data_o, wb_master_data_o => wb_master_data_o,
wb_master_addr_o => wb_master_addr_o, wb_master_addr_o => wb_master_addr_o,
wb_master_ack_i => wb_master_ack_i, wb_master_ack_i => wb_master_ack_i,
wb_master_rty_i => wb_master_rty_i, wb_master_rty_i => wb_master_rty_i,
wb_master_err_i => wb_master_err_i, wb_master_err_i => wb_master_err_i,
wb_slave_stb_i => wb_slave_stb_i, wb_slave_stb_i => wb_slave_stb_i,
wb_slave_cyc_i => wb_slave_cyc_i, wb_slave_cyc_i => wb_slave_cyc_i,
...@@ -177,24 +177,24 @@ begin ...@@ -177,24 +177,24 @@ begin
i2c_driver: i2c_master_driver i2c_driver: i2c_master_driver
port map(tb_clk => wb_clk, port map(tb_clk => wb_clk,
sda_master_i => sda_slave_o, sda_master_i => sda_slave_o,
sda_master_o => sda_slave_i, sda_master_o => sda_slave_i,
scl_master_o => scl_slave_i, scl_master_o => scl_slave_i,
i2c_addr_op_i => s_i2c_addr_op, i2c_addr_op_i => s_i2c_addr_op,
wishbone_addr_i => s_wishbone_addr, wishbone_addr_i => s_wishbone_addr,
wr_data_i => s_wr_data, wr_data_i => s_wr_data,
rd_data_o => s_rd_data, rd_data_o => s_rd_data,
start_i => s_i2c_driver_start, start_i => s_i2c_driver_start,
start_done_o => s_i2c_driver_start_done, start_done_o => s_i2c_driver_start_done,
pause_i => s_i2c_driver_pause, pause_i => s_i2c_driver_pause,
pause_done_o => s_i2c_driver_pause_done, pause_done_o => s_i2c_driver_pause_done,
write_i => s_i2c_driver_write, write_i => s_i2c_driver_write,
write_done_o => s_i2c_driver_write_done, write_done_o => s_i2c_driver_write_done,
read_i => s_i2c_driver_read, read_i => s_i2c_driver_read,
read_done_o => s_i2c_driver_read_done); read_done_o => s_i2c_driver_read_done);
wb_driver: wishbone_driver wb_driver: wishbone_driver
...@@ -206,7 +206,7 @@ begin ...@@ -206,7 +206,7 @@ begin
wb_stb_o => wb_driver_stb_o, wb_stb_o => wb_driver_stb_o,
wb_cyc_o => wb_driver_cyc_o, wb_cyc_o => wb_driver_cyc_o,
wb_sel_o => wb_driver_sel_o, wb_sel_o => wb_driver_sel_o,
wb_we_o => wb_driver_we_o, wb_we_o => wb_driver_we_o,
wb_data_i => wb_driver_data_i, wb_data_i => wb_driver_data_i,
wb_data_o => wb_driver_data_o, wb_data_o => wb_driver_data_o,
wb_addr_o => wb_driver_addr_o, wb_addr_o => wb_driver_addr_o,
...@@ -225,7 +225,7 @@ begin ...@@ -225,7 +225,7 @@ begin
wb_slave_cyc_i <= wb_master_cyc_o when s_feedback_wb_bus = '1' wb_slave_cyc_i <= wb_master_cyc_o when s_feedback_wb_bus = '1'
else wb_driver_cyc_o; else wb_driver_cyc_o;
wb_slave_stb_i <= wb_master_stb_o when s_feedback_wb_bus = '1' wb_slave_stb_i <= wb_master_stb_o when s_feedback_wb_bus = '1'
else wb_driver_stb_o; else wb_driver_stb_o;
wb_slave_sel_i <= wb_master_sel_o when s_feedback_wb_bus = '1' wb_slave_sel_i <= wb_master_sel_o when s_feedback_wb_bus = '1'
else wb_driver_sel_o; else wb_driver_sel_o;
...@@ -265,7 +265,7 @@ begin ...@@ -265,7 +265,7 @@ begin
s_feedback_wb_bus <= '1'; s_feedback_wb_bus <= '1';
wait until rising_edge(wb_clk); wait until rising_edge(wb_clk);
end procedure; end procedure;
procedure unset_i2c_wb_feedback is procedure unset_i2c_wb_feedback is
begin begin
s_feedback_wb_bus <= '0'; s_feedback_wb_bus <= '0';
......
hdl/i2c_slave_wb_master/test/i2c_tb_pkg.vhd
View file @ a9e62b25
...@@ -65,11 +65,11 @@ package i2c_tb_pkg is ...@@ -65,11 +65,11 @@ package i2c_tb_pkg is
g_WB_ADDR_LENGTH : NATURAL := c_WB_ADDR_LENGTH; g_WB_ADDR_LENGTH : NATURAL := c_WB_ADDR_LENGTH;
g_SCL_PERIOD : TIME := c_SCL_I_PERIOD); g_SCL_PERIOD : TIME := c_SCL_I_PERIOD);
port(tb_clk : in STD_LOGIC; port(tb_clk : in STD_LOGIC;
sda_master_i : in STD_LOGIC; sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC; sda_master_o : out STD_LOGIC;
scl_master_o : out STD_LOGIC; scl_master_o : out STD_LOGIC;
i2c_addr_op_i : in STD_LOGIC_VECTOR(7 downto 0); i2c_addr_op_i : in STD_LOGIC_VECTOR(7 downto 0);
wishbone_addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0); wishbone_addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0);
wr_data_i : in STD_LOGIC_VECTOR(g_WR_DATA_LENGTH - 1 downto 0); wr_data_i : in STD_LOGIC_VECTOR(g_WR_DATA_LENGTH - 1 downto 0);
......
hdl/m25p32/rtl/m25p32_core.vhd
View file @ a9e62b25
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- --
-- Copyright CERN 2011. -- Copyright CERN 2011.
-- --
-- This documentation describes Open Hardware and is licensed under the -- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1. -- CERN OHL v. 1.1.
-- --
...@@ -15,23 +15,23 @@ ...@@ -15,23 +15,23 @@
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- --
-- Company: CERN, BE-CO-HT -- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano -- Engineer: Carlos Gil Soriano
-- --
-- Create Date: 23:57:51 06/10/2012 -- Create Date: 23:57:51 06/10/2012
-- Design Name: m25p32 wishbone access -- Design Name: m25p32 wishbone access
-- Module Name: m25p32_core - Behavioral -- Module Name: m25p32_core - Behavioral
-- Project Name: Level Conversion Circuits -- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6 -- Target Devices: Spartan 6
-- Tool versions: -- Tool versions:
-- Description: This is the logic that governs the access to the m25p32 Non -- Description: This is the logic that governs the access to the m25p32 Non
-- volatile Flash memory -- volatile Flash memory
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
library IEEE; library IEEE;
...@@ -51,10 +51,10 @@ entity m25p32_core is ...@@ -51,10 +51,10 @@ entity m25p32_core is
wb_rst_i : in STD_LOGIC; wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC; wb_clk : in STD_LOGIC;
mosi_o : out STD_LOGIC; mosi_o : out STD_LOGIC;
miso_i : in STD_LOGIC; miso_i : in STD_LOGIC;
sclk_o : out STD_LOGIC; sclk_o : out STD_LOGIC;
ss_n_o : out STD_LOGIC; ss_n_o : out STD_LOGIC;
wr_data_i : in STD_LOGIC_VECTOR(g_PAGE_SIZE*8 - 1 downto 0); wr_data_i : in STD_LOGIC_VECTOR(g_PAGE_SIZE*8 - 1 downto 0);
rd_data_o : out STD_LOGIC_VECTOR(r_SPI3'a_length - 1 downto 0); rd_data_o : out STD_LOGIC_VECTOR(r_SPI3'a_length - 1 downto 0);
...@@ -127,12 +127,12 @@ begin ...@@ -127,12 +127,12 @@ begin
g_data_length => c_PAGE_SIZE, g_data_length => c_PAGE_SIZE,
g_clk_i_period => c_CLK_I_PERIOD g_clk_i_period => c_CLK_I_PERIOD
) port map( ) port map(
rst_i => wb_rst_i, rst_i => wb_rst_i,
clk_i => wb_clk, clk_i => wb_clk,
inst_i => s_inst_spi, inst_i => s_inst_spi,
addr_i => s_addr_spi, addr_i => s_addr_spi,
data_i => s_data_i_spi, data_i => s_data_i_spi,
SPI0_i => s_SPI0_slv, SPI0_i => s_SPI0_slv,
SPI1_i => s_SPI1_slv, SPI1_i => s_SPI1_slv,
...@@ -144,7 +144,7 @@ begin ...@@ -144,7 +144,7 @@ begin
spi_mosi_o => mosi_o, spi_mosi_o => mosi_o,
spi_miso_i => miso_i, spi_miso_i => miso_i,
spi_clk_o => sclk_o, spi_clk_o => sclk_o,
spi_cs_n_o => ss_n_o spi_cs_n_o => ss_n_o
); );
p_delays : process (wb_clk) p_delays : process (wb_clk)
...@@ -161,7 +161,7 @@ begin ...@@ -161,7 +161,7 @@ begin
--! @brief Combinational process that sets a SPI operation thanks --! @brief Combinational process that sets a SPI operation thanks
--! to SPI0 and SPI1. --! to SPI0 and SPI1.
--! @param s_MEM_fsm Current state of the m25p32 SPI handler --! @param s_MEM_fsm Current state of the m25p32 SPI handler
--! s_MEM_fsm_d0 One clock delay of s_MEM_fsm --! s_MEM_fsm_d0 One clock delay of s_MEM_fsm
p_comb_SPIx : process (s_MEM_fsm, s_MEM_fsm_d0) p_comb_SPIx : process (s_MEM_fsm, s_MEM_fsm_d0)
procedure setup_SPI0 (operation : t_operations) is procedure setup_SPI0 (operation : t_operations) is
...@@ -342,21 +342,21 @@ begin ...@@ -342,21 +342,21 @@ begin
when R0_RESET => when R0_RESET =>
s_MEM_fsm <= S0_IDLE; s_MEM_fsm <= S0_IDLE;
when S0_IDLE => when S0_IDLE =>
if s_FMI.OPR = '1' then if s_FMI.OPR = '1' then
s_MEM_fsm <= S1B_WREN; s_MEM_fsm <= S1B_WREN;
end if; end if;
when S1B_WREN => when S1B_WREN =>
s_MEM_fsm <= S1_WREN; s_MEM_fsm <= S1_WREN;
when S1_WREN => when S1_WREN =>
if s_SPI2.SENT_OP = '1' then if s_SPI2.SENT_OP = '1' then
s_MEM_fsm <= S2B_SPI_INST; s_MEM_fsm <= S2B_SPI_INST;
end if; end if;
when S2B_SPI_INST => when S2B_SPI_INST =>
s_MEM_fsm <= S2_SPI_INST; s_MEM_fsm <= S2_SPI_INST;
--! We add this assignment here for being less verbose --! We add this assignment here for being less verbose
--! Easiest way to add concurrency while performing an SPI --! Easiest way to add concurrency while performing an SPI
--! operation. --! operation.
when S2_SPI_INST => when S2_SPI_INST =>
if s_SPI2.SENT_OP = '1' then if s_SPI2.SENT_OP = '1' then
s_MEM_fsm <= S3B_WRDI; s_MEM_fsm <= S3B_WRDI;
end if; end if;
......
hdl/m25p32/rtl/m25p32_pkg.vhd
View file @ a9e62b25
This diff is collapsed.
hdl/m25p32/rtl/m25p32_regs.vhd
View file @ a9e62b25
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- --
-- Copyright CERN 2011. -- Copyright CERN 2011.
-- --
-- This documentation describes Open Hardware and is licensed under the -- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1. -- CERN OHL v. 1.1.
-- --
...@@ -15,23 +15,23 @@ ...@@ -15,23 +15,23 @@
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- --
-- Company: CERN, BE-CO-HT -- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano -- Engineer: Carlos Gil Soriano
-- --
-- Create Date: 23:55:10 06/10/2012 -- Create Date: 23:55:10 06/10/2012
-- Design Name: m25p32 wishbone access -- Design Name: m25p32 wishbone access
-- Module Name: m25p32_regs - Behavioral -- Module Name: m25p32_regs - Behavioral
-- Project Name: Level Conversion Circuits -- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6 -- Target Devices: Spartan 6
-- Tool versions: -- Tool versions:
-- Description: This is a wishbone slave able to access m25p32 Non volatile -- Description: This is a wishbone slave able to access m25p32 Non volatile
-- Flash devices and manage the write and read to the memory. -- Flash devices and manage the write and read to the memory.
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
library IEEE; library IEEE;
...@@ -44,22 +44,22 @@ use work.spi_master_pkg.ALL; ...@@ -44,22 +44,22 @@ use work.spi_master_pkg.ALL;
entity m25p32_regs is entity m25p32_regs is
generic( generic(
g_INST_LENGTH : NATURAL := c_INST_LENGTH; g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH; g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH; g_DATA_LENGTH : NATURAL := c_DATA_LENGTH;
g_READ_LENGTH : NATURAL := c_READ_LENGTH; g_READ_LENGTH : NATURAL := c_READ_LENGTH;
g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1); g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port ( port (
wb_rst_i : in STD_LOGIC; wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC; wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC; wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC; wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC; wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0); wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0); wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0); wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0); wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
wb_ack_o : out STD_LOGIC; wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC; wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC; wb_err_o : out STD_LOGIC;
...@@ -115,9 +115,9 @@ begin ...@@ -115,9 +115,9 @@ begin
s_SR_m25p32 <= c_SR_m25p32_default; s_SR_m25p32 <= c_SR_m25p32_default;
wb_data_o <= (others => '0'); wb_data_o <= (others => '0');
s_wb_ack_o <= '0'; s_wb_ack_o <= '0';
s_wb_rty_o <= '0'; s_wb_rty_o <= '0';
s_wb_err_o <= '0'; s_wb_err_o <= '0';
s_rd_data <= (others => '0'); s_rd_data <= (others => '0');
else else
--! We never retry --! We never retry
...@@ -129,8 +129,8 @@ begin ...@@ -129,8 +129,8 @@ begin
if (wb_stb_i = '1' and wb_cyc_i = '1') then if (wb_stb_i = '1' and wb_cyc_i = '1') then
if (s_wb_ack_o or s_wb_rty_o or s_wb_err_o) = '1' then if (s_wb_ack_o or s_wb_rty_o or s_wb_err_o) = '1' then
s_wb_ack_o <= '0'; s_wb_ack_o <= '0';
s_wb_err_o <= '0'; s_wb_err_o <= '0';
else else
s_wb_ack_o <= '1'; s_wb_ack_o <= '1';
s_wb_err_o <= '0'; s_wb_err_o <= '0';
...@@ -141,7 +141,7 @@ begin ...@@ -141,7 +141,7 @@ begin
--! FMI address --! FMI address
when "00" => when "00" =>
if s_OP.OPA = '0' then if s_OP.OPA = '0' then
s_FMI <= f_FMI(wb_data_i(23 downto 0)); s_FMI <= f_FMI(wb_data_i(23 downto 0));
else else
s_wb_ack_o <= '0'; s_wb_ack_o <= '0';
s_wb_err_o <= '1'; s_wb_err_o <= '1';
...@@ -150,7 +150,7 @@ begin ...@@ -150,7 +150,7 @@ begin
when "01" => when "01" =>
s_SR_m25p32 <= f_SR_m25p32(wb_data_i( s_SR_m25p32 <= f_SR_m25p32(wb_data_i(
r_SR_m25p32'a_length-1 downto 0)); r_SR_m25p32'a_length-1 downto 0));
--! READ_DATA address --! READ_DATA address
when others => when others =>
s_wb_ack_o <= '0'; s_wb_ack_o <= '0';
s_wb_err_o <= '1'; s_wb_err_o <= '1';
...@@ -177,7 +177,7 @@ begin ...@@ -177,7 +177,7 @@ begin
<= f_STD_LOGIC_VECTOR(s_SR_m25p32); <= f_STD_LOGIC_VECTOR(s_SR_m25p32);
wb_data_o(31 downto r_SR_m25p32'a_length) wb_data_o(31 downto r_SR_m25p32'a_length)
<= (others => '0'); <= (others => '0');
when "10" => when "10" =>
wb_data_o <= s_rd_data; wb_data_o <= s_rd_data;
when others => when others =>
s_wb_ack_o <= '0'; s_wb_ack_o <= '0';
...@@ -193,7 +193,7 @@ begin ...@@ -193,7 +193,7 @@ begin
end if; end if;
end if; end if;
if s_OP.OPF = '1' then if s_OP.OPF = '1' then
s_FMI.OPR <= '0'; s_FMI.OPR <= '0';
end if; end if;
......
hdl/m25p32/rtl/m25p32_top.vhd
View file @ a9e62b25
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- --
-- Copyright CERN 2011. -- Copyright CERN 2011.
-- --
-- This documentation describes Open Hardware and is licensed under the -- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1. -- CERN OHL v. 1.1.
-- --
...@@ -15,22 +15,22 @@ ...@@ -15,22 +15,22 @@
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- --
-- Company: CERN, BE-CO-HT -- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano -- Engineer: Carlos Gil Soriano
-- --
-- Create Date: 01:22:27 06/11/2012 -- Create Date: 01:22:27 06/11/2012
-- Design Name: m25p32 top level -- Design Name: m25p32 top level
-- Module Name: m25p32_top - Behavioral -- Module Name: m25p32_top - Behavioral
-- Project Name: Level Conversion Circuits -- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6 -- Target Devices: Spartan 6
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
library IEEE; library IEEE;
...@@ -43,7 +43,7 @@ use work.spi_master_pkg.ALL; ...@@ -43,7 +43,7 @@ use work.spi_master_pkg.ALL;
entity m25p32_top is entity m25p32_top is
generic( generic(
g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1); g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port ( port (
wb_rst_i : in STD_LOGIC; wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC; wb_clk : in STD_LOGIC;
...@@ -51,11 +51,11 @@ entity m25p32_top is ...@@ -51,11 +51,11 @@ entity m25p32_top is
wb_stb_i : in STD_LOGIC; wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC; wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0); wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0); wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0); wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0); wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
wb_ack_o : out STD_LOGIC; wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC; wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC; wb_err_o : out STD_LOGIC;
miso_word_rcv : out STD_LOGIC; miso_word_rcv : out STD_LOGIC;
...@@ -107,8 +107,8 @@ architecture Behavioral of m25p32_top is ...@@ -107,8 +107,8 @@ architecture Behavioral of m25p32_top is
component m25p32_regs is component m25p32_regs is
generic( generic(
g_INST_LENGTH : NATURAL := c_INST_LENGTH; g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH; g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH; g_DATA_LENGTH : NATURAL := c_DATA_LENGTH;
g_READ_LENGTH : NATURAL := c_READ_LENGTH; g_READ_LENGTH : NATURAL := c_READ_LENGTH;
g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1); g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
...@@ -145,17 +145,17 @@ begin ...@@ -145,17 +145,17 @@ begin
inst_m25p32_core: m25p32_core inst_m25p32_core: m25p32_core
port map ( port map (
wb_rst_i => wb_rst_i, wb_rst_i => wb_rst_i,
wb_clk => wb_clk, wb_clk => wb_clk,
mosi_o => prom_mosi_o, mosi_o => prom_mosi_o,
miso_i => prom_din_i, miso_i => prom_din_i,
sclk_o => prom_cclk_o, sclk_o => prom_cclk_o,
ss_n_o => prom_cs0_b_n_o, ss_n_o => prom_cs0_b_n_o,
wr_data_i => s_wr_data, wr_data_i => s_wr_data,
rd_data_o => s_rd_data, rd_data_o => s_rd_data,
SR_m25p32_i => s_SR_m25p32, SR_m25p32_i => s_SR_m25p32,
rd_SPI3_o => s_rd_SPI3, rd_SPI3_o => s_rd_SPI3,
...@@ -165,13 +165,13 @@ begin ...@@ -165,13 +165,13 @@ begin
inst_m25p32_regs: m25p32_regs inst_m25p32_regs: m25p32_regs
port map ( port map (
wb_rst_i => wb_rst_i, wb_rst_i => wb_rst_i,
wb_clk => wb_clk, wb_clk => wb_clk,
wb_we_i => wb_we_i, wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i, wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i, wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i, wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i, wb_data_i => wb_data_i,
wb_data_o => wb_data_o, wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i, wb_addr_i => wb_addr_i,
...@@ -181,9 +181,9 @@ begin ...@@ -181,9 +181,9 @@ begin
rd_SPI3_i => s_rd_SPI3, rd_SPI3_i => s_rd_SPI3,
wr_data_o => s_wr_data, wr_data_o => s_wr_data,
rd_data_i => s_rd_data, rd_data_i => s_rd_data,
SR_m25p32_o => s_SR_m25p32, SR_m25p32_o => s_SR_m25p32,
OP_i => s_OP, OP_i => s_OP,
FMI_o => s_FMI FMI_o => s_FMI
......
hdl/m25p32/test/m25p32_top_tb.vhd
View file @ a9e62b25
This diff is collapsed.
hdl/m25p32/test/m25p32_top_tb_pkg.vhd
View file @ a9e62b25
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:31:47 06/20/2012 -- Create Date: 12:31:47 06/20/2012
-- Design Name: -- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd -- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield -- Project Name: spi_master_multifield
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- VHDL Test Bench Created by ISE for module: spi_master_core -- VHDL Test Bench Created by ISE for module: spi_master_core
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-- Notes: -- Notes:
-- This testbench has been automatically generated using types std_logic and -- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends -- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order -- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation -- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model. -- simulation model.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
...@@ -36,34 +36,31 @@ use work.m25p32_pkg.ALL; ...@@ -36,34 +36,31 @@ use work.m25p32_pkg.ALL;
package m25p32_top_tb_pkg is package m25p32_top_tb_pkg is
--! Constant only used in simulation --! Constant only used in simulation
constant c_WISHBONE_PERIOD : TIME := 50 ns; --! Working at 20MHz constant c_WISHBONE_PERIOD : TIME := 50 ns; --! Working at 20MHz
component m25p32_top is component m25p32_top is
generic( generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1); port (wb_rst_i : in STD_LOGIC;
port ( wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC; wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC; wb_cyc_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC; wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_cyc_i : in STD_LOGIC; wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0); wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0); wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0); wb_ack_o : out STD_LOGIC;
wb_addr_i : in STD_LOGIC_VECTOR (g_WB_ADDR_LENGTH - 1 downto 0); wb_rty_o : out STD_LOGIC;
wb_ack_o : out STD_LOGIC; wb_err_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC; miso_word_rcv : out STD_LOGIC;
op_finished_o : out STD_LOGIC;
miso_word_rcv : out STD_LOGIC;
op_finished_o : out STD_LOGIC; prom_mosi_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC;
prom_mosi_o : out STD_LOGIC; prom_cs0_b_n_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC; prom_din_i : in STD_LOGIC);
prom_cs0_b_n_o : out STD_LOGIC;
prom_din_i : in STD_LOGIC
);
end component; end component;
procedure wishbone_write ( procedure wishbone_write (
...@@ -73,10 +70,10 @@ package m25p32_top_tb_pkg is ...@@ -73,10 +70,10 @@ package m25p32_top_tb_pkg is
signal wb_cyc : out STD_LOGIC; signal wb_cyc : out STD_LOGIC;
signal wb_sel : out STD_LOGIC_VECTOR (3 downto 0); signal wb_sel : out STD_LOGIC_VECTOR (3 downto 0);
signal wb_data : out STD_LOGIC_VECTOR (31 downto 0); signal wb_data : out STD_LOGIC_VECTOR (31 downto 0);
signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0); downto 0);
reg_data : STD_LOGIC_VECTOR (31 downto 0); reg_data : STD_LOGIC_VECTOR (31 downto 0);
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0)); downto 0));
procedure wishbone_read ( procedure wishbone_read (
...@@ -86,10 +83,10 @@ package m25p32_top_tb_pkg is ...@@ -86,10 +83,10 @@ package m25p32_top_tb_pkg is
signal wb_cyc : out STD_LOGIC; signal wb_cyc : out STD_LOGIC;
signal wb_sel : out STD_LOGIC_VECTOR (3 downto 0); signal wb_sel : out STD_LOGIC_VECTOR (3 downto 0);
signal wb_data : in STD_LOGIC_VECTOR (31 downto 0); signal wb_data : in STD_LOGIC_VECTOR (31 downto 0);
signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0); downto 0);
signal read_data : out STD_LOGIC_VECTOR (31 downto 0); signal read_data : out STD_LOGIC_VECTOR (31 downto 0);
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0)); downto 0));
function fill_page return r_page; function fill_page return r_page;
...@@ -101,7 +98,7 @@ package body m25p32_top_tb_pkg is ...@@ -101,7 +98,7 @@ package body m25p32_top_tb_pkg is
--! @brief Procedure to place wishbone writes at a given address. --! @brief Procedure to place wishbone writes at a given address.
--! @param wb_clk Wishbone clock signal --! @param wb_clk Wishbone clock signal
--! wb_we Write enable signal --! wb_we Write enable signal
--! wb_stb Strobe signal --! wb_stb Strobe signal
--! wb_cyc Cycle signal --! wb_cyc Cycle signal
--! wb_sel Addres select signal --! wb_sel Addres select signal
...@@ -116,31 +113,31 @@ package body m25p32_top_tb_pkg is ...@@ -116,31 +113,31 @@ package body m25p32_top_tb_pkg is
signal wb_cyc : out STD_LOGIC; signal wb_cyc : out STD_LOGIC;
signal wb_sel : out STD_LOGIC_VECTOR (3 downto 0); signal wb_sel : out STD_LOGIC_VECTOR (3 downto 0);
signal wb_data : out STD_LOGIC_VECTOR (31 downto 0); signal wb_data : out STD_LOGIC_VECTOR (31 downto 0);
signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0); downto 0);
reg_data : STD_LOGIC_VECTOR (31 downto 0); reg_data : STD_LOGIC_VECTOR (31 downto 0);
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0)) is downto 0)) is
begin begin
wait until rising_edge(wb_clk); wait until rising_edge(wb_clk);
wb_we <= '1'; wb_we <= '1';
wb_stb <= '1'; wb_stb <= '1';
wb_cyc <= '1'; wb_cyc <= '1';
wb_sel <= X"F"; wb_sel <= X"F";
wb_data <= reg_data; wb_data <= reg_data;
wb_addr <= reg_addr; wb_addr <= reg_addr;
wait until rising_edge(wb_clk); wait until rising_edge(wb_clk);
--! Here we wait for the ack and keep till operation is finished --! Here we wait for the ack and keep till operation is finished
wait until rising_edge(wb_clk); wait until rising_edge(wb_clk);
wb_we <= '0'; wb_we <= '0';
wb_stb <= '0'; wb_stb <= '0';
wb_cyc <= '0'; wb_cyc <= '0';
wb_sel <= X"F"; wb_sel <= X"F";
end procedure; end procedure;
--! @brief Procedure to place wishbone reads at a given address. --! @brief Procedure to place wishbone reads at a given address.
--! @param wb_clk Wishbone clock signal --! @param wb_clk Wishbone clock signal
--! wb_we Write enable signal --! wb_we Write enable signal
--! wb_stb Strobe signal --! wb_stb Strobe signal
--! wb_cyc Cycle signal --! wb_cyc Cycle signal
--! wb_sel Addres select signal --! wb_sel Addres select signal
...@@ -155,34 +152,34 @@ package body m25p32_top_tb_pkg is ...@@ -155,34 +152,34 @@ package body m25p32_top_tb_pkg is
signal wb_cyc : out STD_LOGIC; signal wb_cyc : out STD_LOGIC;
signal wb_sel : out STD_LOGIC_VECTOR (3 downto 0); signal wb_sel : out STD_LOGIC_VECTOR (3 downto 0);
signal wb_data : in STD_LOGIC_VECTOR (31 downto 0); signal wb_data : in STD_LOGIC_VECTOR (31 downto 0);
signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS signal wb_addr : out STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0); downto 0);
signal read_data : out STD_LOGIC_VECTOR (31 downto 0); signal read_data : out STD_LOGIC_VECTOR (31 downto 0);
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0)) is downto 0)) is
begin begin
wait until rising_edge(wb_clk); wait until rising_edge(wb_clk);
wb_we <= '0'; wb_we <= '0';
wb_stb <= '1'; wb_stb <= '1';
wb_cyc <= '1'; wb_cyc <= '1';
wb_sel <= X"F"; wb_sel <= X"F";
wb_addr <= reg_addr; wb_addr <= reg_addr;
wait until rising_edge(wb_clk); wait until rising_edge(wb_clk);
wait until wb_data'event; wait until wb_data'event;
--! Here we wait for the ack and keep till operation is finished --! Here we wait for the ack and keep till operation is finished
read_data <= wb_data; read_data <= wb_data;
wait until rising_edge(wb_clk); wait until rising_edge(wb_clk);
wb_stb <= '0'; wb_stb <= '0';
wb_cyc <= '0'; wb_cyc <= '0';
wb_sel <= X"F"; wb_sel <= X"F";
end procedure; end procedure;
--! @brief Funtion to fill a page with predefined words. --! @brief Funtion to fill a page with predefined words.
function fill_page return r_page is function fill_page return r_page is
variable v_var0 : r_word := (word_slv => X"DEADBEEF"); variable v_var0 : r_word := (word_slv => X"DEADBEEF");
variable v_var1 : r_word := (word_slv => X"8BADF00D"); variable v_var1 : r_word := (word_slv => X"8BADF00D");
variable v_var2 : r_word := (word_slv => X"C001F007"); variable v_var2 : r_word := (word_slv => X"C001F007");
variable v_var3 : r_word := (word_slv => X"B16B00B5"); variable v_var3 : r_word := (word_slv => X"B16B00B5");
variable v_return : r_page; variable v_return : r_page;
begin begin
......
hdl/multiboot/test/multiboot_core_tb.vhd
View file @ a9e62b25
This diff is collapsed.
hdl/multiboot/test/multiboot_top_tb.vhd
View file @ a9e62b25
-- TestBench Template -- TestBench Template
library IEEE;
library work;
LIBRARY ieee; use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_1164.ALL; use IEEE.NUMERIC_STD.ALL;
USE ieee.numeric_std.ALL; use STD.TEXTIO.ALL;
USE std.textio.ALL; use work.multiboot_pkg.ALL;
ENTITY multiboot_tb IS entity multiboot_tb is
END multiboot_tb; end multiboot_tb;
ARCHITECTURE behavior OF multiboot_tb IS architecture behavior of multiboot_tb is
-- Component Declaration -- Component Declaration
component multiboot_top is component multiboot_top is
...@@ -28,71 +30,53 @@ ARCHITECTURE behavior OF multiboot_tb IS ...@@ -28,71 +30,53 @@ ARCHITECTURE behavior OF multiboot_tb IS
wb_err_o : out STD_LOGIC); wb_err_o : out STD_LOGIC);
end component; end component;
signal wb_rst_i : STD_LOGIC; signal wb_rst_i : STD_LOGIC;
signal wb_clk : STD_LOGIC; signal wb_clk : STD_LOGIC;
signal wb_we_i : STD_LOGIC; signal wb_we_i : STD_LOGIC;
signal wb_stb_i : STD_LOGIC; signal wb_stb_i : STD_LOGIC;
signal wb_cyc_i : STD_LOGIC; signal wb_cyc_i : STD_LOGIC;
signal wb_sel_i : STD_LOGIC; signal wb_sel_i : STD_LOGIC;
signal wb_data_i : STD_LOGIC_VECTOR(31 downto 0); signal wb_data_i : STD_LOGIC_VECTOR(31 downto 0);
signal wb_data_o : STD_LOGIC_VECTOR(31 downto 0); signal wb_data_o : STD_LOGIC_VECTOR(31 downto 0);
signal wb_addr_i : STD_LOGIC_VECTOR(3 downto 0); signal wb_addr_i : STD_LOGIC_VECTOR(3 downto 0);
signal wb_ack_o : STD_LOGIC; signal wb_ack_o : STD_LOGIC;
signal wb_rty_o : STD_LOGIC; signal wb_rty_o : STD_LOGIC;
signal wb_err_o : STD_LOGIC; signal wb_err_o : STD_LOGIC;
constant wb_clk_period : TIME := 50 ns; constant c_WB_CLK_PERIOD : TIME := 50 ns;
constant OP_FULLMULTIBOOT : STD_LOGIC_VECTOR(3 downto 0) := X"0"; signal CTRL_data : STD_LOGIC_VECTOR(31 downto 0);
constant OP_GENERAL1 : STD_LOGIC_VECTOR(3 downto 0) := X"1";
constant OP_GENERAL2 : STD_LOGIC_VECTOR(3 downto 0) := X"2";
constant OP_GENERAL3 : STD_LOGIC_VECTOR(3 downto 0) := X"3";
constant OP_GENERAL4 : STD_LOGIC_VECTOR(3 downto 0) := X"4";
constant OP_IPROG : STD_LOGIC_VECTOR(3 downto 0) := X"7";
constant OP_STAT : STD_LOGIC_VECTOR(3 downto 0) := X"D";
constant CTRL0_addr : STD_LOGIC_VECTOR(3 downto 0) := X"0";
constant CTRL1_addr : STD_LOGIC_VECTOR(3 downto 0) := X"1";
constant STAT_addr : STD_LOGIC_VECTOR(3 downto 0) := X"2";
constant GENERAL1_addr : STD_LOGIC_VECTOR(3 downto 0) := X"4";
constant GENERAL2_addr : STD_LOGIC_VECTOR(3 downto 0) := X"5";
constant GENERAL3_addr : STD_LOGIC_VECTOR(3 downto 0) := X"6";
constant GENERAL4_addr : STD_LOGIC_VECTOR(3 downto 0) := X"7";
signal CTRL_data : STD_LOGIC_VECTOR(31 downto 0);
signal GENERAL1_data : STD_LOGIC_VECTOR(31 downto 0); signal GENERAL1_data : STD_LOGIC_VECTOR(31 downto 0);
signal GENERAL2_data : STD_LOGIC_VECTOR(31 downto 0); signal GENERAL2_data : STD_LOGIC_VECTOR(31 downto 0);
signal GENERAL3_data : STD_LOGIC_VECTOR(31 downto 0); signal GENERAL3_data : STD_LOGIC_VECTOR(31 downto 0);
signal GENERAL4_data : STD_LOGIC_VECTOR(31 downto 0); signal GENERAL4_data : STD_LOGIC_VECTOR(31 downto 0);
file file_handler : TEXT; file file_handler : TEXT;
constant log_path : STRING := "../test/log/multiboot_top_tb.log"; constant c_LOG_PATH : STRING := "../test/log/multiboot_top_tb.log";
constant sep : CHARACTER := ht; constant sep : CHARACTER := ht;
begin begin
uut: multiboot_top uut: multiboot_top
port map( port map(wb_rst_i => wb_rst_i,
wb_rst_i => wb_rst_i, wb_clk => wb_clk,
wb_clk => wb_clk, wb_we_i => wb_we_i,
wb_we_i => wb_we_i, wb_stb_i => wb_stb_i,
wb_stb_i => wb_stb_i, wb_cyc_i => wb_cyc_i,
wb_cyc_i => wb_cyc_i, wb_sel_i => wb_sel_i,
wb_sel_i => wb_sel_i, wb_data_i => wb_data_i,
wb_data_i => wb_data_i, wb_data_o => wb_data_o,
wb_data_o => wb_data_o, wb_addr_i => wb_addr_i,
wb_addr_i => wb_addr_i, wb_ack_o => wb_ack_o,
wb_ack_o => wb_ack_o, wb_rty_o => wb_rty_o,
wb_rty_o => wb_rty_o, wb_err_o => wb_err_o);
wb_err_o => wb_err_o
);
wb_clk_process: process wb_clk_process: process
begin begin
wb_clk <= '1'; wb_clk <= '1';
wait for wb_clk_period/2; wait for c_WB_CLK_PERIOD/2;
wb_clk <= '0'; wb_clk <= '0';
wait for wb_clk_period/2; wait for c_WB_CLK_PERIOD/2;
end process; end process;
...@@ -100,11 +84,11 @@ begin ...@@ -100,11 +84,11 @@ begin
procedure rst is procedure rst is
begin begin
wait for wb_clk_period; wait for c_WB_CLK_PERIOD;
wb_rst_i <= '1'; wb_rst_i <= '1';
wait for wb_clk_period; wait for c_WB_CLK_PERIOD;
wb_rst_i <= '0'; wb_rst_i <= '0';
wait for wb_clk_period*25; wait for c_WB_CLK_PERIOD*25;
end rst; end rst;
procedure read_wishbone(addr: STD_LOGIC_VECTOR(3 downto 0)) is procedure read_wishbone(addr: STD_LOGIC_VECTOR(3 downto 0)) is
...@@ -114,7 +98,7 @@ begin ...@@ -114,7 +98,7 @@ begin
wb_stb_i <= '1'; wb_stb_i <= '1';
wb_cyc_i <= '1'; wb_cyc_i <= '1';
wb_addr_i <= addr; wb_addr_i <= addr;
wait for wb_clk_period*3/2; wait for c_WB_CLK_PERIOD*3/2;
wait until rising_edge(wb_clk); wait until rising_edge(wb_clk);
wb_we_i <= '0'; wb_we_i <= '0';
wb_stb_i <= '0'; wb_stb_i <= '0';
...@@ -130,7 +114,7 @@ begin ...@@ -130,7 +114,7 @@ begin
wb_cyc_i <= '1'; wb_cyc_i <= '1';
wb_addr_i <= addr; wb_addr_i <= addr;
wb_data_i <= data; wb_data_i <= data;
wait for wb_clk_period*3/2; wait for c_WB_CLK_PERIOD*3/2;
wait until rising_edge(wb_clk); wait until rising_edge(wb_clk);
wb_we_i <= '0'; wb_we_i <= '0';
wb_stb_i <= '0'; wb_stb_i <= '0';
...@@ -145,12 +129,12 @@ begin ...@@ -145,12 +129,12 @@ begin
variable line_buffer : LINE; variable line_buffer : LINE;
begin begin
if data = reference then if data = reference then
write(line_buffer, string'(test_id&sep&"OK"&sep&msg)); write(line_buffer, string'(test_id&sep&"OK"&sep&msg));
else else
write(line_buffer, string'(test_id&sep&"Fail"&sep&msg)); write(line_buffer, string'(test_id&sep&"Fail"&sep&msg));
end if; end if;
writeline(file_handler, line_buffer); writeline(file_handler, line_buffer);
assert data = reference report "Bad"&msg; assert data = reference report "Bad"&msg;
end procedure; end procedure;
procedure assert32_to_file(data:STD_LOGIC_VECTOR(31 downto 0); procedure assert32_to_file(data:STD_LOGIC_VECTOR(31 downto 0);
...@@ -160,31 +144,31 @@ begin ...@@ -160,31 +144,31 @@ begin
variable line_buffer : LINE; variable line_buffer : LINE;
begin begin
if data = reference then if data = reference then
write(line_buffer, string'(test_id&sep&"OK"&sep&msg)); write(line_buffer, string'(test_id&sep&"OK"&sep&msg));
else else
write(line_buffer, string'(test_id&sep&"Fail"&sep&msg)); write(line_buffer, string'(test_id&sep&"Fail"&sep&msg));
end if; end if;
writeline(file_handler, line_buffer); writeline(file_handler, line_buffer);
assert data = reference report "Bad"&msg; assert data = reference report "Bad"&msg;
end procedure; end procedure;
variable header_line_buffer : LINE; variable header_line_buffer : LINE;
begin begin
file_open(file_handler, log_path, WRITE_MODE); file_open(file_handler, c_LOG_PATH, WRITE_MODE);
write(header_line_buffer, string'("Test ID"&sep&"Status"&sep&"Description")); write(header_line_buffer, string'("Test ID"&sep&"Status"&sep&"Description"));
writeline(file_handler, header_line_buffer); writeline(file_handler, header_line_buffer);
wait for 2*wb_clk_period; wait for 2*c_WB_CLK_PERIOD;
rst; rst;
GENERAL1_data <= (others => '0'); GENERAL1_data <= (others => '0');
GENERAL2_data <= (others => '0'); GENERAL2_data <= (others => '0');
GENERAL3_data <= (others => '0'); GENERAL3_data <= (others => '0');
GENERAL4_data <= (others => '0'); GENERAL4_data <= (others => '0');
wait for 2*wb_clk_period; wait for 2*c_WB_CLK_PERIOD;
read_wishbone(CTRL_addr); read_wishbone(CTRL_addr);
assert32_to_file(wb_data_o, X"00000000","0x0","CTRL register initialization"); assert32_to_file(wb_data_o, X"00000000","0x0","CTRL register initialization");
read_wishbone(STAT_addr); read_wishbone(STAT_addr);
......
hdl/spi_master_multifield/rtl/spi_master_regs.vhd
View file @ a9e62b25
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- --
-- Copyright CERN 2011. -- Copyright CERN 2011.
-- --
-- This documentation describes Open Hardware and is licensed under the -- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1. -- CERN OHL v. 1.1.
-- --
...@@ -15,24 +15,24 @@ ...@@ -15,24 +15,24 @@
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- --
-- Company: CERN, BE-CO-HT -- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano -- Engineer: Carlos Gil Soriano
-- --
-- Create Date: 17:34:08 06/14/2012 -- Create Date: 17:34:08 06/14/2012
-- Design Name: -- Design Name:
-- Module Name: spi_master_core - Behavioral -- Module Name: spi_master_core - Behavioral
-- Project Name: CTDAH/SVEC -- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6 -- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4 -- Tool versions: Xilinx ISE 13.4
-- Description: Wishbone access for SPI core. -- Description: Wishbone access for SPI core.
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: 0.1 -- Revision: 0.1
-- 0.01 + File Created -- 0.01 + File Created
-- 0.1 - Alpha version. Able to write and output data correctly at -- 0.1 - Alpha version. Able to write and output data correctly at
-- different configurations. -- different configurations.
-- Additional Comments: -- Additional Comments:
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
...@@ -44,22 +44,22 @@ use work.spi_master_pkg.ALL; ...@@ -44,22 +44,22 @@ use work.spi_master_pkg.ALL;
entity spi_master_regs is entity spi_master_regs is
port( port(
wb_rst_i : in STD_LOGIC; wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC; wb_clk_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC; wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC; wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0); wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_we_i : in STD_LOGIC; wb_we_i : in STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0); wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0); wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0); wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC; wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC; wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC; wb_err_o : out STD_LOGIC;
SPI0_o : out STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0); SPI0_o : out STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0); SPI1_o : out STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
SPI2_i : in STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0); SPI2_i : in STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
SPI3_i : in STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0); SPI3_i : in STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
...@@ -73,16 +73,16 @@ architecture Behavioral of spi_master_regs is ...@@ -73,16 +73,16 @@ architecture Behavioral of spi_master_regs is
signal s_SPI2 : STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0); signal s_SPI2 : STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
signal s_wb_ack : STD_LOGIC; signal s_wb_ack : STD_LOGIC;
signal s_wb_rty : STD_LOGIC; signal s_wb_rty : STD_LOGIC;
signal s_wb_err : STD_LOGIC; signal s_wb_err : STD_LOGIC;
begin begin
wb_ack_o <= s_wb_ack; wb_ack_o <= s_wb_ack;
wb_rty_o <= s_wb_rty; wb_rty_o <= s_wb_rty;
wb_err_o <= s_wb_err; wb_err_o <= s_wb_err;
SPI0_o <= s_SPI0; SPI0_o <= s_SPI0;
SPI1_o <= s_SPI1; SPI1_o <= s_SPI1;
s_SPI2 <= SPI2_i; s_SPI2 <= SPI2_i;
...@@ -106,21 +106,21 @@ begin ...@@ -106,21 +106,21 @@ begin
case wb_addr_i is case wb_addr_i is
when c_SPI0_addr => when c_SPI0_addr =>
s_SPI0 <= wb_data_i; s_SPI0 <= wb_data_i;
s_wb_ack <= '1'; s_wb_ack <= '1';
when c_SPI1_addr => when c_SPI1_addr =>
s_SPI1 <= wb_data_i; s_SPI1 <= wb_data_i;
s_wb_ack <= '1'; s_wb_ack <= '1';
when others => when others =>
s_wb_err <= '1'; s_wb_err <= '1';
end case; end case;
when others => when others =>
case wb_addr_i is case wb_addr_i is
when c_SPI0_addr => when c_SPI0_addr =>
wb_data_o <= s_SPI0; wb_data_o <= s_SPI0;
s_wb_ack <= '1'; s_wb_ack <= '1';
when c_SPI1_addr => when c_SPI1_addr =>
wb_data_o <= s_SPI1; wb_data_o <= s_SPI1;
s_wb_ack <= '1'; s_wb_ack <= '1';
when c_SPI2_addr => when c_SPI2_addr =>
wb_data_o(15 downto 0) <= s_SPI2; wb_data_o(15 downto 0) <= s_SPI2;
wb_data_o(31 downto 16) <= (others => '0'); wb_data_o(31 downto 16) <= (others => '0');
......
hdl/spi_master_multifield/rtl/spi_master_top.vhd
View file @ a9e62b25
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- --
-- Copyright CERN 2011. -- Copyright CERN 2011.
-- --
-- This documentation describes Open Hardware and is licensed under the -- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1. -- CERN OHL v. 1.1.
-- --
...@@ -15,25 +15,25 @@ ...@@ -15,25 +15,25 @@
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- --
-- Company: CERN, BE-CO-HT -- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano -- Engineer: Carlos Gil Soriano
-- --
-- Create Date: 17:10:27 06/15/2012 -- Create Date: 17:10:27 06/15/2012
-- Design Name: -- Design Name:
-- Module Name: spi_master_top - Behavioral -- Module Name: spi_master_top - Behavioral
-- Project Name: CTDAH/SVEC -- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6 -- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4 -- Tool versions: Xilinx ISE 13.4
-- Description: This is a spi_master with programable field length and progra -- Description: This is a spi_master with programable field length and progra
-- mable setup and hold chip select times. -- mable setup and hold chip select times.
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: 0.1 -- Revision: 0.1
-- 0.01 + File Created -- 0.01 + File Created
-- 0.1 - Alpha version. Able to write and output data correctly at -- 0.1 - Alpha version. Able to write and output data correctly at
-- different configurations. -- different configurations.
-- Additional Comments: -- Additional Comments:
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
...@@ -48,7 +48,7 @@ entity spi_master_top is ...@@ -48,7 +48,7 @@ entity spi_master_top is
g_INST_LENGTH : NATURAL := c_INST_LENGTH; g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH; g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH; g_DATA_LENGTH : NATURAL := c_DATA_LENGTH;
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD); g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
port( port(
wb_clk : in STD_LOGIC; wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC; wb_rst_i : in STD_LOGIC;
...@@ -108,7 +108,7 @@ architecture Behavioral of spi_master_top is ...@@ -108,7 +108,7 @@ architecture Behavioral of spi_master_top is
port( port(
wb_rst_i : in STD_LOGIC; wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC; wb_clk_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC; wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC; wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0); wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
...@@ -119,7 +119,7 @@ architecture Behavioral of spi_master_top is ...@@ -119,7 +119,7 @@ architecture Behavioral of spi_master_top is
wb_ack_o : out STD_LOGIC; wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC; wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC; wb_err_o : out STD_LOGIC;
SPI0_o : out STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0); SPI0_o : out STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0); SPI1_o : out STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
SPI2_i : in STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0); SPI2_i : in STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
...@@ -128,52 +128,52 @@ architecture Behavioral of spi_master_top is ...@@ -128,52 +128,52 @@ architecture Behavioral of spi_master_top is
end component; end component;
signal s_SPI0 : STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0); signal s_SPI0 : STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
signal s_SPI1 : STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0); signal s_SPI1 : STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
signal s_SPI2 : STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0); signal s_SPI2 : STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
signal s_SPI3 : STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0); signal s_SPI3 : STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
begin begin
inst_spi_master_core: spi_master_core inst_spi_master_core: spi_master_core
port map( port map(
rst_i => wb_rst_i, rst_i => wb_rst_i,
clk_i => wb_clk, clk_i => wb_clk,
inst_i => inst_i, inst_i => inst_i,
addr_i => addr_i, addr_i => addr_i,
data_i => data_i, data_i => data_i,
SPI0_i => s_SPI0, SPI0_i => s_SPI0,
SPI1_i => s_SPI1, SPI1_i => s_SPI1,
SPI2_o => s_SPI2, SPI2_o => s_SPI2,
SPI3_o => s_SPI3, SPI3_o => s_SPI3,
spi_mosi_o => spi_mosi_o, spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i, spi_miso_i => spi_miso_i,
spi_clk_o => spi_clk_o, spi_clk_o => spi_clk_o,
spi_cs_n_o => spi_cs_n_o spi_cs_n_o => spi_cs_n_o
); );
inst_spi_master_regs: spi_master_regs inst_spi_master_regs: spi_master_regs
port map( port map(
wb_rst_i => wb_rst_i, wb_rst_i => wb_rst_i,
wb_clk_i => wb_clk, wb_clk_i => wb_clk,
wb_stb_i => wb_stb_i, wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i, wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i, wb_sel_i => wb_sel_i,
wb_we_i => wb_we_i, wb_we_i => wb_we_i,
wb_data_i => wb_data_i, wb_data_i => wb_data_i,
wb_data_o => wb_data_o, wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i, wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o, wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o, wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o, wb_err_o => wb_err_o,
SPI0_o => s_SPI0, SPI0_o => s_SPI0,
SPI1_o => s_SPI1, SPI1_o => s_SPI1,
SPI2_i => s_SPI2, SPI2_i => s_SPI2,
SPI3_i => s_SPI3, SPI3_i => s_SPI3,
); );
end Behavioral; end Behavioral;
......
hdl/spi_master_multifield/test/spi_analyser.vhd
View file @ a9e62b25
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:31:47 06/20/2012 -- Create Date: 12:31:47 06/20/2012
-- Design Name: -- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd -- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield -- Project Name: spi_master_multifield
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- VHDL Test Bench Created by ISE for module: spi_master_core -- VHDL Test Bench Created by ISE for module: spi_master_core
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-- Notes: -- Notes:
-- This testbench has been automatically generated using types std_logic and -- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends -- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order -- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation -- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model. -- simulation model.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
...@@ -50,23 +50,23 @@ entity spi_analyser is ...@@ -50,23 +50,23 @@ entity spi_analyser is
inst_check_o : out STD_LOGIC_VECTOR (g_INST_LENGTH*8 - 1 downto 0); inst_check_o : out STD_LOGIC_VECTOR (g_INST_LENGTH*8 - 1 downto 0);
addr_check_o : out STD_LOGIC_VECTOR (g_ADDR_LENGTH*8 - 1 downto 0); addr_check_o : out STD_LOGIC_VECTOR (g_ADDR_LENGTH*8 - 1 downto 0);
data_check_o : out STD_LOGIC_VECTOR (g_DATA_LENGTH*8 - 1 downto 0); data_check_o : out STD_LOGIC_VECTOR (g_DATA_LENGTH*8 - 1 downto 0);
end_inst_flag_o : out STD_LOGIC; end_inst_flag_o : out STD_LOGIC;
end_addr_flag_o : out STD_LOGIC; end_addr_flag_o : out STD_LOGIC;
end_data_flag_o : out STD_LOGIC end_data_flag_o : out STD_LOGIC
); );
end spi_analyser; end spi_analyser;
architecture Behavioral of spi_analyser is architecture Behavioral of spi_analyser is
signal s_spi_count : NATURAL := 0; signal s_spi_count : NATURAL := 0;
signal s_SPI0 : r_SPI0; signal s_SPI0 : r_SPI0;
signal s_SPI1 : r_SPI1; signal s_SPI1 : r_SPI1;
signal s_SPI1_tmp : r_SPI1; signal s_SPI1_tmp : r_SPI1;
signal s_spi_mosi : STD_LOGIC; signal s_spi_mosi : STD_LOGIC;
signal s_spi_clk : STD_LOGIC; signal s_spi_clk : STD_LOGIC;
signal s_inst_check : STD_LOGIC_VECTOR (g_INST_LENGTH*8 - 1 downto 0) signal s_inst_check : STD_LOGIC_VECTOR (g_INST_LENGTH*8 - 1 downto 0)
:= (others => '0'); := (others => '0');
...@@ -87,17 +87,17 @@ begin ...@@ -87,17 +87,17 @@ begin
inst_check_o <= s_inst_check; inst_check_o <= s_inst_check;
addr_check_o <= s_addr_check; addr_check_o <= s_addr_check;
data_check_o <= s_data_check; data_check_o <= s_data_check;
end_inst_flag_o <= s_end_inst_flag; end_inst_flag_o <= s_end_inst_flag;
end_addr_flag_o <= s_end_addr_flag; end_addr_flag_o <= s_end_addr_flag;
end_data_flag_o <= s_end_data_flag; end_data_flag_o <= s_end_data_flag;
s_SPI1_tmp <= SPI1_i; s_SPI1_tmp <= SPI1_i;
p_latch : process (s_SPI1_tmp.SEND_OP) p_latch : process (s_SPI1_tmp.SEND_OP)
begin begin
if rising_edge(s_SPI1_tmp.SEND_OP) then if rising_edge(s_SPI1_tmp.SEND_OP) then
s_SPI0 <= SPI0_i; s_SPI0 <= SPI0_i;
s_SPI1 <= SPI1_i; s_SPI1 <= SPI1_i;
end if; end if;
end process; end process;
...@@ -130,11 +130,11 @@ begin ...@@ -130,11 +130,11 @@ begin
end if; end if;
else else
end if; end if;
if s_SPI1.SEND_ADDR = '1' then if s_SPI1.SEND_ADDR = '1' then
if s_SPI1.SEND_INST = '1' then if s_SPI1.SEND_INST = '1' then
if s_spi_count >= (v_inst_length + v_addr_length) then if s_spi_count >= (v_inst_length + v_addr_length) then
elsif s_spi_count >= v_inst_length elsif s_spi_count >= v_inst_length
and s_spi_count < (v_inst_length + v_addr_length) then and s_spi_count < (v_inst_length + v_addr_length) then
s_addr_check(v_addr_length - 1 - (s_spi_count - s_addr_check(v_addr_length - 1 - (s_spi_count -
v_inst_length)) <= s_spi_mosi; v_inst_length)) <= s_spi_mosi;
...@@ -158,7 +158,7 @@ begin ...@@ -158,7 +158,7 @@ begin
end if; end if;
else else
end if; end if;
if s_SPI1.SEND_DATA = '1' then if s_SPI1.SEND_DATA = '1' then
if s_SPI1.SEND_INST = '1' then if s_SPI1.SEND_INST = '1' then
if s_SPI1.SEND_ADDR = '1' then if s_SPI1.SEND_ADDR = '1' then
...@@ -216,9 +216,9 @@ begin ...@@ -216,9 +216,9 @@ begin
begin begin
if rst_i = '1' then if rst_i = '1' then
s_spi_count <= 0; s_spi_count <= 0;
s_inst_check <= (others => '0') ; s_inst_check <= (others => '0') ;
s_addr_check <= (others => '0') ; s_addr_check <= (others => '0') ;
s_data_check <= (others => '0') ; s_data_check <= (others => '0') ;
else else
if rising_edge(spi_clk_o) then if rising_edge(spi_clk_o) then
--! Read cycle --! Read cycle
......
hdl/spi_master_multifield/test/spi_analyser_pkg.vhd
View file @ a9e62b25
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:31:47 06/20/2012 -- Create Date: 12:31:47 06/20/2012
-- Design Name: -- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd -- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield -- Project Name: spi_master_multifield
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- VHDL Test Bench Created by ISE for module: spi_master_core -- VHDL Test Bench Created by ISE for module: spi_master_core
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-- Notes: -- Notes:
-- This testbench has been automatically generated using types std_logic and -- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends -- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order -- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation -- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model. -- simulation model.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
...@@ -32,7 +32,7 @@ use IEEE.STD_LOGIC_1164.ALL; ...@@ -32,7 +32,7 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; use IEEE.NUMERIC_STD.ALL;
use work.spi_master_pkg.ALL; use work.spi_master_pkg.ALL;
package spi_analyser_pkg is package spi_analyser_pkg is
component spi_analyser component spi_analyser
port( rst_i : in STD_LOGIC; port( rst_i : in STD_LOGIC;
...@@ -102,7 +102,7 @@ package spi_analyser_pkg is ...@@ -102,7 +102,7 @@ package spi_analyser_pkg is
signal data_i : out STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0); signal data_i : out STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0);
inst : in STD_LOGIC_VECTOR(8*c_INST_LENGTH - 1 downto 0); inst : in STD_LOGIC_VECTOR(8*c_INST_LENGTH - 1 downto 0);
addr : in STD_LOGIC_VECTOR(8*c_ADDR_LENGTH - 1 downto 0); addr : in STD_LOGIC_VECTOR(8*c_ADDR_LENGTH - 1 downto 0);
data : in STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0)); data : in STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0));
procedure send_SPI_and_wait (signal clk_i : in STD_LOGIC; procedure send_SPI_and_wait (signal clk_i : in STD_LOGIC;
signal SPI1 : out r_SPI1; signal SPI1 : out r_SPI1;
...@@ -111,12 +111,12 @@ package spi_analyser_pkg is ...@@ -111,12 +111,12 @@ package spi_analyser_pkg is
send_addr: in STD_LOGIC; send_addr: in STD_LOGIC;
send_data: in STD_LOGIC; send_data: in STD_LOGIC;
read_miso: in STD_LOGIC; read_miso: in STD_LOGIC;
clk_div : in UNSIGNED(3 downto 0)); clk_div : in UNSIGNED(3 downto 0));
procedure set_SPI1 ( procedure set_SPI1 (
signal clk_i : in STD_LOGIC; signal clk_i : in STD_LOGIC;
signal SPI1 : out r_SPI1; signal SPI1 : out r_SPI1;
signal SPI2 : in r_SPI2; signal SPI2 : in r_SPI2;
send_inst : in STD_LOGIC; send_inst : in STD_LOGIC;
send_addr : in STD_LOGIC; send_addr : in STD_LOGIC;
send_data : in STD_LOGIC; send_data : in STD_LOGIC;
...@@ -151,7 +151,7 @@ package spi_analyser_pkg is ...@@ -151,7 +151,7 @@ package spi_analyser_pkg is
signal data_i : out STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0); signal data_i : out STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0);
inst : in STD_LOGIC_VECTOR(8*c_INST_LENGTH - 1 downto 0); inst : in STD_LOGIC_VECTOR(8*c_INST_LENGTH - 1 downto 0);
addr : in STD_LOGIC_VECTOR(8*c_ADDR_LENGTH - 1 downto 0); addr : in STD_LOGIC_VECTOR(8*c_ADDR_LENGTH - 1 downto 0);
data : in STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0)); data : in STD_LOGIC_VECTOR(8*c_DATA_LENGTH - 1 downto 0));
end spi_analyser_pkg; end spi_analyser_pkg;
...@@ -254,8 +254,8 @@ package body spi_analyser_pkg is ...@@ -254,8 +254,8 @@ package body spi_analyser_pkg is
procedure set_SPI1 ( procedure set_SPI1 (
signal clk_i : in STD_LOGIC; signal clk_i : in STD_LOGIC;
signal SPI1 : out r_SPI1; signal SPI1 : out r_SPI1;
signal SPI2 : in r_SPI2; signal SPI2 : in r_SPI2;
send_inst : in STD_LOGIC; send_inst : in STD_LOGIC;
send_addr : in STD_LOGIC; send_addr : in STD_LOGIC;
send_data : in STD_LOGIC; send_data : in STD_LOGIC;
...@@ -274,7 +274,7 @@ package body spi_analyser_pkg is ...@@ -274,7 +274,7 @@ package body spi_analyser_pkg is
inst, addr, data); inst, addr, data);
send_SPI_and_wait(clk_i, SPI1, SPI2, send_SPI_and_wait(clk_i, SPI1, SPI2,
send_inst, send_addr, send_data, read_mosi, send_inst, send_addr, send_data, read_mosi,
v_clk_div); v_clk_div);
end procedure; end procedure;
......
hdl/spi_master_multifield/test/spi_master_core_tb.vhd
View file @ a9e62b25
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:31:47 06/20/2012 -- Create Date: 12:31:47 06/20/2012
-- Design Name: -- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd -- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield -- Project Name: spi_master_multifield
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- VHDL Test Bench Created by ISE for module: spi_master_core -- VHDL Test Bench Created by ISE for module: spi_master_core
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-- Notes: -- Notes:
-- This testbench has been automatically generated using types std_logic and -- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends -- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order -- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation -- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model. -- simulation model.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
...@@ -32,11 +32,11 @@ use IEEE.STD_LOGIC_1164.ALL; ...@@ -32,11 +32,11 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; use IEEE.NUMERIC_STD.ALL;
use work.spi_master_pkg.ALL; use work.spi_master_pkg.ALL;
use work.spi_analyser_pkg.ALL; use work.spi_analyser_pkg.ALL;
entity spi_master_core_tb is entity spi_master_core_tb is
end spi_master_core_tb; end spi_master_core_tb;
architecture Behavioral of spi_master_core_tb is architecture Behavioral of spi_master_core_tb is
component spi_master_core component spi_master_core
generic( generic(
...@@ -47,7 +47,7 @@ architecture Behavioral of spi_master_core_tb is ...@@ -47,7 +47,7 @@ architecture Behavioral of spi_master_core_tb is
port( port(
rst_i : in STD_LOGIC; rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC; clk_i : in STD_LOGIC;
inst_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0); inst_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0); addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0); data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
...@@ -67,7 +67,7 @@ architecture Behavioral of spi_master_core_tb is ...@@ -67,7 +67,7 @@ architecture Behavioral of spi_master_core_tb is
-- Component Declaration for the Unit Under Test (UUT) -- Component Declaration for the Unit Under Test (UUT)
signal rst_i : STD_LOGIC := '0'; signal rst_i : STD_LOGIC := '0';
signal clk_i : STD_LOGIC := '0'; signal clk_i : STD_LOGIC := '0';
...@@ -80,11 +80,11 @@ architecture Behavioral of spi_master_core_tb is ...@@ -80,11 +80,11 @@ architecture Behavioral of spi_master_core_tb is
signal data_i : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0) := (others => '0'); signal data_i : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0) := (others => '0');
--Inputs --Inputs
signal s_SPI0 : r_SPI0; signal s_SPI0 : r_SPI0;
signal s_SPI0_slv : STD_LOGIC_VECTOR(r_SPI0'a_length - 1 downto 0); signal s_SPI0_slv : STD_LOGIC_VECTOR(r_SPI0'a_length - 1 downto 0);
signal s_SPI1 : r_SPI1; signal s_SPI1 : r_SPI1;
signal s_SPI1_slv : STD_LOGIC_VECTOR(r_SPI1'a_length - 1 downto 0); signal s_SPI1_slv : STD_LOGIC_VECTOR(r_SPI1'a_length - 1 downto 0);
signal s_SPI2 : r_SPI2; signal s_SPI2 : r_SPI2;
signal s_SPI2_slv : STD_LOGIC_VECTOR(r_SPI2'a_length - 1 downto 0); signal s_SPI2_slv : STD_LOGIC_VECTOR(r_SPI2'a_length - 1 downto 0);
signal s_spi_mosi : STD_LOGIC; signal s_spi_mosi : STD_LOGIC;
...@@ -99,8 +99,8 @@ architecture Behavioral of spi_master_core_tb is ...@@ -99,8 +99,8 @@ architecture Behavioral of spi_master_core_tb is
signal s_data_check : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0) := signal s_data_check : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0) :=
(others => '0'); (others => '0');
signal s_end_inst_flag : STD_LOGIC; signal s_end_inst_flag : STD_LOGIC;
signal s_end_addr_flag : STD_LOGIC; signal s_end_addr_flag : STD_LOGIC;
signal s_end_data_flag : STD_LOGIC; signal s_end_data_flag : STD_LOGIC;
--Outputs --Outputs
...@@ -118,9 +118,9 @@ architecture Behavioral of spi_master_core_tb is ...@@ -118,9 +118,9 @@ architecture Behavioral of spi_master_core_tb is
begin begin
s_SPI0_slv <= f_STD_LOGIC_VECTOR(s_SPI0); s_SPI0_slv <= f_STD_LOGIC_VECTOR(s_SPI0);
s_SPI1_slv <= f_STD_LOGIC_VECTOR(s_SPI1); s_SPI1_slv <= f_STD_LOGIC_VECTOR(s_SPI1);
s_SPI2 <= f_SPI2(s_SPI2_slv); s_SPI2 <= f_SPI2(s_SPI2_slv);
-- Instantiate the Unit Under Test (UUT) -- Instantiate the Unit Under Test (UUT)
uut: spi_master_core port map ( uut: spi_master_core port map (
...@@ -139,21 +139,21 @@ begin ...@@ -139,21 +139,21 @@ begin
spi_cs_n_o => s_spi_cs_n); spi_cs_n_o => s_spi_cs_n);
tester : spi_analyser port map( tester : spi_analyser port map(
rst_i => s_rst_spi_analyser, rst_i => s_rst_spi_analyser,
SPI0_i => s_SPI0, SPI0_i => s_SPI0,
SPI1_i => s_SPI1, SPI1_i => s_SPI1,
spi_mosi_o => s_spi_mosi, spi_mosi_o => s_spi_mosi,
spi_miso_i => s_spi_miso, spi_miso_i => s_spi_miso,
spi_clk_o => s_spi_clk, spi_clk_o => s_spi_clk,
spi_cs_n_o => s_spi_cs_n, spi_cs_n_o => s_spi_cs_n,
inst_check_o => s_inst_check, inst_check_o => s_inst_check,
addr_check_o => s_addr_check, addr_check_o => s_addr_check,
data_check_o => s_data_check, data_check_o => s_data_check,
end_inst_flag_o => s_end_inst_flag, end_inst_flag_o => s_end_inst_flag,
end_addr_flag_o => s_end_addr_flag, end_addr_flag_o => s_end_addr_flag,
end_data_flag_o => s_end_data_flag); end_data_flag_o => s_end_data_flag);
...@@ -171,11 +171,11 @@ begin ...@@ -171,11 +171,11 @@ begin
procedure init_cond is procedure init_cond is
begin begin
inst_i <= (others => '0'); inst_i <= (others => '0');
addr_i <= (others => '0'); addr_i <= (others => '0');
data_i <= (others => '0'); data_i <= (others => '0');
s_SPI0 <= c_SPI0_default; s_SPI0 <= c_SPI0_default;
s_SPI1 <= c_SPI1_default; s_SPI1 <= c_SPI1_default;
end procedure; end procedure;
procedure set_FIFO_contents( procedure set_FIFO_contents(
...@@ -209,13 +209,13 @@ begin ...@@ -209,13 +209,13 @@ begin
s_SPI0, s_SPI1, s_SPI2, s_SPI0, s_SPI1, s_SPI2,
cpol, cpha, clk_div, cpol, cpha, clk_div,
inst_length, addr_length, data_length, read_length, inst_length, addr_length, data_length, read_length,
send_inst, send_addr, send_data, read_mosi, send_inst, send_addr, send_data, read_mosi,
inst_i, addr_i, data_i, inst_i, addr_i, data_i,
inst, addr, data); inst, addr, data);
end procedure; end procedure;
begin begin
init_cond; init_cond;
wait until rising_edge(clk_i); wait until rising_edge(clk_i);
......
hdl/spi_master_multifield/test/spi_slave_writer.vhd
View file @ a9e62b25
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:31:47 06/20/2012 -- Create Date: 12:31:47 06/20/2012
-- Design Name: -- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd -- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield -- Project Name: spi_master_multifield
-- Target Device: -- Target Device:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- VHDL Test Bench Created by ISE for module: spi_master_core -- VHDL Test Bench Created by ISE for module: spi_master_core
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
-- Notes: -- Notes:
-- This testbench has been automatically generated using types std_logic and -- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends -- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order -- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation -- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model. -- simulation model.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
...@@ -50,8 +50,8 @@ entity spi_slave_writer is ...@@ -50,8 +50,8 @@ entity spi_slave_writer is
); );
end spi_slave_writer; end spi_slave_writer;
architecture Behavioral of spi_slave_writer is architecture Behavioral of spi_slave_writer is
signal s_spi_count : NATURAL := 0; signal s_spi_count : NATURAL := 0;
signal s_SPI0 : r_SPI0; signal s_SPI0 : r_SPI0;
...@@ -59,7 +59,7 @@ architecture Behavioral of spi_slave_writer is ...@@ -59,7 +59,7 @@ architecture Behavioral of spi_slave_writer is
signal s_STATUS : r_STATUS; signal s_STATUS : r_STATUS;
signal s_spi_clk : STD_LOGIC; signal s_spi_clk : STD_LOGIC;
signal s_read : STD_LOGIC_VECTOR (g_READ_LENGTH*8 - 1 downto 0) signal s_read : STD_LOGIC_VECTOR (g_READ_LENGTH*8 - 1 downto 0)
:= (others => '0'); := (others => '0');
...@@ -118,10 +118,10 @@ begin ...@@ -118,10 +118,10 @@ begin
spi_miso_o <= 'Z'; spi_miso_o <= 'Z';
s_end_read_flag <= '0'; s_end_read_flag <= '0';
else else
if rising_edge(spi_clk_i) if rising_edge(spi_clk_i)
and (write_on_rise(s_SPI0) = '1') then and (write_on_rise(s_SPI0) = '1') then
write_bit; write_bit;
elsif falling_edge(spi_clk_i) elsif falling_edge(spi_clk_i)
and (write_on_rise(s_SPI0) = '0') then and (write_on_rise(s_SPI0) = '0') then
write_bit; write_bit;
end if; end if;
......
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