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Conv TTL Blocking
Commit c782c3fc authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Added test01 (thermometer) support in HDL, pending testing.

parent ee3b4c61
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hdl/pts/syn/conv_ttl_blo_v2.gise
View file @ c782c3fc
...@@ -78,35 +78,35 @@ ...@@ -78,35 +78,35 @@
</files> </files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"> <transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1364415005" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1364415005"> <transform xil_pn:end_ts="1365009260" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1365009260">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1364416893" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1364416893"> <transform xil_pn:end_ts="1365009260" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1365009260">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
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<transform xil_pn:end_ts="1364416893" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1364416893"> <transform xil_pn:end_ts="1365009260" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1365009260">
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<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
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<transform xil_pn:end_ts="1364416893" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1364416893"> <transform xil_pn:end_ts="1365009260" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1365009260">
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<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1364416905" xil_pn:in_ck="761168912318142379" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1364416893"> <transform xil_pn:end_ts="1365009276" xil_pn:in_ck="761168912318142379" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1365009260">
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<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -124,11 +124,11 @@ ...@@ -124,11 +124,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
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<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
...@@ -137,7 +137,7 @@ ...@@ -137,7 +137,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/> <outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
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<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
...@@ -150,9 +150,8 @@ ...@@ -150,9 +150,8 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/> <outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/> <outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1364416969" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1364416940"> <transform xil_pn:end_ts="1365009357" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1365009320">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
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<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.ncd"/> <outfile xil_pn:name="conv_ttl_blo_v2.ncd"/>
...@@ -165,7 +164,7 @@ ...@@ -165,7 +164,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/> <outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
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<transform xil_pn:end_ts="1364416987" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1364416969"> <transform xil_pn:end_ts="1365009378" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1365009357">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
...@@ -179,12 +178,14 @@ ...@@ -179,12 +178,14 @@
<transform xil_pn:end_ts="1364417005" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1364416987"> <transform xil_pn:end_ts="1364417005" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1364416987">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_impact.cmd"/> <status xil_pn:value="OutOfDateForInputs"/>
<outfile xil_pn:name="_impact.log"/> <status xil_pn:value="OutOfDateForOutputs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.mcs"/> <status xil_pn:value="InputAdded"/>
<outfile xil_pn:name="conv_ttl_blo_v2.prm"/> <status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1364416969" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1364416962"> <transform xil_pn:end_ts="1365009357" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1365009346">
<status xil_pn:value="FailedRun"/> <status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/pts/syn/conv_ttl_blo_v2.xise
View file @ c782c3fc
...@@ -346,19 +346,19 @@ ...@@ -346,19 +346,19 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../top/pts_regs.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../top/pts_regs.vhd" xil_pn:type="FILE_VHDL">
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</file> </file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file> </file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file> </file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...@@ -424,7 +424,7 @@ ...@@ -424,7 +424,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...@@ -454,13 +454,13 @@ ...@@ -454,13 +454,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file> </file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file> </file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...@@ -547,7 +547,7 @@ ...@@ -547,7 +547,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file> </file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...@@ -589,7 +589,7 @@ ...@@ -589,7 +589,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...@@ -625,19 +625,19 @@ ...@@ -625,19 +625,19 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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<file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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<file xil_pn:name="../../vme64x_i2c/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../vme64x_i2c/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file> </file>
<file xil_pn:name="../../vme64x_i2c/rtl/vme64x_i2c.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../vme64x_i2c/rtl/vme64x_i2c.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
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<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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</files> </files>
......
hdl/pts/top/conv_ttl_blo_v2.ucf
View file @ c782c3fc
...@@ -260,8 +260,8 @@ NET "FPGA_GAP" IOSTANDARD = LVTTL; ...@@ -260,8 +260,8 @@ NET "FPGA_GAP" IOSTANDARD = LVTTL;
####------------------- ####-------------------
####-- Thermo for UID ####-- Thermo for UID
####------------------- ####-------------------
##NET "THERMOMETER" LOC = B1; NET "THERMOMETER" LOC = B1;
## NET "THERMOMETER" IOSTANDARD = "LVCMOS25"; NET "THERMOMETER" IOSTANDARD = LVCMOS33;
####------------------- ####-------------------
####-- DACs control ####-- DACs control
####-- ####--
......
hdl/pts/top/conv_ttl_blo_v2.vhd
View file @ c782c3fc
...@@ -106,7 +106,10 @@ entity conv_ttl_blo_v2 is ...@@ -106,7 +106,10 @@ entity conv_ttl_blo_v2 is
-- RTM identifiers, should match with the expected values -- RTM identifiers, should match with the expected values
-- TODO: add matching -- TODO: add matching
FPGA_RTMM_N : in std_logic_vector(2 downto 0); FPGA_RTMM_N : in std_logic_vector(2 downto 0);
FPGA_RTMP_N : in std_logic_vector(2 downto 0) FPGA_RTMP_N : in std_logic_vector(2 downto 0);
-- DS18B20U+ thermometer bidirectional port
THERMOMETER : inout std_logic
); );
end conv_ttl_blo_v2; end conv_ttl_blo_v2;
...@@ -126,42 +129,41 @@ architecture behav of conv_ttl_blo_v2 is ...@@ -126,42 +129,41 @@ architecture behav of conv_ttl_blo_v2 is
--============================================================================ --============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar -- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : NATURAL := 1; constant c_nr_masters : NATURAL := 1;
constant c_nr_slaves : NATURAL := 1; constant c_nr_slaves : NATURAL := 2;
----------------------------------------- -----------------------------------------
-- Memory map -- Memory map
-- * all registers are word-addressable -- * all registers are word-addressable
-- * all registers are word aligned -- * all registers are word aligned
----------------------------------------- -----------------------------------------
-- M25P32 [0200-03FF] -- PTS [0000-0004]
-- MULTIBOOT [0080-00CF] -- ONEWIRE [0008-000C]
-- I2C_SLAVE [0040-007F]
-- SR [0000-003F]
----------------------------------------- -----------------------------------------
-- slave order definitions
constant c_slv_pts_regs : natural := 0;
constant c_slv_onewire_mst : natural := 1;
-- base address definitions -- base address definitions
constant c_addr_pts_regs : t_wishbone_address := x"00000000"; constant c_addr_pts_regs : t_wishbone_address := x"00000000";
constant c_addr_i2c_bridge : t_wishbone_address := X"00000040"; constant c_addr_onewire_mst : t_wishbone_address := x"00000008";
constant c_addr_multiboot : t_wishbone_address := X"00000080";
constant c_addr_m25p32 : t_wishbone_address := X"00000200";
-- address mask definitions -- address mask definitions
-- 64 words per page: 6 + 1 bits constant c_mask_pts_regs : t_wishbone_address := x"FFFFFFF8";
constant c_mask_pts_regs : t_wishbone_address := X"FFFFFFF0"; constant c_mask_onewire_mst : t_wishbone_address := x"FFFFFFF8";
constant c_mask_i2c_bridge : t_wishbone_address := X"FFFFFFC0";
constant c_mask_multiboot : t_wishbone_address := X"FFFFFFC0";
constant c_mask_m25p32 : t_wishbone_address := X"FFFFFE00";
-- addresses constant for Wishbone crossbar -- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves - 1 downto 0) constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= ( := (
(others => c_addr_pts_regs) 0 => c_addr_pts_regs,
1 => c_addr_onewire_mst
); );
-- masks constant for Wishbone crossbar -- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves - 1 downto 0) constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= ( := (
(others => c_mask_pts_regs) 0 => c_mask_pts_regs,
1 => c_mask_onewire_mst
); );
--============================================================================ --============================================================================
...@@ -304,23 +306,28 @@ architecture behav of conv_ttl_blo_v2 is ...@@ -304,23 +306,28 @@ architecture behav of conv_ttl_blo_v2 is
signal cnt_halfsec : unsigned(25 downto 0); signal cnt_halfsec : unsigned(25 downto 0);
signal led_seq : unsigned( 4 downto 0); signal led_seq : unsigned( 4 downto 0);
-- one-wire master signals
signal owr_pwren : std_logic_vector(0 downto 0);
signal owr_en : std_logic_vector(0 downto 0);
signal owr_in : std_logic_vector(0 downto 0);
begin begin
--============================================================================ --============================================================================
-- Generate 125 MHz global signal from differential lines -- Generate 125 MHz global signal from differential lines
--============================================================================ --============================================================================
cmp_125_diff_buf: IBUFGDS cmp_125_diff_buf: IBUFGDS
generic map generic map
( (
DIFF_TERM => TRUE, DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE IBUF_LOW_PWR => TRUE
) )
port map port map
( (
I => FPGA_CLK_P, I => FPGA_CLK_P,
IB => FPGA_CLK_N, IB => FPGA_CLK_N,
O => clk_125 O => clk_125
); );
--============================================================================ --============================================================================
-- Internal and external reset generation -- Internal and external reset generation
...@@ -423,7 +430,7 @@ begin ...@@ -423,7 +430,7 @@ begin
end process p_i2c_up; end process p_i2c_up;
--============================================================================ --============================================================================
-- Output enable logic -- PTS registers
--============================================================================ --============================================================================
-- Regs to test I2C operation -- Regs to test I2C operation
cmp_pts_regs: pts_regs cmp_pts_regs: pts_regs
...@@ -431,15 +438,15 @@ begin ...@@ -431,15 +438,15 @@ begin
( (
rst_n_i => rst_n, rst_n_i => rst_n,
clk_sys_i => clk_125, clk_sys_i => clk_125,
wb_adr_i => xbar_master_out(0).adr(2 downto 2), wb_adr_i => xbar_master_out(c_slv_pts_regs).adr(2 downto 2),
wb_dat_i => xbar_master_out(0).dat, wb_dat_i => xbar_master_out(c_slv_pts_regs).dat,
wb_dat_o => xbar_master_in(0).dat, wb_dat_o => xbar_master_in(c_slv_pts_regs).dat,
wb_cyc_i => xbar_master_out(0).cyc, wb_cyc_i => xbar_master_out(c_slv_pts_regs).cyc,
wb_sel_i => xbar_master_out(0).sel, wb_sel_i => xbar_master_out(c_slv_pts_regs).sel,
wb_stb_i => xbar_master_out(0).stb, wb_stb_i => xbar_master_out(c_slv_pts_regs).stb,
wb_we_i => xbar_master_out(0).we, wb_we_i => xbar_master_out(c_slv_pts_regs).we,
wb_ack_o => xbar_master_in(0).ack, wb_ack_o => xbar_master_in(c_slv_pts_regs).ack,
wb_stall_o => xbar_master_in(0).stall, wb_stall_o => xbar_master_in(c_slv_pts_regs).stall,
-- PTS control register -- PTS control register
pts_ctrl_crrt_test_o => pts_crrt_test, pts_ctrl_crrt_test_o => pts_crrt_test,
...@@ -451,7 +458,7 @@ begin ...@@ -451,7 +458,7 @@ begin
--============================================================================ --============================================================================
-- Instantiation and connection of a Wishbone crossbar module -- Instantiation and connection of a Wishbone crossbar module
--============================================================================ --============================================================================
-- xbar_master_in(0).stall <= '0'; -- xbar_master_in(0).stall <= '0';
xbar_master_in(0).int <= '0'; xbar_master_in(0).int <= '0';
xbar_master_in(0).err <= '0'; xbar_master_in(0).err <= '0';
...@@ -620,6 +627,42 @@ begin ...@@ -620,6 +627,42 @@ begin
line_oen_o(1) => LED_CTRL1_OEN line_oen_o(1) => LED_CTRL1_OEN
); );
--============================================================================
-- One-wire master instantiation
--============================================================================
cmp_onewire_master: wb_onewire_master
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map
(
clk_sys_i => clk_125,
rst_n_i => rst_n,
wb_cyc_i => xbar_master_out(c_slv_onewire_mst).cyc,
wb_sel_i => xbar_master_out(c_slv_onewire_mst).sel,
wb_stb_i => xbar_master_out(c_slv_onewire_mst).stb,
wb_we_i => xbar_master_out(c_slv_onewire_mst).we,
wb_adr_i => xbar_master_out(c_slv_onewire_mst).adr(4 downto 2),
wb_dat_i => xbar_master_out(c_slv_onewire_mst).dat,
wb_dat_o => xbar_master_in(c_slv_onewire_mst).dat,
wb_ack_o => xbar_master_in(c_slv_onewire_mst).ack,
wb_int_o => open,
wb_stall_o => xbar_master_in(c_slv_onewire_mst).stall,
owr_pwren_o => owr_pwren,
owr_en_o => owr_en,
owr_i => owr_in
);
THERMOMETER <= '0' when (owr_en(0) = '1') else
'Z';
owr_in(0) <= THERMOMETER;
--============================================================================ --============================================================================
-- RTM detection logic -- RTM detection logic
--============================================================================ --============================================================================
......
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