HDL roadmap
The development of HDL code has been divided into functional blocks. Each functional block consist of a /rtl folder, a /test one and a documentation explaining its behaviour.
HDL Specifications
The following document establish the HDL Specifications to be followed.
User Guide
We're working in the user guide that can be found in our repo.
HDL Blocks Status
Basic functionality cores
Two kinds of repetitions are offered:
- A clocked solution which introduces a sampling jitter of 5 us: basic-trigger
- A non-clocked solution which introduces a sampling jitter of 500 ps worst-case: basic_trigger_async
It should be noted that using the non-clocked solution, it is at a expense of introducing a RC constant in the inputs to guarantee glitch-free working conditions. See issue 621 for further details. On the other hand, having a comparable solution in terms of low-jitter figure can only be achieved by using ISERDES2 in Spartan6. It should be kept in ming that this alternate solution will be power-agressive.
HDL Block | HDL name | Tested | Synthesizable |
Clocked repetition | basic_trigger | YES | YES |
Non clocked repetition | basic_trigger_async | YES | YES |
Extended functionality repetitor IP cores
HDL Block | HDL name | Tested | Synthesizable | Documented |
Pulse Trigger Control | trigger | YES | YES | YES |
I2C Slave to Wishbone Master | i2c_slave_wb_master | YES | YES | YES |
SPI for block transfers | spi_master_multifield | YES | YES | YES |
EEPROM manager | m25p32 | YES | YES | YES |
Multiboot manager | multiboot | Developing | YES | YES |
White Rabbit | wr-core | YES | YES | NO |
Bitstreams Status
Version | Functionality | Mapped | Status | Test performed |
image0 | Basic pulse repetition | YES | Working | image 0 tests |
image1 | Complete but time-tagging | YES | Under development | image 1 tests |
image2 | Basic + Firmware upgradeable via I2C + I2C reports + WR time-tagging | NO | On the way |
Carlos Gil Soriano - November 26, 2012