Second review of the architecture of the Converter from/to TTL to Blocking
Date: 20 October 2011
Present: Erik van der Bij, Carlos Gil Soriano, Matthieu Cattin, Olivier
Barriere, Emmanuel Said
The following modifications were decided after the second review of the architecture:
Architectural decisions
- Main characteristics:
- 6 channels. Every channel can be accessed via front panel or
rear panel. The front panel has one input - TTL or TTL-bar
signal level - and one output with the same type of signal as
the input -
it eases daisy-chaining. The front panel is responsible of the interconnections for daisy-chaining the pulse. In the rear panel, one channel consist of one inputTTL or Blocking signal levels - and three standard blocking outputs. - CTDAH is now White Rabbit capable for timetagging precisely the pulses.
- 6 channels. Every channel can be accessed via front panel or
rear panel. The front panel has one input - TTL or TTL-bar
signal level - and one output with the same type of signal as
the input -
- Front module:
- Three or four separate inputs with each their own, inverted output are added to the front panel to improve flexibility.
- Internal 50 ohm parallel termination is required.
- SFP connector in front panel.
- Reprogrammable Xilinx: I2C reprogramable feature is important. JTAG connector is placed in the front board rather than in the front panel -- so there is more room for the new connectors of the front panel.
- A switch to select the input level is placed in the front board.
- Another switch is selected in the front board, increasing the flexibility of the board for adding new functionalities.
- LED colour in the front panel for easing the task of recognising the board?
- Rear Transition Module RTM
- Every channel consist of one input and three outputs. The input signals should be either TTL or Standard Blocking. The output signal is always Standard Blocking.
- Internal 50 ohm parallel termination is required.
- Functionality
- Apart from the conversion, timetagging of the pulses is required.
Open questions
- P2 front-to-rear connector pinout, RJ2: EMC problems in blocking pins --spacing and grounding for signal integrity?
- Problems with power supply?
- More intuitive//self-explanatory names for the modules.
- Carlos Gil Soriano, 20 October 2011