Add granularity generic for both ports.

1a129390 · Tristan Gingold · 73878a95 · 1a129390 · 1a129390
Commit 1a129390 authored Jul 25, 2019 by Tristan Gingold
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Showing with 25 additions and 12 deletions

ddr3_ctrl.vhd hdl/rtl/ddr3_ctrl.vhd +14 -7

ddr3_ctrl_wb.vhd hdl/rtl/ddr3_ctrl_wb.vhd +11 -5

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--- a/hdl/rtl/ddr3_ctrl.vhd
+++ b/hdl/rtl/ddr3_ctrl.vhd
@@ -59,6 +59,7 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.NUMERIC_STD.all;
 --! Specific packages
+use work.wishbone_pkg.all;
 --==============================================================================
 --! Entity declaration for ddr3_ctrl
@@ -90,12 +91,16 @@ entity ddr3_ctrl is
    g_P0_DATA_PORT_SIZE  : integer := 32;
    --! Port 0 byte address width
    g_P0_BYTE_ADDR_WIDTH : integer := 30;
+    --! Port 0 address granularity
+    g_P0_ADDR_GRANULARITY : t_wishbone_address_granularity := WORD;
    --! Wishbone port 1 data mask size (8-bit granularity)
    g_P1_MASK_SIZE       : integer := 4;
    --! Wishbone port 1 data width
    g_P1_DATA_PORT_SIZE  : integer := 32;
    --! Port 1 byte address width
-    g_P1_BYTE_ADDR_WIDTH : integer := 30
+    g_P1_BYTE_ADDR_WIDTH : integer := 30;
+    --! Port 0 address granularity
+    g_P1_ADDR_GRANULARITY : t_wishbone_address_granularity := WORD
    );
  port(
@@ -333,9 +338,10 @@ begin
  ------------------------------------------------------------------------------
  cmp_ddr3_ctrl_wb_0 : entity work.ddr3_ctrl_wb
    generic map(
-      g_BYTE_ADDR_WIDTH => g_P0_BYTE_ADDR_WIDTH,
+      g_BYTE_ADDR_WIDTH  => g_P0_BYTE_ADDR_WIDTH,
-      g_MASK_SIZE       => g_P0_MASK_SIZE,
+      g_MASK_SIZE        => g_P0_MASK_SIZE,
-      g_DATA_PORT_SIZE  => g_P0_DATA_PORT_SIZE
+      g_DATA_PORT_SIZE   => g_P0_DATA_PORT_SIZE,
+      g_ADDR_GRANULARITY => g_P0_ADDR_GRANULARITY 
      )
    port map(
      rst_n_i             => wb0_rst_n_i,
@@ -380,9 +386,10 @@ begin
  ------------------------------------------------------------------------------
  cmp_ddr3_ctrl_wb_1 : entity work.ddr3_ctrl_wb
    generic map(
-      g_BYTE_ADDR_WIDTH => g_P1_BYTE_ADDR_WIDTH,
+      g_BYTE_ADDR_WIDTH  => g_P1_BYTE_ADDR_WIDTH,
-      g_MASK_SIZE       => g_P1_MASK_SIZE,
+      g_MASK_SIZE        => g_P1_MASK_SIZE,
-      g_DATA_PORT_SIZE  => g_P1_DATA_PORT_SIZE
+      g_DATA_PORT_SIZE   => g_P1_DATA_PORT_SIZE,
+      g_ADDR_GRANULARITY => g_P1_ADDR_GRANULARITY
      )
    port map(
      rst_n_i             => wb1_rst_n_i,

--- a/hdl/rtl/ddr3_ctrl_wb.vhd
+++ b/hdl/rtl/ddr3_ctrl_wb.vhd
@@ -56,6 +56,7 @@ use IEEE.NUMERIC_STD.all;
 library work;
 use work.ddr3_ctrl_pkg.all;
 use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
 --==============================================================================
 --! Entity declaration for ddr3_ctrl_wb
@@ -68,7 +69,9 @@ entity ddr3_ctrl_wb is
    --! Data mask size (8-bit granularity)
    g_MASK_SIZE       : integer := 4;
    --! Data width
-    g_DATA_PORT_SIZE  : integer := 32
+    g_DATA_PORT_SIZE  : integer := 32;
+    --! Granularity
+    g_ADDR_GRANULARITY : t_wishbone_address_granularity := WORD
    );
  port(
@@ -140,6 +143,8 @@ architecture rtl of ddr3_ctrl_wb is
  constant c_ADDR_SHIFT : integer := log2_ceil(g_DATA_PORT_SIZE/8);
+  constant ADDR_SHIFT   : std_logic_vector(c_ADDR_SHIFT-1 downto 0) := (others => '0');
  ------------------------------------------------------------------------------
  -- Signals declaration
  ------------------------------------------------------------------------------
@@ -158,7 +163,6 @@ architecture rtl of ddr3_ctrl_wb is
  signal ddr_cmd_instr     : std_logic_vector(2 downto 0);
  signal ddr_cmd_bl        : std_logic_vector(5 downto 0);
  signal ddr_cmd_byte_addr : std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
-  signal addr_shift        : std_logic_vector(c_ADDR_SHIFT-1 downto 0);
  signal ddr_wr_en         : std_logic;
  signal ddr_wr_mask       : std_logic_vector(g_MASK_SIZE - 1 downto 0);
  signal ddr_wr_data       : std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
@@ -229,7 +233,11 @@ begin
        if ((ddr_burst_cnt = 0 and wb_cyc_r_edge = '1' and wb_stb_valid = '1') or
            (ddr_burst_cnt = 1))
        then
-          ddr_cmd_byte_addr <= wb_addr_d(g_BYTE_ADDR_WIDTH-c_ADDR_SHIFT-1 downto 0) & addr_shift;
+          if g_ADDR_GRANULARITY = WORD then
+            ddr_cmd_byte_addr <= wb_addr_d(g_BYTE_ADDR_WIDTH-c_ADDR_SHIFT-1 downto 0) & addr_shift;
+          else
+            ddr_cmd_byte_addr <= wb_addr_d(g_BYTE_ADDR_WIDTH-1 downto 0);
+          end if;
          ddr_cmd_instr     <= "00" & not(wb_we_d);
        end if;
        ddr_cmd_bl <= std_logic_vector(ddr_burst_cnt - 1);
@@ -237,8 +245,6 @@ begin
    end if;
  end process p_ddr_cmd;
-  addr_shift <= (others => '0');
  -- Command enable signal generation
  p_ddr_cmd_en : process (wb_clk_i)
  begin