Skip to content

D
DDR3 controller for Spartan6
Commit 5d69a3a4 authored by mcattin's avatar mcattin
Browse files
Options

Remove IBUFG from core. Was causing error during translation, because the buffer… 

Remove IBUFG from core. Was causing error during translation, because the buffer wasn't connected to a top port. (see AR #22252).

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@99 739e5516-d4a2-47df-ba96-5610c1fa693f
parent d1ab2bbb
Hide whitespace changes
Inline Side-by-side
Showing with 24 additions and 20 deletions
hdl/spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/memc3_infrastructure.vhd
View file @ 5d69a3a4
......@@ -165,11 +165,12 @@ begin
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
--u_ibufg_sys_clk : IBUFG
-- port map (
-- I => sys_clk,
-- O => sys_clk_ibufg
-- );
sys_clk_ibufg <= sys_clk;
end generate;
--***************************************************************************
......
hdl/spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd
View file @ 5d69a3a4
......@@ -165,11 +165,12 @@ begin
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
--u_ibufg_sys_clk : IBUFG
-- port map (
-- I => sys_clk,
-- O => sys_clk_ibufg
-- );
sys_clk_ibufg <= sys_clk;
end generate;
--***************************************************************************
......
hdl/svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl/memc4_infrastructure.vhd
View file @ 5d69a3a4
......@@ -165,11 +165,12 @@ begin
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
--u_ibufg_sys_clk : IBUFG
-- port map (
-- I => sys_clk,
-- O => sys_clk_ibufg
-- );
sys_clk_ibufg <= sys_clk;
end generate;
--***************************************************************************
......
hdl/svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl/memc5_infrastructure.vhd
View file @ 5d69a3a4
......@@ -165,11 +165,12 @@ begin
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
--u_ibufg_sys_clk : IBUFG
-- port map (
-- I => sys_clk,
-- O => sys_clk_ibufg
-- );
sys_clk_ibufg <= sys_clk;
end generate;
--***************************************************************************
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment