FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xml · 490a9cf120ee2d97c034ba5df7e19cfc10d47429 · Projects / FPGA and ARM SoC FMC Carrier FASEC · Open Hardware Repository

Blame History Permalink

porting Eino's project (thus 2016.4) to Vivado 2018.1, including: · 490a9cf1
Pieter Van Trappen authored Jun 26, 2018
```
* submodule cores update
* wrpc stays the same
* set_registers.tcl script ported
```
490a9cf1

system_design_axi_uartlite_0_0.xml 65.3 KB