readme and tcl files updated

11960e62 · Pieter Van Trappen · 2a3066fe · 11960e62 · 11960e62 · 11960e62
Commit 11960e62 authored May 31, 2017 by Pieter Van Trappen
4 changed files
--- a/FASEC_prototype.srcs/tcl/set_registers.tcl
+++ b/FASEC_prototype.srcs/tcl/set_registers.tcl
@@ -2,7 +2,7 @@
 # in a VHDL file for use during synthesis
 # !! FIXME: first remove top if IP updated: $ rm modules/fasec_hwtest/top_mod.vhd.old 
 # start manually as follows:
-# cd /home/pieter/Development/projects/FIDS/FASEC_prototype; source FASEC_prototype.srcs/tcl/set_registers.tcl
+# > cd [get_property DIRECTORY [current_project]]; source FASEC_prototype.srcs/tcl/set_registers.tcl

 # xilinc tcl info:
 # each class can have many properties, to list them:
@@ -18,6 +18,7 @@ set filefilter *top_mod*
 set git {/usr/bin/git}
 set backupext .old
 set backupnm {modules/fasec_hwtest/top_mod.vhd.old}
+set backupnd {modules/fasec_hwtest}

 set projd [get_property DIRECTORY [current_project]]
 puts $projd
@@ -34,7 +35,9 @@ set dateCode [format %08X [clock seconds]]
 set gitCode [string range [exec $git log --format=%H -n 1] 0 7]

 # create backup file if it doesn't exist to preserve the DEADBEE. strings
+# file mkdir needed in case of fresh project creation after clone
 if [file exists $backupnm]==0 {
+    file mkdir $backupnd
    file copy -force $topfile $backupnm
 }


--- a/FASEC_prototype.xpr
+++ b/FASEC_prototype.xpr
@@ -10,12 +10,12 @@
    <Option Name="Part" Val="xc7z030ffg676-2"/>
    <Option Name="CompiledLibDir" Val="$PPRDIR/../../../../../../local/EDA/xilinx_simlib"/>
    <Option Name="CompiledLibDirXSim" Val=""/>
-    <Option Name="CompiledLibDirModelSim" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/modelsim"/>
-    <Option Name="CompiledLibDirQuesta" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/questa"/>
-    <Option Name="CompiledLibDirIES" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/ies"/>
-    <Option Name="CompiledLibDirVCS" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/vcs"/>
-    <Option Name="CompiledLibDirRiviera" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/riviera"/>
-    <Option Name="CompiledLibDirActivehdl" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/activehdl"/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
    <Option Name="TargetLanguage" Val="VHDL"/>
    <Option Name="BoardPart" Val=""/>
    <Option Name="ActiveSimSet" Val="sim_1"/>
@@ -53,6 +53,15 @@
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.hwdef"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design_bd.tcl"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design.hwh"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="system_design_ooc.xdc"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_2/system_design_auto_pc_2.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_1/system_design_auto_pc_1.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_0/system_design_auto_pc_0.xci"/>
        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.vhd"/>
        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci"/>
        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0.xci"/>
@@ -62,23 +71,14 @@
        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xci"/>
        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci"/>
        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.hwdef"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design.hwh"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xci"/>
        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xbar_0/system_design_xbar_0.xci"/>
        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci"/>
        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xci"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xbar_0/system_design_xbar_0.xci"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_0/system_design_auto_pc_0.xci"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_1/system_design_auto_pc_1.xci"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_2/system_design_auto_pc_2.xci"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="system_design_ooc.xdc"/>
-        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design_bd.tcl"/>
      </File>
      <File Path="$PSRCDIR/sources_1/bd/system_design/hdl/system_design_wrapper.vhd">
        <FileInfo>

--- a/README.md
+++ b/README.md
@@ -11,3 +11,13 @@ The following has been tested so far:
 * FMCs I2C bus
 * PL output LEDs
 ...
+
+The project itself is not uploaded, to recreate it after cloning the repo:
+$ git submodule init
+$ git submodule update --recursive
+$ vivado -mode batch -source syn/fasec_prototype_project-generation.tcl
+
+Now the project can be openend with Vivado. There's a hacky script to update
+some fasec_hwtest AXI4-Lite registers to include build time and commit
+number. To use, run bitstream generation as follows from the Tcl Console:
+> cd [get_property DIRECTORY [current_project]]; source FASEC_prototype.srcs/tcl/set_registers.tcl
--- a/syn/fasec_prototype_fmcs_sfp-gig-eth_xadc_dma.tcl
+++ b/syn/fasec_prototype_fmcs_sfp-gig-eth_xadc_dma.tcl
@@ -3,7 +3,7 @@
 #
 # fasec_prototype_fmcs_sfp-gig-eth_xadc_dma.tcl: Tcl script for re-creating project 'FASEC_prototype'
 #
-# Generated by Vivado on Mon Mar 27 12:53:17 CEST 2017
+# Generated by Vivado on Wed May 31 14:28:19 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016
 #
 # This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -23,13 +23,13 @@
 # 2. The following source(s) files that were local or imported into the original project.
 #    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
 #
-#    "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd"
-#    "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd"
-#    "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc"
+#    <none>
 #
 # 3. The following remote source files that were added to the original project:-
 #
-#    <none>
+#    "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd"
+#    "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd"
+#    "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc"
 #
 #*****************************************************************************************

@@ -127,20 +127,22 @@ set files [list \
 add_files -norecurse -fileset $obj $files

 # Set 'sources_1' fileset file properties for remote files
-# None
-
-# Set 'sources_1' fileset file properties for local files
-set file "system_design/system_design.bd"
+set file "$origin_dir/../FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd"
+set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 if { ![get_property "is_locked" $file_obj] } {
  set_property "generate_synth_checkpoint" "0" $file_obj
 }

-set file "hdl/system_design_wrapper.vhd"
+set file "$origin_dir/../FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd"
+set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj


+# Set 'sources_1' fileset file properties for local files
+# None
+
 # Set 'sources_1' fileset properties
 set obj [get_filesets sources_1]
 set_property "top" "system_design_wrapper" $obj
@@ -156,7 +158,8 @@ set obj [get_filesets constrs_1]
 # Add/Import constrs file and set constrs file properties
 set file "[file normalize "$origin_dir/../FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc"]"
 set file_added [add_files -norecurse -fileset $obj $file]
-set file "new/fasec_constraints_synth.xdc"
+set file "$origin_dir/../FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc"
+set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
 set_property "file_type" "XDC" $file_obj