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FPGA and ARM SoC FMC Carrier FASEC
Commit 12b9ef23 authored by Pieter Van Trappen's avatar Pieter Van Trappen
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FMC1_GP1_i now connected to wrpc pps instead of dmtd; after synthesis

parent d5590770
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FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
View file @ 12b9ef23
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Fri May 12 15:46:39 2017
--Date : Mon May 15 15:45:08 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
--Command : generate_target system_design.bd
--Design : system_design
......@@ -4528,7 +4528,6 @@ architecture STRUCTURE of system_design is
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_wrc_1p_kintex7_0_62M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_wrc_1p_kintex7_0_62M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal wrc_1p_kintex7_0_clk_dmtd_o : STD_LOGIC;
signal wrc_1p_kintex7_0_clk_ref_o : STD_LOGIC;
signal wrc_1p_kintex7_0_clk_rx_rbclk_o : STD_LOGIC;
signal wrc_1p_kintex7_0_dac_cs1_n_o : STD_LOGIC;
......@@ -4548,6 +4547,7 @@ architecture STRUCTURE of system_design is
signal wrc_1p_kintex7_0_gtp_wr_TXP : STD_LOGIC;
signal wrc_1p_kintex7_0_gtp_wr_TX_DISABLE : STD_LOGIC;
signal wrc_1p_kintex7_0_gtp_wr_TX_FAULT : STD_LOGIC;
signal wrc_1p_kintex7_0_pps_o : STD_LOGIC;
signal wrc_1p_kintex7_0_s00_axi_aclk_o : STD_LOGIC;
signal wrc_1p_kintex7_0_uart_txd_o : STD_LOGIC;
signal xadc_axis_fifo_adapter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
......@@ -4596,9 +4596,9 @@ architecture STRUCTURE of system_design is
signal NLW_rst_wrc_1p_kintex7_0_62M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_wrc_1p_kintex7_0_62M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_wrc_1p_kintex7_0_axi_int_o_UNCONNECTED : STD_LOGIC;
signal NLW_wrc_1p_kintex7_0_clk_dmtd_o_UNCONNECTED : STD_LOGIC;
signal NLW_wrc_1p_kintex7_0_gtp0_wrmode_led_o_UNCONNECTED : STD_LOGIC;
signal NLW_wrc_1p_kintex7_0_pps_ctrl_o_UNCONNECTED : STD_LOGIC;
signal NLW_wrc_1p_kintex7_0_pps_o_UNCONNECTED : STD_LOGIC;
signal NLW_wrc_1p_kintex7_0_term_en_o_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_axis_fifo_adapter_0_INTR_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_axis_fifo_adapter_0_M_AXIS_TID_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
......@@ -4903,7 +4903,7 @@ fasec_hwtest_0: component system_design_fasec_hwtest_0_0
FMC1_CLK0M2C_N_i => FMC1_CLK0M2C_N_i_1,
FMC1_CLK0M2C_P_i => FMC1_CLK0M2C_P_i_1,
FMC1_GP0_i => wrc_1p_kintex7_0_clk_ref_o,
FMC1_GP1_i => wrc_1p_kintex7_0_clk_dmtd_o,
FMC1_GP1_i => wrc_1p_kintex7_0_pps_o,
FMC1_GP2_i => wrc_1p_kintex7_0_clk_rx_rbclk_o,
FMC1_GP3_b => NLW_fasec_hwtest_0_FMC1_GP3_b_UNCONNECTED,
FMC1_LA_N_b(33 downto 0) => FMC1_LA_N_b(33 downto 0),
......@@ -5342,7 +5342,7 @@ wrc_1p_kintex7_0: component system_design_wrc_1p_kintex7_0_0
axi_int_o => NLW_wrc_1p_kintex7_0_axi_int_o_UNCONNECTED,
button_rst_n_i => pb_gp_i_1,
clk_20m_vcxo_i => clk_25m_vcxo_i_1,
clk_dmtd_o => wrc_1p_kintex7_0_clk_dmtd_o,
clk_dmtd_o => NLW_wrc_1p_kintex7_0_clk_dmtd_o_UNCONNECTED,
clk_ref_o => wrc_1p_kintex7_0_clk_ref_o,
clk_rx_rbclk_o => wrc_1p_kintex7_0_clk_rx_rbclk_o,
dac_cs1_n_o => wrc_1p_kintex7_0_dac_cs1_n_o,
......@@ -5371,7 +5371,7 @@ wrc_1p_kintex7_0: component system_design_wrc_1p_kintex7_0_0
gtp_dedicated_clk_p_i => gtp_dedicated_clk_p_i_1,
pps_ctrl_o => NLW_wrc_1p_kintex7_0_pps_ctrl_o_UNCONNECTED,
pps_i => xlconstant_7_dout(0),
pps_o => NLW_wrc_1p_kintex7_0_pps_o_UNCONNECTED,
pps_o => wrc_1p_kintex7_0_pps_o,
s00_axi_aclk_o => wrc_1p_kintex7_0_s00_axi_aclk_o,
s00_axi_araddr(31 downto 0) => axi_interconnect_1_M00_AXI_ARADDR(31 downto 0),
s00_axi_aresetn => rst_wrc_1p_kintex7_0_62M_peripheral_aresetn(0),
......
FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
View file @ 12b9ef23
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Fri May 12 15:46:39 2017
--Date : Mon May 15 15:45:08 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
--Command : generate_target system_design_wrapper.bd
--Design : system_design_wrapper
......
FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
View file @ 12b9ef23
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri May 12 15:46:41 2017" VIVADOVERSION="2016.2">
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Mon May 15 15:45:10 2017" VIVADOVERSION="2016.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z030" NAME="system_design" PACKAGE="ffg676" SPEEDGRADE="-2"/>
......@@ -3803,9 +3803,9 @@
<CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="clk_ref_o"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="FMC1_GP1_i" SIGIS="undef" SIGNAME="wrc_1p_kintex7_0_clk_dmtd_o">
<PORT DIR="I" NAME="FMC1_GP1_i" SIGIS="undef" SIGNAME="wrc_1p_kintex7_0_pps_o">
<CONNECTIONS>
<CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="clk_dmtd_o"/>
<CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="pps_o"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="FMC1_GP2_i" SIGIS="undef" SIGNAME="wrc_1p_kintex7_0_clk_rx_rbclk_o">
......@@ -7519,11 +7519,7 @@
<CONNECTION INSTANCE="External_Ports" PORT="gtp_dedicated_clk_n_i"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="clk_dmtd_o" SIGIS="undef" SIGNAME="wrc_1p_kintex7_0_clk_dmtd_o">
<CONNECTIONS>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="FMC1_GP1_i"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="clk_dmtd_o" SIGIS="undef"/>
<PORT DIR="O" NAME="clk_ref_o" SIGIS="undef" SIGNAME="wrc_1p_kintex7_0_clk_ref_o">
<CONNECTIONS>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="FMC1_GP0_i"/>
......@@ -7627,7 +7623,11 @@
</PORT>
<PORT DIR="O" NAME="pps_ctrl_o" SIGIS="undef"/>
<PORT DIR="O" NAME="term_en_o" SIGIS="undef"/>
<PORT DIR="O" NAME="pps_o" SIGIS="undef"/>
<PORT DIR="O" NAME="pps_o" SIGIS="undef" SIGNAME="wrc_1p_kintex7_0_pps_o">
<CONNECTIONS>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="FMC1_GP1_i"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="axi_int_o" SIGIS="undef"/>
<PORT CLKFREQUENCY="62500000" DIR="O" NAME="s00_axi_aclk_o" SIGIS="clk" SIGNAME="wrc_1p_kintex7_0_s00_axi_aclk_o">
<CONNECTIONS>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
View file @ 12b9ef23
......@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:40 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:09 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:40 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:09 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:40 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:09 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:40 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:09 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:40 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:09 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
View file @ 12b9ef23
......@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:40 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:09 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:41 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:09 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:41 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:09 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:40 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:09 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:41 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:09 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
View file @ 12b9ef23
......@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:40 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:09 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:41 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:10 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:41 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:10 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:40 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:09 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri May 12 13:46:41 UTC 2017</spirit:value>
<spirit:value>Mon May 15 13:45:10 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_4/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
View file @ 12b9ef23
......@@ -294,8 +294,8 @@ begin
s_data(c_FASEC_BASE+1) <= resize(unsigned(s_ins), g_S00_AXI_DATA_WIDTH);
s_data(c_FASEC_BASE+2) <= resize(unsigned(gem_status_vector_i), g_S00_AXI_DATA_WIDTH);
-- s_data(c_FASEC_BASE+3).data used in p_fasec_dio
s_data(c_FASEC_BASE+6) <= x"5915BD9E"; -- tcl-script will put unix build time
s_data(c_FASEC_BASE+7) <= x"48a224f0"; -- tcl-script will put git commit id
s_data(c_FASEC_BASE+6) <= x"5919B0E0"; -- tcl-script will put unix build time
s_data(c_FASEC_BASE+7) <= x"d5590770"; -- tcl-script will put git commit id
-- copy in rw data, 'for generate' only possible with constants!
gen_data_readwrite : for i in 0 to c_MEMMAX-1 generate
gen_fasec : if c_FASECMEM(i).ro = '0' generate
......
FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
View file @ 12b9ef23
......@@ -2,9 +2,9 @@
<Root MajorVersion="0" MinorVersion="33">
<CompositeFile CompositeFileTopName="system_design" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1494855746"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1494855746"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1494855746"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1494855914"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1494855914"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1494855914"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0"/>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ui/bd_7f01d80e.ui
View file @ 12b9ef23
......@@ -76,7 +76,8 @@ preplace netloc fasec_hwtest_0_dig_outs_i 1 9 1 NJ
preplace netloc gtp_dedicated_clk_n_i_1 1 0 9 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ
preplace netloc wrc_1p_kintex7_0_dac_din_o 1 9 1 NJ
preplace netloc gtp_dedicated_clk_p_i_1 1 0 9 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ
preplace netloc wrc_1p_kintex7_0_clk_rx_rbclk_o 1 8 2 3030 1190 3390
preplace netloc wrc_1p_kintex7_0_clk_rx_rbclk_o 1 8 2 3040 1180 3390
preplace netloc wrc_1p_kintex7_0_pps_o 1 8 2 3020 1200 3410
preplace netloc axi_uartlite_0_tx 1 3 7 NJ 600 NJ 600 NJ 600 NJ 600 NJ 600 NJ 600 3430
preplace netloc dig_in3_n_i_1 1 0 9 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ
preplace netloc FMC1_PRSNTM2C_n_i_1 1 0 9 NJ 660 NJ 660 NJ 290 NJ 220 NJ 220 NJ 230 NJ 230 NJ 230 NJ
......@@ -103,7 +104,7 @@ preplace netloc processing_system7_0_axi_periph_M02_AXI 1 2 7 NJ 280 NJ 280 NJ 2
preplace netloc xadc_axis_fifo_adapter_0_M_AXIS 1 4 1 1320
preplace netloc processing_system7_0_axi_periph_M07_AXI 1 2 1 700
preplace netloc fasec_hwtest_0_intr_led_o 1 5 5 1730 590 NJ 590 NJ 570 NJ 570 3440
preplace netloc wrc_1p_kintex7_0_gtp0_synced_led_o 1 8 2 3020 580 3480
preplace netloc wrc_1p_kintex7_0_gtp0_synced_led_o 1 8 2 3030 580 3480
preplace netloc fasec_hwtest_0_FMC2_CLK0C2M_N_o 1 9 1 NJ
preplace netloc rst_wrc_1p_kintex7_0_62M_peripheral_aresetn 1 7 2 2520 660 2910
preplace netloc clk_25m_vcxo_i_1 1 0 9 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 2900
......@@ -117,7 +118,6 @@ preplace netloc fasec_hwtest_0_watchdog_pl_o 1 9 1 NJ
preplace netloc processing_system7_0_axi_periph_M01_AXI 1 2 1 730
preplace netloc fasec_hwtest_0_dig_out5_n 1 9 1 NJ
preplace netloc FMC1_CLK0M2C_P_i_1 1 0 9 NJ 920 NJ 920 NJ 920 NJ 920 NJ 920 NJ 920 NJ 920 NJ 920 NJ
preplace netloc wrc_1p_kintex7_0_clk_dmtd_o 1 8 2 3040 1170 3410
preplace netloc Vaux0_1 1 0 3 NJ 360 NJ 540 NJ
preplace netloc Net 1 9 1 NJ
preplace netloc Net10 1 9 1 NJ
......@@ -134,7 +134,7 @@ preplace netloc fasec_hwtest_0_led_line_en_pl_o 1 9 1 NJ
preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 2070 850 2550 620 NJ 620 3470
preplace netloc Net4 1 9 1 NJ
preplace netloc Vaux8_1 1 0 3 NJ 590 NJ 590 NJ
preplace netloc wrc_1p_kintex7_0_gtp0_activity_led_o 1 8 2 3010 1200 3380
preplace netloc wrc_1p_kintex7_0_gtp0_activity_led_o 1 8 2 3010 1190 3380
preplace netloc Net5 1 9 1 NJ
preplace netloc xadc_wiz_0_ip2intc_irpt 1 3 3 1060 230 NJ 230 NJ
preplace netloc Net6 1 9 1 NJ
......@@ -144,7 +144,7 @@ preplace netloc dig_in2_i_1 1 0 9 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 102
preplace netloc axi_uartlite_0_interrupt 1 3 3 1060 590 NJ 460 NJ
preplace netloc Vaux10_1 1 0 3 NJ 630 NJ 630 NJ
preplace netloc processing_system7_0_M_AXI_GP0 1 1 7 400 20 NJ 20 NJ 20 NJ 20 NJ 240 NJ 240 2490
preplace netloc wrc_1p_kintex7_0_clk_ref_o 1 8 2 3020 1180 3400
preplace netloc wrc_1p_kintex7_0_clk_ref_o 1 8 2 3030 1170 3400
preplace netloc Vaux1_1 1 0 3 NJ 380 NJ 550 NJ
preplace netloc Vaux9_1 1 0 3 NJ 610 NJ 610 NJ
preplace netloc axi_dma_0_s2mm_introut 1 5 1 1650
......
FASEC_prototype.xpr
View file @ 12b9ef23
......@@ -57,7 +57,6 @@
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.vhd"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.hwdef"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci"/>
......@@ -66,7 +65,10 @@
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xbar_0/system_design_xbar_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="system_design_ooc.xdc"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_2/system_design_auto_pc_2.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design_bd.tcl"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.hwdef"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design.hwh"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci"/>
......@@ -75,10 +77,8 @@
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_2/system_design_auto_pc_2.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="system_design_ooc.xdc"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_0/system_design_auto_pc_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_1/system_design_auto_pc_1.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_0/system_design_auto_pc_0.xci"/>
</File>
<File Path="$PSRCDIR/sources_1/bd/system_design/hdl/system_design_wrapper.vhd">
<FileInfo>
......
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