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FMC ADC 200k 16b 11cha
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Cycle Analytics
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FMC ADC 200k 16b 11cha
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No lvds signalling for clk_m2c pins
#14
· opened
Jul 19, 2011
by
Ross Millar
bug
CLOSED
1
updated
Feb 12, 2019
clocks from mezzanine to carrier not used in ascending order
#13
· opened
Jul 19, 2011
by
Ross Millar
bug
CLOSED
1
updated
Feb 12, 2019
undriven clock lines should be connected to differential logic '0'
#12
· opened
Jul 19, 2011
by
Ross Millar
bug
CLOSED
0
updated
Feb 12, 2019
Propogation delay of buffer in feedback loop of PLL
#11
· opened
Jul 27, 2011
by
Ross Millar
bug
0
updated
Feb 12, 2019
Schematics need clean-up and pass via design office
#9
· opened
Aug 31, 2011
by
Erik van der Bij
bug
0
updated
Feb 12, 2019
Ground 4 inner shield lines on connector
#8
· opened
Aug 31, 2011
by
Erik van der Bij
bug
CLOSED
1
updated
Feb 12, 2019
Camera Link connector should touch front-panel, opening for screws
#7
· opened
Oct 03, 2011
by
Erik van der Bij
bug
0
updated
Feb 12, 2019
ADC problem observed - CS to valid data time extremely high.
#3
· opened
Dec 19, 2011
by
Ross Millar
bug
0
updated
Feb 12, 2019
SPI master and AD5662BRMZ-1 DAC bug
#2
· opened
Dec 19, 2011
by
Ross Millar
bug
0
updated
Feb 12, 2019