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FMC ADC 100M 14b 4cha - Gateware
Commit 14262933 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: adjusted timetag core to WR time interface format (40bit TAI + 28bit clock ticks)

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doc/manual/timetag_core_regs.tex
View file @ 14262933
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hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 14262933
......@@ -9,7 +9,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-24
-- Last update: 2016-04-19
-- Last update: 2016-06-08
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: FMC ADC 100Ms/s core.
......@@ -1357,8 +1357,9 @@ begin
trig_tag_done <= acq_in_trig_tag and acq_in_trig_tag_d;
trig_tag_data <= trigger_tag_i.fine & trigger_tag_i.coarse when trig_tag_done = '1' else
trigger_tag_i.seconds & trigger_tag_i.meta;
-- keep compatibility with trig_tag_data order prior to 5.0 release
trig_tag_data <= X"000000000" & trigger_tag_i.coarse when trig_tag_done = '1' else
trigger_tag_i.seconds(31 downto 0) & X"000000" & trigger_tag_i.seconds(39 downto 32);
------------------------------------------------------------------------------
-- Dual DPRAM buffers for multi-shots acquisition
......
hdl/adc/rtl/fmc_adc_mezzanine.vhd
View file @ 14262933
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- FMC ADC mezzanine
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: fmc_adc_mezzanine (fmc_adc_mezzanine.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 07-05-2013
--
-- description: The FMC ADC mezzanine is wrapper around the fmc-adc-100ms core and
-- the other wishbone slaves connected to a FMC ADC mezzanine.
--
-- dependencies:
--
-- references:
--
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : FMC ADC mezzanine
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : fmc_adc_mezzanine.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-05-07
-- Last update: 2016-06-08
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: The FMC ADC mezzanine is wrapper around the fmc-adc-100ms core
-- and the other wishbone slaves connected to a FMC ADC mezzanine.
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
......@@ -29,11 +27,11 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see git log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2013-05-07 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -612,9 +610,11 @@ begin
acq_stop_p_i => acq_stop_p,
acq_end_p_i => acq_end_p,
wr_enabled_i => '0',
trig_tag_o => trigger_tag,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(5 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TIMETAG).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TIMETAG).cyc,
......
hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
View file @ 14262933
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Timetag core package
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: timetag_core_pkg.vhd (timetag_core_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 05-07-2013
--
-- version: 1.0
--
-- description: Package for timetag core
--
-- dependencies:
--
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : Timetag core package
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : timetag_core_pkg.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-05
-- Last update: 2016-06-08
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for timetag core
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
......@@ -28,11 +26,11 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2013-07-05 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -48,47 +46,35 @@ package timetag_core_pkg is
-- Types declaration
------------------------------------------------------------------------------
type t_timetag is record
meta : std_logic_vector(31 downto 0);
seconds : std_logic_vector(31 downto 0);
coarse : std_logic_vector(31 downto 0);
fine : std_logic_vector(31 downto 0);
seconds : std_logic_vector(39 downto 0);
coarse : std_logic_vector(27 downto 0);
end record t_timetag;
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component timetag_core
port (
-- Clock, reset
clk_i : in std_logic; -- Must be 125MHz
rst_n_i : in std_logic;
-- Input pulses to time-tag
trigger_p_i : in std_logic;
acq_start_p_i : in std_logic;
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
-- Trigger time-tag output
trig_tag_o : out t_timetag;
-- Wishbone interface
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end component timetag_core;
component timetag_core is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
trigger_p_i : in std_logic;
acq_start_p_i : in std_logic;
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
wr_enabled_i : in std_logic;
trig_tag_o : out t_timetag;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component timetag_core;
end timetag_core_pkg;
package body timetag_core_pkg is
end timetag_core_pkg;
hdl/ip_cores/timetag_core/wb_gen/Makefile
View file @ 14262933
WBGEN2=~/projects/wbgen2/wbgen2
WBGEN2=$(shell which wbgen2)
RTL=../rtl/
TEX=../../../../doc/manual/
......
hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.h
View file @ 14262933
......@@ -3,7 +3,7 @@
* File : timetag_core_regs.h
* Author : auto-generated by wbgen2 from timetag_core_regs.wb
* Created : Thu Jul 4 18:04:57 2013
* Created : Wed Jun 8 10:54:43 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
......@@ -31,79 +31,67 @@
#endif
/* definitions for register: Timetag seconds register */
/* definitions for register: Timetag seconds register (upper) */
/* definitions for register: Timetag seconds register (lower) */
/* definitions for register: Timetag coarse time register, system clock ticks (125MHz) */
/* definitions for register: Trigger time-tag metadata register */
/* definitions for register: Trigger time-tag seconds register (upper) */
/* definitions for register: Trigger time-tag seconds register */
/* definitions for register: Trigger time-tag seconds register (lower) */
/* definitions for register: Trigger time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Trigger time-tag fine time register, always 0 (used for time-tag format compatibility) */
/* definitions for register: Acquisition start time-tag metadata register */
/* definitions for register: Acquisition start time-tag seconds register (upper) */
/* definitions for register: Acquisition start time-tag seconds register */
/* definitions for register: Acquisition start time-tag seconds register (lower) */
/* definitions for register: Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility) */
/* definitions for register: Acquisition stop time-tag metadata register */
/* definitions for register: Acquisition stop time-tag seconds register (upper) */
/* definitions for register: Acquisition stop time-tag seconds register */
/* definitions for register: Acquisition stop time-tag seconds register (lower) */
/* definitions for register: Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility) */
/* definitions for register: Acquisition end time-tag seconds register (upper) */
/* definitions for register: Acquisition end time-tag metadata register */
/* definitions for register: Acquisition end time-tag seconds register */
/* definitions for register: Acquisition end time-tag seconds register (lower) */
/* definitions for register: Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility) */
PACKED struct TIMETAG_CORE_WB {
/* [0x0]: REG Timetag seconds register */
uint32_t SECONDS;
/* [0x4]: REG Timetag coarse time register, system clock ticks (125MHz) */
/* [0x0]: REG Timetag seconds register (upper) */
uint32_t SECONDS_UPPER;
/* [0x4]: REG Timetag seconds register (lower) */
uint32_t SECONDS_LOWER;
/* [0x8]: REG Timetag coarse time register, system clock ticks (125MHz) */
uint32_t COARSE;
/* [0x8]: REG Trigger time-tag metadata register */
uint32_t TRIG_TAG_META;
/* [0xc]: REG Trigger time-tag seconds register */
uint32_t TRIG_TAG_SECONDS;
/* [0x10]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
/* [0xc]: REG Trigger time-tag seconds register (upper) */
uint32_t TRIG_TAG_SECONDS_UPPER;
/* [0x10]: REG Trigger time-tag seconds register (lower) */
uint32_t TRIG_TAG_SECONDS_LOWER;
/* [0x14]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
uint32_t TRIG_TAG_COARSE;
/* [0x14]: REG Trigger time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t TRIG_TAG_FINE;
/* [0x18]: REG Acquisition start time-tag metadata register */
uint32_t ACQ_START_TAG_META;
/* [0x1c]: REG Acquisition start time-tag seconds register */
uint32_t ACQ_START_TAG_SECONDS;
/* [0x18]: REG Acquisition start time-tag seconds register (upper) */
uint32_t ACQ_START_TAG_SECONDS_UPPER;
/* [0x1c]: REG Acquisition start time-tag seconds register (lower) */
uint32_t ACQ_START_TAG_SECONDS_LOWER;
/* [0x20]: REG Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_START_TAG_COARSE;
/* [0x24]: REG Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_START_TAG_FINE;
/* [0x28]: REG Acquisition stop time-tag metadata register */
uint32_t ACQ_STOP_TAG_META;
/* [0x2c]: REG Acquisition stop time-tag seconds register */
uint32_t ACQ_STOP_TAG_SECONDS;
/* [0x30]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
/* [0x24]: REG Acquisition stop time-tag seconds register (upper) */
uint32_t ACQ_STOP_TAG_SECONDS_UPPER;
/* [0x28]: REG Acquisition stop time-tag seconds register (lower) */
uint32_t ACQ_STOP_TAG_SECONDS_LOWER;
/* [0x2c]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_STOP_TAG_COARSE;
/* [0x34]: REG Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_STOP_TAG_FINE;
/* [0x38]: REG Acquisition end time-tag metadata register */
uint32_t ACQ_END_TAG_META;
/* [0x3c]: REG Acquisition end time-tag seconds register */
uint32_t ACQ_END_TAG_SECONDS;
/* [0x40]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
/* [0x30]: REG Acquisition end time-tag seconds register (upper) */
uint32_t ACQ_END_TAG_SECONDS_UPPER;
/* [0x34]: REG Acquisition end time-tag seconds register (lower) */
uint32_t ACQ_END_TAG_SECONDS_LOWER;
/* [0x38]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_END_TAG_COARSE;
/* [0x44]: REG Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_END_TAG_FINE;
};
#endif
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