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FMC ADC 100M 14b 4cha - Gateware
Commit 3cc58f1f authored by Matthieu Cattin's avatar Matthieu Cattin
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syn: Firmware release 1.1 

- Reports after synthesis and place+route.
- sdb meta-info update in (sdb_meta_pkg.vhd).
parent 9c86f458
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hdl/spec/rtl/sdb_meta_pkg.vhd
View file @ 3cc58f1f
...@@ -53,14 +53,14 @@ package sdb_meta_pkg is ...@@ -53,14 +53,14 @@ package sdb_meta_pkg is
-- Top module name (string, 16 char) -- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_adc", syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char) -- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32 -- git log -1 --format="%H" | cut -c1-320
syn_commit_id => "baa41197a02acc5cbdfbc5c893849b40", syn_commit_id => "d8644900e0d9b8544a5e20da9d0567dd",
-- Synthesis tool name (string, 8 char) -- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ", syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit) -- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133", syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit) -- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20130312", syn_date => x"20130328",
-- Synthesised by (string, 15 char) -- Synthesised by (string, 15 char)
syn_username => "mcattin "); syn_username => "mcattin ");
...@@ -69,8 +69,8 @@ package sdb_meta_pkg is ...@@ -69,8 +69,8 @@ package sdb_meta_pkg is
product => ( product => (
vendor_id => x"000000000000CE42", -- CERN vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8 device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00010000", -- bcd encoded, [31:16] = major, [15:0] = minor version => x"00010001", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130312", -- yyyymmdd date => x"20130328", -- yyyymmdd
name => "spec_fmcadc100m14b ")); name => "spec_fmcadc100m14b "));
......
hdl/spec/syn/spec_fmc_adc_100Ms.xise
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hdl/spec/syn/spec_top_fmc_adc_100Ms.par
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hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
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hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
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hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
View file @ 3cc58f1f
...@@ -11,7 +11,7 @@ Target Device : xc6slx45t ...@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484 Target Package : fgg484
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $ Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Mar 12 08:37:23 2013 Mapped Date : Thu Mar 28 12:22:38 2013
Design Summary Design Summary
-------------- --------------
...@@ -23,11 +23,11 @@ Slice Logic Utilization: ...@@ -23,11 +23,11 @@ Slice Logic Utilization:
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 5,481 out of 27,288 20% Number of Slice LUTs: 5,552 out of 27,288 20%
Number used as logic: 5,116 out of 27,288 18% Number used as logic: 5,118 out of 27,288 18%
Number using O6 output only: 3,207 Number using O6 output only: 3,207
Number using O5 output only: 278 Number using O5 output only: 279
Number using O5 and O6: 1,631 Number using O5 and O6: 1,632
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1% Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0 Number used as Dual Port RAM: 0
...@@ -36,18 +36,18 @@ Slice Logic Utilization: ...@@ -36,18 +36,18 @@ Slice Logic Utilization:
Number using O6 output only: 2 Number using O6 output only: 2
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 363 Number used exclusively as route-thrus: 432
Number with same-slice register load: 351 Number with same-slice register load: 420
Number with same-slice carry load: 12 Number with same-slice carry load: 12
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 2,465 out of 6,822 36% Number of occupied Slices: 2,433 out of 6,822 35%
Nummber of MUXCYs used: 1,456 out of 13,644 10% Nummber of MUXCYs used: 1,456 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,735 Number of LUT Flip Flop pairs used: 7,634
Number with an unused Flip Flop: 1,738 out of 7,735 22% Number with an unused Flip Flop: 1,720 out of 7,634 22%
Number with an unused LUT: 2,254 out of 7,735 29% Number with an unused LUT: 2,082 out of 7,634 27%
Number of fully used LUT-FF pairs: 3,743 out of 7,735 48% Number of fully used LUT-FF pairs: 3,832 out of 7,634 50%
Number of unique control sets: 261 Number of unique control sets: 261
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 678 out of 54,576 1% to control set restrictions: 678 out of 54,576 1%
...@@ -100,11 +100,11 @@ Specific Feature Utilization: ...@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.78 Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 409 MB Peak Memory Usage: 409 MB
Total REAL time to MAP completion: 4 mins 37 secs Total REAL time to MAP completion: 4 mins 25 secs
Total CPU time to MAP completion (all processors): 4 mins 37 secs Total CPU time to MAP completion (all processors): 4 mins 24 secs
Table of Contents Table of Contents
----------------- -----------------
...@@ -164,8 +164,8 @@ INFO:LIT:243 - Logical network ...@@ -164,8 +164,8 @@ INFO:LIT:243 - Logical network
_infrastructure_inst/rst0_sync_r<24> has no load. _infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 8 more times for the following INFO:LIT:395 - The above info message is repeated 8 more times for the following
(max. 5 shown): (max. 5 shown):
N786, N794,
N788, N796,
aux_buttons_i<1>_IBUF, aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF, aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF P_WR_REQ<1>_IBUF
......
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