Change end of acquisition interrupt generation.

Now the interrupt is generated when the DDR interface write FIFO is empty. This is to avoid read request from the host before all data are written to the DDR memory. Add synthesis, p&r and timing reports. Remove generated simulation files from repo. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@123 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

Change end of acquisition interrupt generation.
Now the interrupt is generated when the DDR interface write FIFO is empty. This is to avoid read request from the host before all data are written to the DDR memory. Add synthesis, p&r and timing reports. Remove generated simulation files from repo. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@123 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
468ef662 · mcattin · 990cc919 · 468ef662 · 990cc919 · 990cc919
Commit 468ef662 authored Jul 09, 2012 by mcattin
13 changed files
--- a/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+++ b/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
@@ -432,11 +432,16 @@ architecture rtl of spec_top_fmc_adc_100Ms is
  signal wb_ddr_stall : std_logic;

  -- Interrupts stuff
-  signal dma_irq           : std_logic_vector(1 downto 0);
-  signal dma_irq_p         : std_logic_vector(1 downto 0);
-  signal irq_sources       : std_logic_vector(31 downto 0);
-  signal irq_to_gn4124     : std_logic;
-  signal irq_sources_2_led : std_logic_vector(1 downto 0);
+  signal dma_irq             : std_logic_vector(1 downto 0);
+  signal dma_irq_p           : std_logic_vector(1 downto 0);
+  signal irq_sources         : std_logic_vector(31 downto 0);
+  signal irq_to_gn4124       : std_logic;
+  signal irq_sources_2_led   : std_logic_vector(1 downto 0);
+  signal ddr_wr_fifo_empty   : std_logic;
+  signal ddr_wr_fifo_empty_d : std_logic;
+  signal ddr_wr_fifo_empty_p : std_logic;
+  signal acq_end_irq_p       : std_logic;
+  signal acq_end             : std_logic;

  -- Mezzanine I2C for Si570
  signal si570_scl_in   : std_logic;
@@ -844,11 +849,41 @@ begin
  wb_stall(c_CSR_WB_IRQ_CTRL) <= '0';

  -- IRQ sources
+  --   0    -> End of DMA transfer
+  --   1    -> DMA transfer error
+  --   2    -> Trigger
+  --   3    -> End of acquisition (data written to DDR)
+  --   4-31 -> Unused
  irq_sources(1 downto 0)  <= dma_irq;
  irq_sources(2)           <= trigger_p;
-  irq_sources(3)           <= acq_end_p;
+  irq_sources(3)           <= acq_end_irq_p;
  irq_sources(31 downto 4) <= (others => '0');

+  -- End of acquisition interrupt generation
+  p_ddr_wr_fifo_empty : process (sys_clk_125)
+  begin
+    if rising_edge(sys_clk_125) then
+      ddr_wr_fifo_empty_d <= ddr_wr_fifo_empty;
+    end if;
+  end process p_ddr_wr_fifo_empty;
+
+  ddr_wr_fifo_empty_p <= ddr_wr_fifo_empty and not(ddr_wr_fifo_empty_d);
+
+  p_acq_end : process (sys_clk_125)
+  begin
+    if rising_edge(sys_clk_125) then
+      if sys_rst_n = '0' then
+        acq_end <= '0';
+      elsif acq_end_p = '1' then
+        acq_end <= '1';
+      elsif ddr_wr_fifo_empty_p = '1' then
+        acq_end <= '0';
+      end if;
+    end if;
+  end process p_acq_end;
+
+  acq_end_irq_p <= ddr_wr_fifo_empty_p and acq_end;
+
  -- just forward irq pulses for test
  --irq_to_gn4124 <= dma_irq(1) or dma_irq(0);

@@ -1148,6 +1183,19 @@ begin
      wb0_ack_o   => wb_ddr_ack,
      wb0_stall_o => wb_ddr_stall,

+      p0_cmd_empty_o   => open,
+      p0_cmd_full_o    => open,
+      p0_rd_full_o     => open,
+      p0_rd_empty_o    => open,
+      p0_rd_count_o    => open,
+      p0_rd_overflow_o => open,
+      p0_rd_error_o    => open,
+      p0_wr_full_o     => open,
+      p0_wr_empty_o    => ddr_wr_fifo_empty,
+      p0_wr_count_o    => open,
+      p0_wr_underrun_o => open,
+      p0_wr_error_o    => open,
+
      wb1_clk_i   => sys_clk_125,
      wb1_sel_i   => wb_dma_sel,
      wb1_cyc_i   => wb_dma_cyc,
@@ -1157,7 +1205,22 @@ begin
      wb1_data_i  => wb_dma_dat_o,
      wb1_data_o  => wb_dma_dat_i,
      wb1_ack_o   => wb_dma_ack,
-      wb1_stall_o => wb_dma_stall);
+      wb1_stall_o => wb_dma_stall,
+
+      p1_cmd_empty_o   => open,
+      p1_cmd_full_o    => open,
+      p1_rd_full_o     => open,
+      p1_rd_empty_o    => open,
+      p1_rd_count_o    => open,
+      p1_rd_overflow_o => open,
+      p1_rd_error_o    => open,
+      p1_wr_full_o     => open,
+      p1_wr_empty_o    => open,
+      p1_wr_count_o    => open,
+      p1_wr_underrun_o => open,
+      p1_wr_error_o    => open
+
+      );

  ddr3_calib_done <= ddr3_status(0);


--- a/hdl/spec/sim/fifo_generator_v6_1/.fifo_generator_v6_1
+++ b/hdl/spec/sim/fifo_generator_v6_1/.fifo_generator_v6_1
--- a/hdl/spec/sim/fifo_generator_v6_1/_info
+++ b/hdl/spec/sim/fifo_generator_v6_1/_info
-m255
-K3
-13
-cModel Technology
-Z0 d/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/sim
-Exilinx_dummy_sim
-w1320743602
-Z1 d/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/sim
-8../ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd
-F../ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd
-l0
-L1
-VKd8^[`j@TZDeV[[hfDI:J0
-!s100 nF<;LZ6J0iDiIE_]ATjaA3
-Z2 OE;C;6.6e_1;45
-32
-o-quiet -work fifo_generator_v6_1
-Z3 tExplicit 1
--- a/hdl/spec/sim/fifo_generator_v6_1/_vmake
+++ b/hdl/spec/sim/fifo_generator_v6_1/_vmake
-m255
-K3
-cModel Technology
--- a/hdl/spec/sim/fifo_generator_v6_1/dummy/.dummy_vhd
+++ b/hdl/spec/sim/fifo_generator_v6_1/dummy/.dummy_vhd
--- a/hdl/spec/sim/fifo_generator_v6_1/xilinx_dummy_sim/_primary.dat
+++ b/hdl/spec/sim/fifo_generator_v6_1/xilinx_dummy_sim/_primary.dat
--- a/hdl/spec/sim/fifo_generator_v6_1/xilinx_dummy_sim/_primary.dbs
+++ b/hdl/spec/sim/fifo_generator_v6_1/xilinx_dummy_sim/_primary.dbs
--- a/hdl/spec/sim/modelsim.ini
+++ b/hdl/spec/sim/modelsim.ini
--- a/hdl/spec/sim/spec.do
+++ b/hdl/spec/sim/spec.do
@@ -5,8 +5,9 @@ log -r /*
 ##do wave_datapath.do
 ##do wave_multishot.do
 ##do wave_onewire.do
-do wave_adc_core.do
+##do wave_adc_core.do
 ##do wave_gnum.do
+do wave_end_acq_irq.do

 view wave
 view transcript

--- a/hdl/spec/syn/spec_top_fmc_adc_100Ms.par
+++ b/hdl/spec/syn/spec_top_fmc_adc_100Ms.par
--- a/hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
+++ b/hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
--- a/hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
+++ b/hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
--- a/hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
+++ b/hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp