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FMC ADC 100M 14b 4cha - Gateware
Commit 4d155222 authored by mcattin's avatar mcattin
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Add stall management in datapath wb interface. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@51 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent d31b0d43
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Showing with 235 additions and 81 deletions
hdl/spec/ip_cores/_xmsgs/xst.xmsgs
View file @ 4d155222
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hdl/spec/ip_cores/coregen.cgc
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hdl/spec/ip_cores/wb_sync_fifo.ngc
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hdl/spec/ip_cores/wb_sync_fifo.sym
View file @ 4d155222
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="wb_sync_fifo">
<symboltype>BLOCK</symboltype>
<timestamp>2011-3-4T16:18:13</timestamp>
<timestamp>2011-3-24T8:0:54</timestamp>
<pin polarity="Input" x="0" y="80" name="din[63:0]" />
<pin polarity="Input" x="0" y="144" name="wr_en" />
<pin polarity="Input" x="0" y="176" name="wr_clk" />
......
hdl/spec/ip_cores/wb_sync_fifo.vhd
View file @ 4d155222
......@@ -94,7 +94,7 @@ end component;
c_preload_latency => 1,
c_dout_width => 32,
c_msgon_val => 1,
c_rd_depth => 32,
c_rd_depth => 128,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
......@@ -102,31 +102,31 @@ end component;
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 4,
c_data_count_width => 6,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 5,
c_rd_pntr_width => 7,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 5,
c_rd_data_count_width => 7,
c_enable_rlocs => 0,
c_wr_pntr_width => 4,
c_wr_pntr_width => 6,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 4,
c_wr_data_count_width => 6,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 12,
c_wr_depth => 16,
c_prog_full_thresh_negate_val => 60,
c_wr_depth => 64,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 13,
c_prog_full_thresh_assert_val => 61,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
......
hdl/spec/ip_cores/wb_sync_fifo.xco
View file @ 4d155222
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Fri Mar 4 16:21:34 2011
# Date: Thu Mar 24 08:04:16 2011
#
##############################################################
#
......@@ -39,7 +39,7 @@ CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=wb_sync_fifo
CSET data_count=false
CSET data_count_width=4
CSET data_count_width=6
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
......@@ -49,14 +49,14 @@ CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=13
CSET full_threshold_negate_value=12
CSET full_threshold_assert_value=61
CSET full_threshold_negate_value=60
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=64
CSET input_depth=16
CSET input_depth=64
CSET output_data_width=32
CSET output_depth=32
CSET output_depth=128
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
......@@ -64,7 +64,7 @@ CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=5
CSET read_data_count_width=7
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
......@@ -78,7 +78,7 @@ CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=4
CSET write_data_count_width=6
# END Parameters
GENERATE
# CRC: 5ab90f71
# CRC: 5cec2fb3
hdl/spec/ip_cores/wb_sync_fifo.xise
View file @ 4d155222
......@@ -370,8 +370,8 @@
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-03-04T17:21:42" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F14EDD8CC30E922DA6BDEA21CF890B8E" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-03-24T09:04:24" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6542611C029AA541E8A3F85A38DEDEAB" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......
hdl/spec/ise_project/_xmsgs/pn_parser.xmsgs
View file @ 4d155222
......@@ -8,5 +8,8 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/rtl/ddr3_ctrl.vhd&quot; into library work</arg>
</msg>
</messages>
hdl/spec/ise_project/spec_fmc_adc_100Ms.gise
View file @ 4d155222
......@@ -78,6 +78,8 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="spec_top_fmc_adc_100Ms.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="spec_top_fmc_adc_100Ms.xst"/>
<file xil_pn:fileType="FILE_BLIF" xil_pn:name="spec_top_fmc_adc_100Ms_cs.blc"/>
<file xil_pn:fileType="FILE_NGC" xil_pn:name="spec_top_fmc_adc_100Ms_cs.ngc"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="spec_top_fmc_adc_100Ms_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spec_top_fmc_adc_100Ms_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms_map.map" xil_pn:subbranch="Map"/>
......@@ -137,7 +139,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1300809331" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1300809106">
<transform xil_pn:end_ts="1300903400" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1300903183">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -159,7 +161,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1300809359" xil_pn:in_ck="6806541686375937701" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300809331">
<transform xil_pn:end_ts="1300903428" xil_pn:in_ck="6806541686375937701" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300903400">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -169,7 +171,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ngd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1300809738" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1300809359">
<transform xil_pn:end_ts="1300903791" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1300903428">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -183,7 +185,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_summary.xml"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1300809947" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1300809738">
<transform xil_pn:end_ts="1300904000" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1300903791">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -198,7 +200,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_pad.txt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1300810013" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1300809947">
<transform xil_pn:end_ts="1300904068" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1300904000">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -219,7 +221,15 @@
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1300809947" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1300809905">
<transform xil_pn:end_ts="1300874535" xil_pn:in_ck="1401670161614890390" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300874535">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1300904000" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1300903955">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/spec/rtl/fmc_adc_100Ms_core.vhd
View file @ 4d155222
......@@ -349,6 +349,9 @@ architecture rtl of fmc_adc_100Ms_core is
signal ram_addr_cnt : unsigned(25 downto 0);
signal ram_wr_en : std_logic;
-- Wishbone interface to DDR
signal wb_ddr_stall_t : std_logic;
begin
......@@ -674,7 +677,7 @@ begin
if decim_factor /= X"0000" then
decim_cnt <= unsigned(decim_factor) - 1;
end if;
decim_en <= '1';
decim_en <= '1';
else
decim_cnt <= decim_cnt - 1;
decim_en <= '0';
......@@ -922,7 +925,7 @@ begin
wb_sync_fifo_din <= sync_fifo_dout(63 downto 0);
wb_sync_fifo_wr <= wb_sync_fifo_wr_en and not(wb_sync_fifo_full);
wb_sync_fifo_rd <= wb_sync_fifo_dreq and not(wb_sync_fifo_empty); -- and not(wb_ddr_stall_i)
wb_sync_fifo_rd <= wb_sync_fifo_dreq and not(wb_sync_fifo_empty) and not(wb_ddr_stall_t);
wb_sync_fifo_dreq <= '1';
------------------------------------------------------------------------------
......@@ -961,23 +964,32 @@ begin
p_wb_master : process (wb_ddr_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
wb_ddr_stb_o <= '0';
wb_ddr_adr_o <= (others => '0');
wb_ddr_dat_o <= (others => '0');
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
wb_ddr_stb_o <= '0';
wb_ddr_adr_o <= (others => '0');
wb_ddr_dat_o <= (others => '0');
wb_ddr_stall_t <= '0';
elsif rising_edge(wb_ddr_clk_i) then
if wb_sync_fifo_valid = '1' then --if (wb_sync_fifo_valid = '1') and (wb_ddr_stall_i = '0') then
wb_ddr_cyc_o <= '1';
wb_ddr_we_o <= '1';
wb_ddr_stb_o <= '1';
wb_ddr_adr_o <= "000000" & std_logic_vector(ram_addr_cnt);
wb_ddr_dat_o <= wb_sync_fifo_dout;
else
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
wb_ddr_stb_o <= '0';
end if;
if wb_sync_fifo_valid = '1' then
wb_ddr_cyc_o <= '1';
elsif wb_sync_fifo_empty = '1' then
wb_ddr_cyc_o <= '0';
end if;
wb_ddr_stall_t <= wb_ddr_stall_i;
end if;
end process p_wb_master;
......
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