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FMC ADC 100M 14b 4cha - Gateware
Commit 4e6378bd authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Merge branch 'feature/convention' into proposed_master

parents d98dbd10 bb7a29f7
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.gitmodules
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...@@ -13,3 +13,9 @@ ...@@ -13,3 +13,9 @@
[submodule "hdl/ip_cores/wr-cores"] [submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
doc/manual/fmc_adc_100Ms_csr.html deleted 100644 → 0
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doc/manual/fmc_adc_alt_trigin.html deleted 100644 → 0
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<HTML>
<HEAD>
<TITLE>alt_trigin</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
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</STYLE>
</HEAD>
<BODY>
<h1 class="heading">alt_trigin</h1>
<h3>FMC ADC alt trigger out registers</h3>
<p></p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x00</td>
<td>REG</td>
<td><A href="#version">version</a></td>
<td class="td_code">version</td>
<td class="td_code">version</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x04</td>
<td>REG</td>
<td><A href="#ctrl">ctrl</a></td>
<td class="td_code">ctrl</td>
<td class="td_code">ctrl</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#seconds">seconds</a></td>
<td class="td_code">seconds</td>
<td class="td_code">seconds</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#cycles">cycles</a></td>
<td class="td_code">cycles</td>
<td class="td_code">cycles</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="version"></a>
<h3><a name="sect_3_1">2.1. version</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">version</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">version</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Core version
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[7:0]</td>
</tr>
</table>
<ul>
<li><b>
version
</b>[<i>ro</i>]: Core version
</ul>
<a name="ctrl"></a>
<h3><a name="sect_3_2">2.2. ctrl</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Control register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">enable</td>
</tr>
</table>
<ul>
<li><b>
enable
</b>[<i>rw</i>]: Enable trigger, cleared when triggered
</ul>
<a name="seconds"></a>
<h3><a name="sect_3_3">2.3. seconds</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">seconds</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">seconds</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Time (seconds) to trigger
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">63</td>
<td class="td_bit" colspan="1">62</td>
<td class="td_bit" colspan="1">61</td>
<td class="td_bit" colspan="1">60</td>
<td class="td_bit" colspan="1">59</td>
<td class="td_bit" colspan="1">58</td>
<td class="td_bit" colspan="1">57</td>
<td class="td_bit" colspan="1">56</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[63:56]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">55</td>
<td class="td_bit" colspan="1">54</td>
<td class="td_bit" colspan="1">53</td>
<td class="td_bit" colspan="1">52</td>
<td class="td_bit" colspan="1">51</td>
<td class="td_bit" colspan="1">50</td>
<td class="td_bit" colspan="1">49</td>
<td class="td_bit" colspan="1">48</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[55:48]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">47</td>
<td class="td_bit" colspan="1">46</td>
<td class="td_bit" colspan="1">45</td>
<td class="td_bit" colspan="1">44</td>
<td class="td_bit" colspan="1">43</td>
<td class="td_bit" colspan="1">42</td>
<td class="td_bit" colspan="1">41</td>
<td class="td_bit" colspan="1">40</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[47:40]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">39</td>
<td class="td_bit" colspan="1">38</td>
<td class="td_bit" colspan="1">37</td>
<td class="td_bit" colspan="1">36</td>
<td class="td_bit" colspan="1">35</td>
<td class="td_bit" colspan="1">34</td>
<td class="td_bit" colspan="1">33</td>
<td class="td_bit" colspan="1">32</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[39:32]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[7:0]</td>
</tr>
</table>
<ul>
<li><b>
seconds
</b>[<i>rw</i>]: Time (seconds) to trigger
</ul>
<a name="cycles"></a>
<h3><a name="sect_3_4">2.4. cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">cycles</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">cycles</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Time (cycles) to trigger
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[7:0]</td>
</tr>
</table>
<ul>
<li><b>
cycles
</b>[<i>rw</i>]: Time (cycles) to trigger
</ul>
</BODY>
</HTML>
doc/manual/fmc_adc_alt_trigout.html deleted 100644 → 0
View file @ d98dbd10
<HTML>
<HEAD>
<TITLE>alt_trigout</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
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padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
</STYLE>
</HEAD>
<BODY>
<h1 class="heading">alt_trigout</h1>
<h3>FMC ADC alt trigger out registers</h3>
<p></p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x00</td>
<td>REG</td>
<td><A href="#status">status</a></td>
<td class="td_code">status</td>
<td class="td_code">status</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#ts_mask_sec">ts_mask_sec</a></td>
<td class="td_code">ts_mask_sec</td>
<td class="td_code">ts_mask_sec</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#ts_cycles">ts_cycles</a></td>
<td class="td_code">ts_cycles</td>
<td class="td_code">ts_cycles</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="status"></a>
<h3><a name="sect_3_1">2.1. status</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">status</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">status</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Status register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ts_present</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">wr_valid</td>
<td class="td_field" colspan="1">wr_link</td>
<td class="td_field" colspan="1">wr_enable</td>
</tr>
</table>
<ul>
<li><b>
wr_enable
</b>[<i>ro</i>]: Set when WR is enabled
<li><b>
wr_link
</b>[<i>ro</i>]: WR link status
<li><b>
wr_valid
</b>[<i>ro</i>]: Set when WR time is valid
<li><b>
ts_present
</b>[<i>ro</i>]: Set when the timestamp fifo is not empty
</ul>
<a name="ts_mask_sec"></a>
<h3><a name="sect_3_2">2.2. ts_mask_sec</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ts_mask_sec</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ts_mask_sec</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Time (seconds) of the last event
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">63</td>
<td class="td_bit" colspan="1">62</td>
<td class="td_bit" colspan="1">61</td>
<td class="td_bit" colspan="1">60</td>
<td class="td_bit" colspan="1">59</td>
<td class="td_bit" colspan="1">58</td>
<td class="td_bit" colspan="1">57</td>
<td class="td_bit" colspan="1">56</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ext_mask</td>
</tr>
<tr>
<td class="td_bit" colspan="1">55</td>
<td class="td_bit" colspan="1">54</td>
<td class="td_bit" colspan="1">53</td>
<td class="td_bit" colspan="1">52</td>
<td class="td_bit" colspan="1">51</td>
<td class="td_bit" colspan="1">50</td>
<td class="td_bit" colspan="1">49</td>
<td class="td_bit" colspan="1">48</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ch4_mask</td>
<td class="td_field" colspan="1">ch3_mask</td>
<td class="td_field" colspan="1">ch2_mask</td>
<td class="td_field" colspan="1">ch1_mask</td>
</tr>
<tr>
<td class="td_bit" colspan="1">47</td>
<td class="td_bit" colspan="1">46</td>
<td class="td_bit" colspan="1">45</td>
<td class="td_bit" colspan="1">44</td>
<td class="td_bit" colspan="1">43</td>
<td class="td_bit" colspan="1">42</td>
<td class="td_bit" colspan="1">41</td>
<td class="td_bit" colspan="1">40</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">39</td>
<td class="td_bit" colspan="1">38</td>
<td class="td_bit" colspan="1">37</td>
<td class="td_bit" colspan="1">36</td>
<td class="td_bit" colspan="1">35</td>
<td class="td_bit" colspan="1">34</td>
<td class="td_bit" colspan="1">33</td>
<td class="td_bit" colspan="1">32</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[39:32]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[7:0]</td>
</tr>
</table>
<ul>
<li><b>
ts_sec
</b>[<i>ro</i>]: Seconds part of the timestamp
<li><b>
ch1_mask
</b>[<i>ro</i>]: Set if channel 1 triggered
<li><b>
ch2_mask
</b>[<i>ro</i>]: Set if channel 2 triggered
<li><b>
ch3_mask
</b>[<i>ro</i>]: Set if channel 3 triggered
<li><b>
ch4_mask
</b>[<i>ro</i>]: Set if channel 4 triggered
<li><b>
ext_mask
</b>[<i>ro</i>]: Set if external trigger
</ul>
<a name="ts_cycles"></a>
<h3><a name="sect_3_3">2.3. ts_cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ts_cycles</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ts_cycles</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Cycles part of timestamp fifo.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">cycles[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[7:0]</td>
</tr>
</table>
<ul>
<li><b>
cycles
</b>[<i>ro</i>]: Cycles
</ul>
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<BODY>
<h1 class="heading">aux_trigin</h1>
<h3>FMC ADC aux trigger out registers</h3>
<p></p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x00</td>
<td>REG</td>
<td><A href="#version">version</a></td>
<td class="td_code">version</td>
<td class="td_code">version</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x04</td>
<td>REG</td>
<td><A href="#ctrl">ctrl</a></td>
<td class="td_code">ctrl</td>
<td class="td_code">ctrl</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#seconds">seconds</a></td>
<td class="td_code">seconds</td>
<td class="td_code">seconds</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#cycles">cycles</a></td>
<td class="td_code">cycles</td>
<td class="td_code">cycles</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="version"></a>
<h3><a name="sect_3_1">2.1. version</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">version</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">version</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Core version
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[7:0]</td>
</tr>
</table>
<ul>
<li><b>
version
</b>[<i>ro</i>]: Core version
</ul>
<a name="ctrl"></a>
<h3><a name="sect_3_2">2.2. ctrl</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Control register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">enable</td>
</tr>
</table>
<ul>
<li><b>
enable
</b>[<i>rw</i>]: Enable trigger, cleared when triggered
</ul>
<a name="seconds"></a>
<h3><a name="sect_3_3">2.3. seconds</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">seconds</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">seconds</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Time (seconds) to trigger
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">63</td>
<td class="td_bit" colspan="1">62</td>
<td class="td_bit" colspan="1">61</td>
<td class="td_bit" colspan="1">60</td>
<td class="td_bit" colspan="1">59</td>
<td class="td_bit" colspan="1">58</td>
<td class="td_bit" colspan="1">57</td>
<td class="td_bit" colspan="1">56</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[63:56]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">55</td>
<td class="td_bit" colspan="1">54</td>
<td class="td_bit" colspan="1">53</td>
<td class="td_bit" colspan="1">52</td>
<td class="td_bit" colspan="1">51</td>
<td class="td_bit" colspan="1">50</td>
<td class="td_bit" colspan="1">49</td>
<td class="td_bit" colspan="1">48</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[55:48]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">47</td>
<td class="td_bit" colspan="1">46</td>
<td class="td_bit" colspan="1">45</td>
<td class="td_bit" colspan="1">44</td>
<td class="td_bit" colspan="1">43</td>
<td class="td_bit" colspan="1">42</td>
<td class="td_bit" colspan="1">41</td>
<td class="td_bit" colspan="1">40</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[47:40]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">39</td>
<td class="td_bit" colspan="1">38</td>
<td class="td_bit" colspan="1">37</td>
<td class="td_bit" colspan="1">36</td>
<td class="td_bit" colspan="1">35</td>
<td class="td_bit" colspan="1">34</td>
<td class="td_bit" colspan="1">33</td>
<td class="td_bit" colspan="1">32</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[39:32]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[7:0]</td>
</tr>
</table>
<ul>
<li><b>
seconds
</b>[<i>rw</i>]: Time (seconds) to trigger
</ul>
<a name="cycles"></a>
<h3><a name="sect_3_4">2.4. cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">cycles</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">cycles</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Time (cycles) to trigger
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[7:0]</td>
</tr>
</table>
<ul>
<li><b>
cycles
</b>[<i>rw</i>]: Time (cycles) to trigger
</ul>
</BODY>
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<BODY>
<h1 class="heading">aux_trigout</h1>
<h3>FMC ADC aux trigger out registers</h3>
<p></p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x00</td>
<td>REG</td>
<td><A href="#status">status</a></td>
<td class="td_code">status</td>
<td class="td_code">status</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#ts_mask_sec">ts_mask_sec</a></td>
<td class="td_code">ts_mask_sec</td>
<td class="td_code">ts_mask_sec</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#ts_cycles">ts_cycles</a></td>
<td class="td_code">ts_cycles</td>
<td class="td_code">ts_cycles</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="status"></a>
<h3><a name="sect_3_1">2.1. status</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">status</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">status</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Status register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ts_present</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">wr_valid</td>
<td class="td_field" colspan="1">wr_link</td>
<td class="td_field" colspan="1">wr_enable</td>
</tr>
</table>
<ul>
<li><b>
wr_enable
</b>[<i>ro</i>]: Set when WR is enabled
<li><b>
wr_link
</b>[<i>ro</i>]: WR link status
<li><b>
wr_valid
</b>[<i>ro</i>]: Set when WR time is valid
<li><b>
ts_present
</b>[<i>ro</i>]: Set when the timestamp fifo is not empty
</ul>
<a name="ts_mask_sec"></a>
<h3><a name="sect_3_2">2.2. ts_mask_sec</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ts_mask_sec</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ts_mask_sec</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Time (seconds) of the last event
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">63</td>
<td class="td_bit" colspan="1">62</td>
<td class="td_bit" colspan="1">61</td>
<td class="td_bit" colspan="1">60</td>
<td class="td_bit" colspan="1">59</td>
<td class="td_bit" colspan="1">58</td>
<td class="td_bit" colspan="1">57</td>
<td class="td_bit" colspan="1">56</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ext_mask</td>
</tr>
<tr>
<td class="td_bit" colspan="1">55</td>
<td class="td_bit" colspan="1">54</td>
<td class="td_bit" colspan="1">53</td>
<td class="td_bit" colspan="1">52</td>
<td class="td_bit" colspan="1">51</td>
<td class="td_bit" colspan="1">50</td>
<td class="td_bit" colspan="1">49</td>
<td class="td_bit" colspan="1">48</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ch4_mask</td>
<td class="td_field" colspan="1">ch3_mask</td>
<td class="td_field" colspan="1">ch2_mask</td>
<td class="td_field" colspan="1">ch1_mask</td>
</tr>
<tr>
<td class="td_bit" colspan="1">47</td>
<td class="td_bit" colspan="1">46</td>
<td class="td_bit" colspan="1">45</td>
<td class="td_bit" colspan="1">44</td>
<td class="td_bit" colspan="1">43</td>
<td class="td_bit" colspan="1">42</td>
<td class="td_bit" colspan="1">41</td>
<td class="td_bit" colspan="1">40</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">39</td>
<td class="td_bit" colspan="1">38</td>
<td class="td_bit" colspan="1">37</td>
<td class="td_bit" colspan="1">36</td>
<td class="td_bit" colspan="1">35</td>
<td class="td_bit" colspan="1">34</td>
<td class="td_bit" colspan="1">33</td>
<td class="td_bit" colspan="1">32</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[39:32]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[7:0]</td>
</tr>
</table>
<ul>
<li><b>
ts_sec
</b>[<i>ro</i>]: Seconds part of the timestamp
<li><b>
ch1_mask
</b>[<i>ro</i>]: Set if channel 1 triggered
<li><b>
ch2_mask
</b>[<i>ro</i>]: Set if channel 2 triggered
<li><b>
ch3_mask
</b>[<i>ro</i>]: Set if channel 3 triggered
<li><b>
ch4_mask
</b>[<i>ro</i>]: Set if channel 4 triggered
<li><b>
ext_mask
</b>[<i>ro</i>]: Set if external trigger
</ul>
<a name="ts_cycles"></a>
<h3><a name="sect_3_3">2.3. ts_cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ts_cycles</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ts_cycles</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Cycles part of timestamp fifo.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">cycles[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[7:0]</td>
</tr>
</table>
<ul>
<li><b>
cycles
</b>[<i>ro</i>]: Cycles
</ul>
</BODY>
</HTML>
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<HTML>
<HEAD>
<TITLE>spec_carrier_csr</TITLE>
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<BODY>
<h1 class="heading">spec_carrier_csr</h1>
<h3>Carrier control and status registers</h3>
<p>Wishbone slave for control and status registers related to the FMC carrier</p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x0</td>
<td>REG</td>
<td><A href="#carrier">carrier</a></td>
<td class="td_code">carrier</td>
<td class="td_code">carrier</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x4</td>
<td>REG</td>
<td><A href="#stat">stat</a></td>
<td class="td_code">stat</td>
<td class="td_code">stat</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x8</td>
<td>REG</td>
<td><A href="#ctrl">ctrl</a></td>
<td class="td_code">ctrl</td>
<td class="td_code">ctrl</td>
</tr>
<tr class="tr_even">
<td class="td_code">0xc</td>
<td>REG</td>
<td><A href="#rst">rst</a></td>
<td class="td_code">rst</td>
<td class="td_code">rst</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="carrier"></a>
<h3><a name="sect_3_1">2.1. carrier</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">carrier</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">carrier</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Carrier type and PCB version
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">type[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">type[7:0]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">reserved[11:4]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="4">reserved[3:0]</td>
<td class="td_field" colspan="4">pcb_rev[3:0]</td>
</tr>
</table>
<ul>
<li><b>
pcb_rev
</b>[<i>ro</i>]: PCB revision
<br>Binary coded PCB layout revision.
<li><b>
reserved
</b>[<i>ro</i>]: Reserved register
<br>Ignore on read, write with 0's.
<li><b>
type
</b>[<i>ro</i>]: Carrier type
<br>Carrier type identifier<br>1 = SPEC<br>2 = SVEC<br>3 = VFC<br>4 = SPEXI
</ul>
<a name="stat"></a>
<h3><a name="sect_3_2">2.2. stat</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">stat</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">stat</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Status
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ddr3_cal_done</td>
<td class="td_field" colspan="1">sys_pll_lck</td>
<td class="td_field" colspan="1">p2l_pll_lck</td>
<td class="td_field" colspan="1">fmc_pres</td>
</tr>
</table>
<ul>
<li><b>
fmc_pres
</b>[<i>ro</i>]: FMC presence
<br>0: FMC slot is populated<br>1: FMC slot is not populated.
<li><b>
p2l_pll_lck
</b>[<i>ro</i>]: GN4142 core P2L PLL status
<br>0: not locked<br>1: locked.
<li><b>
sys_pll_lck
</b>[<i>ro</i>]: System clock PLL status
<br>0: not locked<br>1: locked.
<li><b>
ddr3_cal_done
</b>[<i>ro</i>]: DDR3 calibration status
<br>0: not done<br>1: done.
</ul>
<a name="ctrl"></a>
<h3><a name="sect_3_3">2.3. ctrl</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Control
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">led_red</td>
<td class="td_field" colspan="1">led_green</td>
</tr>
</table>
<ul>
<li><b>
led_green
</b>[<i>rw</i>]: Green LED
<br>Manual control of the front panel green LED (unused in the fmc-adc application)
<li><b>
led_red
</b>[<i>rw</i>]: Red LED
<br>Manual control of the front panel red LED (unused in the fmc-adc application)
</ul>
<a name="rst"></a>
<h3><a name="sect_3_4">2.4. rst</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">rst</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0xc</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">rst</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0xc</td></tr>
</table>
<p>
Reset Register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">fmc0</td>
</tr>
</table>
<ul>
<li><b>
fmc0
</b>[<i>wo</i>]: State of the reset line
<br>write 0: Normal FMC operation<br>write 1: FMC is held in reset
</ul>
</BODY>
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<HTML>
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<h1 class="heading">svec_carrier_csr</h1>
<h3>SVEC carrier control and status registers</h3>
<p>Wishbone slave for control and status registers related to the SVEC FMC carrier</p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x0</td>
<td>REG</td>
<td><A href="#carrier">carrier</a></td>
<td class="td_code">carrier</td>
<td class="td_code">carrier</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x4</td>
<td>REG</td>
<td><A href="#stat">stat</a></td>
<td class="td_code">stat</td>
<td class="td_code">stat</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x8</td>
<td>REG</td>
<td><A href="#ctrl">ctrl</a></td>
<td class="td_code">ctrl</td>
<td class="td_code">ctrl</td>
</tr>
<tr class="tr_even">
<td class="td_code">0xc</td>
<td>REG</td>
<td><A href="#rst">rst</a></td>
<td class="td_code">rst</td>
<td class="td_code">rst</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="carrier"></a>
<h3><a name="sect_3_1">2.1. carrier</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">carrier</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">carrier</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Carrier type and PCB version
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">type[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">type[7:0]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">reserved[10:3]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="3">reserved[2:0]</td>
<td class="td_field" colspan="5">pcb_rev[4:0]</td>
</tr>
</table>
<ul>
<li><b>
pcb_rev
</b>[<i>ro</i>]: PCB revision
<br>Binary coded PCB layout revision.
<li><b>
reserved
</b>[<i>ro</i>]: Reserved register
<br>Ignore on read, write with 0's.
<li><b>
type
</b>[<i>ro</i>]: Carrier type
<br>Carrier type identifier<br>1 = SPEC<br>2 = SVEC<br>3 = VFC<br>4 = SPEXI
</ul>
<a name="stat"></a>
<h3><a name="sect_3_2">2.2. stat</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">stat</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">stat</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Status
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ddr1_cal_done</td>
<td class="td_field" colspan="1">ddr0_cal_done</td>
<td class="td_field" colspan="1">sys_pll_lck</td>
<td class="td_field" colspan="1">fmc1_pres</td>
<td class="td_field" colspan="1">fmc0_pres</td>
</tr>
</table>
<ul>
<li><b>
fmc0_pres
</b>[<i>ro</i>]: FMC 1 presence
<br>0: FMC slot 1 is populated<br>1: FMC slot 1 is not populated.
<li><b>
fmc1_pres
</b>[<i>ro</i>]: FMC 2 presence
<br>0: FMC slot 2 is populated<br>1: FMC slot 2 is not populated.
<li><b>
sys_pll_lck
</b>[<i>ro</i>]: System clock PLL status
<br>0: not locked<br>1: locked.
<li><b>
ddr0_cal_done
</b>[<i>ro</i>]: DDR3 bank 4 calibration status
<br>0: not done<br>1: done.
<li><b>
ddr1_cal_done
</b>[<i>ro</i>]: DDR3 bank 5 calibration status
<br>0: not done<br>1: done.
</ul>
<a name="ctrl"></a>
<h3><a name="sect_3_3">2.3. ctrl</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Control
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">fp_leds_man[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">fp_leds_man[7:0]</td>
</tr>
</table>
<ul>
<li><b>
fp_leds_man
</b>[<i>rw</i>]: Front panel LED manual control
<br>Height front panel LED, two bits per LED.<br>00 = OFF<br>01 = Green<br>10 = Red<br>11 = Orange
</ul>
<a name="rst"></a>
<h3><a name="sect_3_4">2.4. rst</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">rst</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0xc</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">rst</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0xc</td></tr>
</table>
<p>
Reset Register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">fmc1</td>
<td class="td_field" colspan="1">fmc0</td>
</tr>
</table>
<ul>
<li><b>
fmc0
</b>[<i>wo</i>]: State of the FMC 1 reset line
<br>write 0: Normal FMC operation<br>write 1: FMC is held in reset
<li><b>
fmc1
</b>[<i>wo</i>]: State of the FMC 2 reset line
<br>write 0: Normal FMC operation<br>write 1: FMC is held in reset
</ul>
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</HEAD>
<BODY>
<h1 class="heading">timetag_core_regs</h1>
<h3>Time-tagging core registers</h3>
<p>Wishbone slave for registers related to time-tagging core</p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x00</td>
<td>REG</td>
<td><A href="#seconds_upper">seconds_upper</a></td>
<td class="td_code">seconds_upper</td>
<td class="td_code">seconds_upper</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x04</td>
<td>REG</td>
<td><A href="#seconds_lower">seconds_lower</a></td>
<td class="td_code">seconds_lower</td>
<td class="td_code">seconds_lower</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#coarse">coarse</a></td>
<td class="td_code">coarse</td>
<td class="td_code">coarse</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x0c</td>
<td>REG</td>
<td><A href="#time_trig_seconds_upper">time_trig_seconds_upper</a></td>
<td class="td_code">time_trig_seconds_upper</td>
<td class="td_code">time_trig_seconds_upper</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#time_trig_seconds_lower">time_trig_seconds_lower</a></td>
<td class="td_code">time_trig_seconds_lower</td>
<td class="td_code">time_trig_seconds_lower</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x14</td>
<td>REG</td>
<td><A href="#time_trig_coarse">time_trig_coarse</a></td>
<td class="td_code">time_trig_coarse</td>
<td class="td_code">time_trig_coarse</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x18</td>
<td>REG</td>
<td><A href="#trig_tag_seconds_upper">trig_tag_seconds_upper</a></td>
<td class="td_code">trig_tag_seconds_upper</td>
<td class="td_code">trig_tag_seconds_upper</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x1c</td>
<td>REG</td>
<td><A href="#trig_tag_seconds_lower">trig_tag_seconds_lower</a></td>
<td class="td_code">trig_tag_seconds_lower</td>
<td class="td_code">trig_tag_seconds_lower</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x20</td>
<td>REG</td>
<td><A href="#trig_tag_coarse">trig_tag_coarse</a></td>
<td class="td_code">trig_tag_coarse</td>
<td class="td_code">trig_tag_coarse</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x24</td>
<td>REG</td>
<td><A href="#acq_start_tag_seconds_upper">acq_start_tag_seconds_upper</a></td>
<td class="td_code">acq_start_tag_seconds_upper</td>
<td class="td_code">acq_start_tag_seconds_upper</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x28</td>
<td>REG</td>
<td><A href="#acq_start_tag_seconds_lower">acq_start_tag_seconds_lower</a></td>
<td class="td_code">acq_start_tag_seconds_lower</td>
<td class="td_code">acq_start_tag_seconds_lower</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x2c</td>
<td>REG</td>
<td><A href="#acq_start_tag_coarse">acq_start_tag_coarse</a></td>
<td class="td_code">acq_start_tag_coarse</td>
<td class="td_code">acq_start_tag_coarse</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x30</td>
<td>REG</td>
<td><A href="#acq_stop_tag_seconds_upper">acq_stop_tag_seconds_upper</a></td>
<td class="td_code">acq_stop_tag_seconds_upper</td>
<td class="td_code">acq_stop_tag_seconds_upper</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x34</td>
<td>REG</td>
<td><A href="#acq_stop_tag_seconds_lower">acq_stop_tag_seconds_lower</a></td>
<td class="td_code">acq_stop_tag_seconds_lower</td>
<td class="td_code">acq_stop_tag_seconds_lower</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x38</td>
<td>REG</td>
<td><A href="#acq_stop_tag_coarse">acq_stop_tag_coarse</a></td>
<td class="td_code">acq_stop_tag_coarse</td>
<td class="td_code">acq_stop_tag_coarse</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x3c</td>
<td>REG</td>
<td><A href="#acq_end_tag_seconds_upper">acq_end_tag_seconds_upper</a></td>
<td class="td_code">acq_end_tag_seconds_upper</td>
<td class="td_code">acq_end_tag_seconds_upper</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x40</td>
<td>REG</td>
<td><A href="#acq_end_tag_seconds_lower">acq_end_tag_seconds_lower</a></td>
<td class="td_code">acq_end_tag_seconds_lower</td>
<td class="td_code">acq_end_tag_seconds_lower</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x44</td>
<td>REG</td>
<td><A href="#acq_end_tag_coarse">acq_end_tag_coarse</a></td>
<td class="td_code">acq_end_tag_coarse</td>
<td class="td_code">acq_end_tag_coarse</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="seconds_upper"></a>
<h3><a name="sect_3_1">2.1. seconds_upper</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">seconds_upper</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">seconds_upper</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Timetag seconds register (upper)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds_upper[7:0]</td>
</tr>
</table>
<ul>
<li><b>
seconds_upper
</b>[<i>rw</i>]: Timetag seconds
</ul>
<a name="seconds_lower"></a>
<h3><a name="sect_3_2">2.2. seconds_lower</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">seconds_lower</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">seconds_lower</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Timetag seconds register (lower)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds_lower[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds_lower[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds_lower[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds_lower[7:0]</td>
</tr>
</table>
<ul>
<li><b>
seconds_lower
</b>[<i>rw</i>]: Timetag seconds register (lower)
</ul>
<a name="coarse"></a>
<h3><a name="sect_3_3">2.3. coarse</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">coarse</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">coarse</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Timetag coarse time register, system clock ticks (125MHz)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">coarse[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">coarse[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">coarse[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">coarse[7:0]</td>
</tr>
</table>
<ul>
<li><b>
coarse
</b>[<i>rw</i>]: Timetag coarse time
</ul>
<a name="time_trig_seconds_upper"></a>
<h3><a name="sect_3_4">2.4. time_trig_seconds_upper</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">time_trig_seconds_upper</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0xc</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">time_trig_seconds_upper</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0xc</td></tr>
</table>
<p>
Time trigger seconds register (upper)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_seconds_upper[7:0]</td>
</tr>
</table>
<ul>
<li><b>
time_trig_seconds_upper
</b>[<i>rw</i>]: Time trigger seconds
</ul>
<a name="time_trig_seconds_lower"></a>
<h3><a name="sect_3_5">2.5. time_trig_seconds_lower</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">time_trig_seconds_lower</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">time_trig_seconds_lower</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Time trigger seconds register (lower)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_seconds_lower[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_seconds_lower[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_seconds_lower[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_seconds_lower[7:0]</td>
</tr>
</table>
<ul>
<li><b>
time_trig_seconds_lower
</b>[<i>rw</i>]: Time trigger seconds register (lower)
</ul>
<a name="time_trig_coarse"></a>
<h3><a name="sect_3_6">2.6. time_trig_coarse</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">time_trig_coarse</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x14</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">time_trig_coarse</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x14</td></tr>
</table>
<p>
Time trigger coarse time register, system clock ticks (125MHz)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">time_trig_coarse[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_coarse[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_coarse[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_coarse[7:0]</td>
</tr>
</table>
<ul>
<li><b>
time_trig_coarse
</b>[<i>rw</i>]: Time trigger coarse value
</ul>
<a name="trig_tag_seconds_upper"></a>
<h3><a name="sect_3_7">2.7. trig_tag_seconds_upper</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">trig_tag_seconds_upper</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x18</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">trig_tag_seconds_upper</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x18</td></tr>
</table>
<p>
Trigger time-tag seconds register (upper)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_seconds_upper[7:0]</td>
</tr>
</table>
<ul>
<li><b>
trig_tag_seconds_upper
</b>[<i>ro</i>]: Trigger time-tag seconds
<br>Holds time-tag seconds of the last trigger event
</ul>
<a name="trig_tag_seconds_lower"></a>
<h3><a name="sect_3_8">2.8. trig_tag_seconds_lower</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">trig_tag_seconds_lower</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x1c</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">trig_tag_seconds_lower</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x1c</td></tr>
</table>
<p>
Trigger time-tag seconds register (lower)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_seconds_lower[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_seconds_lower[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_seconds_lower[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_seconds_lower[7:0]</td>
</tr>
</table>
<ul>
<li><b>
trig_tag_seconds_lower
</b>[<i>ro</i>]: Trigger time-tag seconds register (lower)
</ul>
<a name="trig_tag_coarse"></a>
<h3><a name="sect_3_9">2.9. trig_tag_coarse</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">trig_tag_coarse</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x20</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">trig_tag_coarse</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x20</td></tr>
</table>
<p>
Trigger time-tag coarse time (system clock ticks 125MHz) register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">trig_tag_coarse[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_coarse[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_coarse[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_coarse[7:0]</td>
</tr>
</table>
<ul>
<li><b>
trig_tag_coarse
</b>[<i>ro</i>]: Trigger time-tag coarse time
<br>Holds time-tag coarse time of the last trigger event
</ul>
<a name="acq_start_tag_seconds_upper"></a>
<h3><a name="sect_3_10">2.10. acq_start_tag_seconds_upper</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_start_tag_seconds_upper</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x24</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_start_tag_seconds_upper</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x24</td></tr>
</table>
<p>
Acquisition start time-tag seconds register (upper)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_seconds_upper[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_start_tag_seconds_upper
</b>[<i>ro</i>]: Acquisition start time-tag seconds
<br>Holds time-tag seconds of the last acquisition start event
</ul>
<a name="acq_start_tag_seconds_lower"></a>
<h3><a name="sect_3_11">2.11. acq_start_tag_seconds_lower</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_start_tag_seconds_lower</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x28</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_start_tag_seconds_lower</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x28</td></tr>
</table>
<p>
Acquisition start time-tag seconds register (lower)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_seconds_lower[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_seconds_lower[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_seconds_lower[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_seconds_lower[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_start_tag_seconds_lower
</b>[<i>ro</i>]: Acquisition start time-tag seconds register (lower)
</ul>
<a name="acq_start_tag_coarse"></a>
<h3><a name="sect_3_12">2.12. acq_start_tag_coarse</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_start_tag_coarse</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x2c</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_start_tag_coarse</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x2c</td></tr>
</table>
<p>
Acquisition start time-tag coarse time (system clock ticks 125MHz) register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">acq_start_tag_coarse[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_coarse[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_coarse[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_coarse[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_start_tag_coarse
</b>[<i>ro</i>]: Acquisition start time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition start event
</ul>
<a name="acq_stop_tag_seconds_upper"></a>
<h3><a name="sect_3_13">2.13. acq_stop_tag_seconds_upper</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_stop_tag_seconds_upper</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x30</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_stop_tag_seconds_upper</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x30</td></tr>
</table>
<p>
Acquisition stop time-tag seconds register (upper)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_seconds_upper[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_stop_tag_seconds_upper
</b>[<i>ro</i>]: Acquisition stop time-tag seconds
<br>Holds time-tag seconds of the last acquisition stop event
</ul>
<a name="acq_stop_tag_seconds_lower"></a>
<h3><a name="sect_3_14">2.14. acq_stop_tag_seconds_lower</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_stop_tag_seconds_lower</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x34</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_stop_tag_seconds_lower</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x34</td></tr>
</table>
<p>
Acquisition stop time-tag seconds register (lower)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_seconds_lower[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_seconds_lower[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_seconds_lower[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_seconds_lower[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_stop_tag_seconds_lower
</b>[<i>ro</i>]: Acquisition stop time-tag seconds register (lower)
</ul>
<a name="acq_stop_tag_coarse"></a>
<h3><a name="sect_3_15">2.15. acq_stop_tag_coarse</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_stop_tag_coarse</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x38</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_stop_tag_coarse</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x38</td></tr>
</table>
<p>
Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">acq_stop_tag_coarse[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_coarse[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_coarse[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_coarse[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_stop_tag_coarse
</b>[<i>ro</i>]: Acquisition stop time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition stop event
</ul>
<a name="acq_end_tag_seconds_upper"></a>
<h3><a name="sect_3_16">2.16. acq_end_tag_seconds_upper</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_end_tag_seconds_upper</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x3c</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_end_tag_seconds_upper</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x3c</td></tr>
</table>
<p>
Acquisition end time-tag seconds register (upper)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_seconds_upper[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_end_tag_seconds_upper
</b>[<i>ro</i>]: Acquisition end time-tag seconds
<br>Holds time-tag seconds of the last acquisition end event
</ul>
<a name="acq_end_tag_seconds_lower"></a>
<h3><a name="sect_3_17">2.17. acq_end_tag_seconds_lower</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_end_tag_seconds_lower</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x40</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_end_tag_seconds_lower</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x40</td></tr>
</table>
<p>
Acquisition end time-tag seconds register (lower)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_seconds_lower[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_seconds_lower[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_seconds_lower[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_seconds_lower[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_end_tag_seconds_lower
</b>[<i>ro</i>]: Acquisition end time-tag seconds register (lower)
</ul>
<a name="acq_end_tag_coarse"></a>
<h3><a name="sect_3_18">2.18. acq_end_tag_coarse</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_end_tag_coarse</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x44</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_end_tag_coarse</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x44</td></tr>
</table>
<p>
Acquisition end time-tag coarse time (system clock ticks 125MHz) register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">acq_end_tag_coarse[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_coarse[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_coarse[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_coarse[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_end_tag_coarse
</b>[<i>ro</i>]: Acquisition end time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition end event
</ul>
</BODY>
</HTML>
hdl/rtl/Makefile → hdl/cheby/Makefile
View file @ 4e6378bd
SIM =../testbench/include SIM =../testbench/include
DOC =../../doc/manual
SW =../../software/include/hw SW =../../software/include/hw
SOURCES = $(wildcard *.cheby) SOURCES = $(wildcard *.cheby)
...@@ -13,6 +12,5 @@ $(TARGETS): %.vhd : %.cheby ...@@ -13,6 +12,5 @@ $(TARGETS): %.vhd : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m" @echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@ @cheby -i $< --gen-hdl=$@
@cheby -i $< \ @cheby -i $< \
--gen-doc=$(DOC)/$(@:.vhd=.html) \
--gen-consts=$(SIM)/$(@:.vhd=.v) \ --gen-consts=$(SIM)/$(@:.vhd=.v) \
--gen-c=$(SW)/$(@:.vhd=.h) --gen-c=$(SW)/$(@:.vhd=.h)
hdl/rtl/fmc_adc_100Ms_csr.cheby → hdl/cheby/fmc_adc_100Ms_csr.cheby
View file @ 4e6378bd
memory-map: memory-map:
bus: wb-32-be bus: wb-32-be
name: fmc_adc_100ms_csr name: fmc_adc_100ms_csr
size: 0x200
description: FMC ADC 100MS/s core registers description: FMC ADC 100MS/s core registers
comment: | comment: |
Wishbone slave for FMC ADC 100MS/s core Wishbone slave for FMC ADC 100MS/s core
......
hdl/cheby/fmc_adc_mezzanine_mmap.cheby 0 → 100644
View file @ 4e6378bd
memory-map:
name: fmc_adc_mezzanine_mmap
bus: wb-32-be
description: FMC-ADC-100M mezzanine memory map
size: 0x2000
x-hdl:
busgroup: True
children:
- submap:
name: fmc_adc_100m_csr
address: 0x1000
description: FMC ADC 100M CSR
filename: fmc_adc_100Ms_csr.cheby
- submap:
name: fmc_adc_eic
address: 0x1500
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
description: FMC ADC Embedded Interrupt Controller
- submap:
name: si570_i2c_master
address: 0x1600
size: 0x100
interface: wb-32-be
x-hdl:
busgroup: True
description: Si570 control I2C master
- submap:
name: ds18b20_onewire_master
address: 0x1700
description: DS18B20 OneWire master
filename: ../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.cheby
- submap:
name: fmc_spi_master
address: 0x1800
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
description: Mezzanine SPI master (ADC control + DAC offsets)
- submap:
name: timetag_core
address: 0x1900
description: Timetag Core
filename: timetag_core_regs.cheby
hdl/cheby/fmc_adc_mezzanine_mmap.vhd 0 → 100644
View file @ 4e6378bd
-- Do not edit; this file was generated by Cheby using these options:
-- -i fmc_adc_mezzanine_mmap.cheby --gen-hdl=fmc_adc_mezzanine_mmap.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity fmc_adc_mezzanine_mmap is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- FMC ADC 100M CSR
fmc_adc_100m_csr_i : in t_wishbone_master_in;
fmc_adc_100m_csr_o : out t_wishbone_master_out;
-- FMC ADC Embedded Interrupt Controller
fmc_adc_eic_i : in t_wishbone_master_in;
fmc_adc_eic_o : out t_wishbone_master_out;
-- Si570 control I2C master
si570_i2c_master_i : in t_wishbone_master_in;
si570_i2c_master_o : out t_wishbone_master_out;
-- DS18B20 OneWire master
ds18b20_onewire_master_i : in t_wishbone_master_in;
ds18b20_onewire_master_o : out t_wishbone_master_out;
-- Mezzanine SPI master (ADC control + DAC offsets)
fmc_spi_master_i : in t_wishbone_master_in;
fmc_spi_master_o : out t_wishbone_master_out;
-- Timetag Core
timetag_core_i : in t_wishbone_master_in;
timetag_core_o : out t_wishbone_master_out
);
end fmc_adc_mezzanine_mmap;
architecture syn of fmc_adc_mezzanine_mmap is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal fmc_adc_100m_csr_re : std_logic;
signal fmc_adc_100m_csr_wt : std_logic;
signal fmc_adc_100m_csr_rt : std_logic;
signal fmc_adc_100m_csr_tr : std_logic;
signal fmc_adc_100m_csr_wack : std_logic;
signal fmc_adc_100m_csr_rack : std_logic;
signal fmc_adc_eic_re : std_logic;
signal fmc_adc_eic_wt : std_logic;
signal fmc_adc_eic_rt : std_logic;
signal fmc_adc_eic_tr : std_logic;
signal fmc_adc_eic_wack : std_logic;
signal fmc_adc_eic_rack : std_logic;
signal si570_i2c_master_re : std_logic;
signal si570_i2c_master_wt : std_logic;
signal si570_i2c_master_rt : std_logic;
signal si570_i2c_master_tr : std_logic;
signal si570_i2c_master_wack : std_logic;
signal si570_i2c_master_rack : std_logic;
signal ds18b20_onewire_master_re : std_logic;
signal ds18b20_onewire_master_wt : std_logic;
signal ds18b20_onewire_master_rt : std_logic;
signal ds18b20_onewire_master_tr : std_logic;
signal ds18b20_onewire_master_wack : std_logic;
signal ds18b20_onewire_master_rack : std_logic;
signal fmc_spi_master_re : std_logic;
signal fmc_spi_master_wt : std_logic;
signal fmc_spi_master_rt : std_logic;
signal fmc_spi_master_tr : std_logic;
signal fmc_spi_master_wack : std_logic;
signal fmc_spi_master_rack : std_logic;
signal timetag_core_re : std_logic;
signal timetag_core_wt : std_logic;
signal timetag_core_rt : std_logic;
signal timetag_core_tr : std_logic;
signal timetag_core_wack : std_logic;
signal timetag_core_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
-- Assignments for submap fmc_adc_100m_csr
fmc_adc_100m_csr_tr <= fmc_adc_100m_csr_wt or fmc_adc_100m_csr_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_adc_100m_csr_rt <= '0';
else
fmc_adc_100m_csr_rt <= (fmc_adc_100m_csr_rt or fmc_adc_100m_csr_re) and not fmc_adc_100m_csr_rack;
end if;
end if;
end process;
fmc_adc_100m_csr_o.cyc <= fmc_adc_100m_csr_tr;
fmc_adc_100m_csr_o.stb <= fmc_adc_100m_csr_tr;
fmc_adc_100m_csr_wack <= fmc_adc_100m_csr_i.ack and fmc_adc_100m_csr_wt;
fmc_adc_100m_csr_rack <= fmc_adc_100m_csr_i.ack and fmc_adc_100m_csr_rt;
fmc_adc_100m_csr_o.adr <= ((22 downto 0 => '0') & wb_i.adr(8 downto 2)) & (1 downto 0 => '0');
fmc_adc_100m_csr_o.sel <= (others => '1');
fmc_adc_100m_csr_o.we <= fmc_adc_100m_csr_wt;
fmc_adc_100m_csr_o.dat <= wb_i.dat;
-- Assignments for submap fmc_adc_eic
fmc_adc_eic_tr <= fmc_adc_eic_wt or fmc_adc_eic_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_adc_eic_rt <= '0';
else
fmc_adc_eic_rt <= (fmc_adc_eic_rt or fmc_adc_eic_re) and not fmc_adc_eic_rack;
end if;
end if;
end process;
fmc_adc_eic_o.cyc <= fmc_adc_eic_tr;
fmc_adc_eic_o.stb <= fmc_adc_eic_tr;
fmc_adc_eic_wack <= fmc_adc_eic_i.ack and fmc_adc_eic_wt;
fmc_adc_eic_rack <= fmc_adc_eic_i.ack and fmc_adc_eic_rt;
fmc_adc_eic_o.adr <= ((27 downto 0 => '0') & wb_i.adr(3 downto 2)) & (1 downto 0 => '0');
fmc_adc_eic_o.sel <= (others => '1');
fmc_adc_eic_o.we <= fmc_adc_eic_wt;
fmc_adc_eic_o.dat <= wb_i.dat;
-- Assignments for submap si570_i2c_master
si570_i2c_master_tr <= si570_i2c_master_wt or si570_i2c_master_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
si570_i2c_master_rt <= '0';
else
si570_i2c_master_rt <= (si570_i2c_master_rt or si570_i2c_master_re) and not si570_i2c_master_rack;
end if;
end if;
end process;
si570_i2c_master_o.cyc <= si570_i2c_master_tr;
si570_i2c_master_o.stb <= si570_i2c_master_tr;
si570_i2c_master_wack <= si570_i2c_master_i.ack and si570_i2c_master_wt;
si570_i2c_master_rack <= si570_i2c_master_i.ack and si570_i2c_master_rt;
si570_i2c_master_o.adr <= ((23 downto 0 => '0') & wb_i.adr(7 downto 2)) & (1 downto 0 => '0');
si570_i2c_master_o.sel <= (others => '1');
si570_i2c_master_o.we <= si570_i2c_master_wt;
si570_i2c_master_o.dat <= wb_i.dat;
-- Assignments for submap ds18b20_onewire_master
ds18b20_onewire_master_tr <= ds18b20_onewire_master_wt or ds18b20_onewire_master_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ds18b20_onewire_master_rt <= '0';
else
ds18b20_onewire_master_rt <= (ds18b20_onewire_master_rt or ds18b20_onewire_master_re) and not ds18b20_onewire_master_rack;
end if;
end if;
end process;
ds18b20_onewire_master_o.cyc <= ds18b20_onewire_master_tr;
ds18b20_onewire_master_o.stb <= ds18b20_onewire_master_tr;
ds18b20_onewire_master_wack <= ds18b20_onewire_master_i.ack and ds18b20_onewire_master_wt;
ds18b20_onewire_master_rack <= ds18b20_onewire_master_i.ack and ds18b20_onewire_master_rt;
ds18b20_onewire_master_o.adr <= ((27 downto 0 => '0') & wb_i.adr(3 downto 2)) & (1 downto 0 => '0');
ds18b20_onewire_master_o.sel <= (others => '1');
ds18b20_onewire_master_o.we <= ds18b20_onewire_master_wt;
ds18b20_onewire_master_o.dat <= wb_i.dat;
-- Assignments for submap fmc_spi_master
fmc_spi_master_tr <= fmc_spi_master_wt or fmc_spi_master_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_spi_master_rt <= '0';
else
fmc_spi_master_rt <= (fmc_spi_master_rt or fmc_spi_master_re) and not fmc_spi_master_rack;
end if;
end if;
end process;
fmc_spi_master_o.cyc <= fmc_spi_master_tr;
fmc_spi_master_o.stb <= fmc_spi_master_tr;
fmc_spi_master_wack <= fmc_spi_master_i.ack and fmc_spi_master_wt;
fmc_spi_master_rack <= fmc_spi_master_i.ack and fmc_spi_master_rt;
fmc_spi_master_o.adr <= ((26 downto 0 => '0') & wb_i.adr(4 downto 2)) & (1 downto 0 => '0');
fmc_spi_master_o.sel <= (others => '1');
fmc_spi_master_o.we <= fmc_spi_master_wt;
fmc_spi_master_o.dat <= wb_i.dat;
-- Assignments for submap timetag_core
timetag_core_tr <= timetag_core_wt or timetag_core_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
timetag_core_rt <= '0';
else
timetag_core_rt <= (timetag_core_rt or timetag_core_re) and not timetag_core_rack;
end if;
end if;
end process;
timetag_core_o.cyc <= timetag_core_tr;
timetag_core_o.stb <= timetag_core_tr;
timetag_core_wack <= timetag_core_i.ack and timetag_core_wt;
timetag_core_rack <= timetag_core_i.ack and timetag_core_rt;
timetag_core_o.adr <= ((24 downto 0 => '0') & wb_i.adr(6 downto 2)) & (1 downto 0 => '0');
timetag_core_o.sel <= (others => '1');
timetag_core_o.we <= timetag_core_wt;
timetag_core_o.dat <= wb_i.dat;
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
fmc_adc_100m_csr_wt <= '0';
fmc_adc_eic_wt <= '0';
si570_i2c_master_wt <= '0';
ds18b20_onewire_master_wt <= '0';
fmc_spi_master_wt <= '0';
timetag_core_wt <= '0';
else
wr_ack_int <= '0';
fmc_adc_100m_csr_wt <= '0';
fmc_adc_eic_wt <= '0';
si570_i2c_master_wt <= '0';
ds18b20_onewire_master_wt <= '0';
fmc_spi_master_wt <= '0';
timetag_core_wt <= '0';
case wb_i.adr(12 downto 9) is
when "1000" =>
-- Submap fmc_adc_100m_csr
fmc_adc_100m_csr_wt <= (fmc_adc_100m_csr_wt or wr_int) and not fmc_adc_100m_csr_wack;
wr_ack_int <= fmc_adc_100m_csr_wack;
when "1010" =>
-- Submap fmc_adc_eic
fmc_adc_eic_wt <= (fmc_adc_eic_wt or wr_int) and not fmc_adc_eic_wack;
wr_ack_int <= fmc_adc_eic_wack;
when "1011" =>
case wb_i.adr(8 downto 8) is
when "0" =>
-- Submap si570_i2c_master
si570_i2c_master_wt <= (si570_i2c_master_wt or wr_int) and not si570_i2c_master_wack;
wr_ack_int <= si570_i2c_master_wack;
when "1" =>
-- Submap ds18b20_onewire_master
ds18b20_onewire_master_wt <= (ds18b20_onewire_master_wt or wr_int) and not ds18b20_onewire_master_wack;
wr_ack_int <= ds18b20_onewire_master_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "1100" =>
case wb_i.adr(8 downto 7) is
when "00" =>
-- Submap fmc_spi_master
fmc_spi_master_wt <= (fmc_spi_master_wt or wr_int) and not fmc_spi_master_wack;
wr_ack_int <= fmc_spi_master_wack;
when "10" =>
-- Submap timetag_core
timetag_core_wt <= (timetag_core_wt or wr_int) and not timetag_core_wack;
wr_ack_int <= timetag_core_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_i.adr(12 downto 9) is
when "1000" =>
when "1010" =>
when "1011" =>
case wb_i.adr(8 downto 8) is
when "0" =>
when "1" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "1100" =>
case wb_i.adr(8 downto 7) is
when "00" =>
when "10" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int, rd_int, fmc_adc_100m_csr_i.dat, fmc_adc_100m_csr_rack, fmc_adc_100m_csr_rt, rd_int, fmc_adc_eic_i.dat, fmc_adc_eic_rack, fmc_adc_eic_rt, rd_int, si570_i2c_master_i.dat, si570_i2c_master_rack, si570_i2c_master_rt, rd_int, ds18b20_onewire_master_i.dat, ds18b20_onewire_master_rack, ds18b20_onewire_master_rt, rd_int, fmc_spi_master_i.dat, fmc_spi_master_rack, fmc_spi_master_rt, rd_int, timetag_core_i.dat, timetag_core_rack, timetag_core_rt) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
fmc_adc_100m_csr_re <= '0';
fmc_adc_eic_re <= '0';
si570_i2c_master_re <= '0';
ds18b20_onewire_master_re <= '0';
fmc_spi_master_re <= '0';
timetag_core_re <= '0';
case wb_i.adr(12 downto 9) is
when "1000" =>
-- Submap fmc_adc_100m_csr
fmc_adc_100m_csr_re <= rd_int;
wb_o.dat <= fmc_adc_100m_csr_i.dat;
rd_ack_int <= fmc_adc_100m_csr_rack;
when "1010" =>
-- Submap fmc_adc_eic
fmc_adc_eic_re <= rd_int;
wb_o.dat <= fmc_adc_eic_i.dat;
rd_ack_int <= fmc_adc_eic_rack;
when "1011" =>
case wb_i.adr(8 downto 8) is
when "0" =>
-- Submap si570_i2c_master
si570_i2c_master_re <= rd_int;
wb_o.dat <= si570_i2c_master_i.dat;
rd_ack_int <= si570_i2c_master_rack;
when "1" =>
-- Submap ds18b20_onewire_master
ds18b20_onewire_master_re <= rd_int;
wb_o.dat <= ds18b20_onewire_master_i.dat;
rd_ack_int <= ds18b20_onewire_master_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when "1100" =>
case wb_i.adr(8 downto 7) is
when "00" =>
-- Submap fmc_spi_master
fmc_spi_master_re <= rd_int;
wb_o.dat <= fmc_spi_master_i.dat;
rd_ack_int <= fmc_spi_master_rack;
when "10" =>
-- Submap timetag_core
timetag_core_re <= rd_int;
wb_o.dat <= timetag_core_i.dat;
rd_ack_int <= timetag_core_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.cheby 0 → 100644
View file @ 4e6378bd
memory-map:
name: spec_ref_fmc_adc_100m_mmap
bus: wb-32-be
description: SPEC FMC-ADC-100M memory map
size: 0x6000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
address: 0x2000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
description: a ROM containing the application metadata
- submap:
name: fmc_adc_mezzanine
address: 0x4000
description: FMC ADC Mezzanine
filename: fmc_adc_mezzanine_mmap.cheby
hdl/top/svec_ref_design/svec_carrier_csr.vhd → hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.vhd
View file @ 4e6378bd
-- Do not edit; this file was generated by Cheby using these options: -- Do not edit; this file was generated by Cheby using these options:
-- -i svec_carrier_csr.cheby --gen-hdl=svec_carrier_csr.vhd -- -i spec_ref_fmc_adc_100Ms_mmap.cheby --gen-hdl=spec_ref_fmc_adc_100Ms_mmap.vhd
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
package svec_carrier_csr_pkg is entity spec_ref_fmc_adc_100m_mmap is
type t_carrier_csr_master_out is record
ctrl_fp_leds_man : std_logic_vector(15 downto 0);
rst_fmc0 : std_logic;
rst_fmc1 : std_logic;
end record t_carrier_csr_master_out;
subtype t_carrier_csr_slave_in is t_carrier_csr_master_out;
type t_carrier_csr_slave_out is record
carrier_pcb_rev : std_logic_vector(4 downto 0);
carrier_reserved : std_logic_vector(10 downto 0);
carrier_type : std_logic_vector(15 downto 0);
stat_fmc0_pres : std_logic;
stat_fmc1_pres : std_logic;
stat_sys_pll_lck : std_logic;
stat_ddr0_cal_done : std_logic;
stat_ddr1_cal_done : std_logic;
end record t_carrier_csr_slave_out;
subtype t_carrier_csr_master_in is t_carrier_csr_slave_out;
end svec_carrier_csr_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.svec_carrier_csr_pkg.all;
entity svec_carrier_csr is
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
clk_i : in std_logic; clk_i : in std_logic;
wb_i : in t_wishbone_slave_in; wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out; wb_o : out t_wishbone_slave_out;
-- Wires and registers -- a ROM containing the application metadata
carrier_csr_i : in t_carrier_csr_master_in; metadata_i : in t_wishbone_master_in;
carrier_csr_o : out t_carrier_csr_master_out metadata_o : out t_wishbone_master_out;
-- FMC ADC Mezzanine
fmc_adc_mezzanine_i : in t_wishbone_master_in;
fmc_adc_mezzanine_o : out t_wishbone_master_out
); );
end svec_carrier_csr; end spec_ref_fmc_adc_100m_mmap;
architecture syn of svec_carrier_csr is architecture syn of spec_ref_fmc_adc_100m_mmap is
signal rd_int : std_logic; signal rd_int : std_logic;
signal wr_int : std_logic; signal wr_int : std_logic;
signal rd_ack_int : std_logic; signal rd_ack_int : std_logic;
...@@ -55,9 +32,18 @@ architecture syn of svec_carrier_csr is ...@@ -55,9 +32,18 @@ architecture syn of svec_carrier_csr is
signal ack_int : std_logic; signal ack_int : std_logic;
signal wb_rip : std_logic; signal wb_rip : std_logic;
signal wb_wip : std_logic; signal wb_wip : std_logic;
signal ctrl_fp_leds_man_reg : std_logic_vector(15 downto 0); signal metadata_re : std_logic;
signal rst_fmc0_reg : std_logic; signal metadata_wt : std_logic;
signal rst_fmc1_reg : std_logic; signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal fmc_adc_mezzanine_re : std_logic;
signal fmc_adc_mezzanine_wt : std_logic;
signal fmc_adc_mezzanine_rt : std_logic;
signal fmc_adc_mezzanine_tr : std_logic;
signal fmc_adc_mezzanine_wack : std_logic;
signal fmc_adc_mezzanine_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0); signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic; signal rd_ack1_int : std_logic;
begin begin
...@@ -94,38 +80,67 @@ begin ...@@ -94,38 +80,67 @@ begin
wb_o.err <= '0'; wb_o.err <= '0';
-- Assign outputs -- Assign outputs
carrier_csr_o.ctrl_fp_leds_man <= ctrl_fp_leds_man_reg;
carrier_csr_o.rst_fmc0 <= rst_fmc0_reg; -- Assignments for submap metadata
carrier_csr_o.rst_fmc1 <= rst_fmc1_reg; metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
end if;
end if;
end process;
metadata_o.cyc <= metadata_tr;
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & wb_i.adr(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= (others => '1');
metadata_o.we <= metadata_wt;
metadata_o.dat <= wb_i.dat;
-- Assignments for submap fmc_adc_mezzanine
fmc_adc_mezzanine_tr <= fmc_adc_mezzanine_wt or fmc_adc_mezzanine_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_adc_mezzanine_rt <= '0';
else
fmc_adc_mezzanine_rt <= (fmc_adc_mezzanine_rt or fmc_adc_mezzanine_re) and not fmc_adc_mezzanine_rack;
end if;
end if;
end process;
fmc_adc_mezzanine_o.cyc <= fmc_adc_mezzanine_tr;
fmc_adc_mezzanine_o.stb <= fmc_adc_mezzanine_tr;
fmc_adc_mezzanine_wack <= fmc_adc_mezzanine_i.ack and fmc_adc_mezzanine_wt;
fmc_adc_mezzanine_rack <= fmc_adc_mezzanine_i.ack and fmc_adc_mezzanine_rt;
fmc_adc_mezzanine_o.adr <= ((18 downto 0 => '0') & wb_i.adr(12 downto 2)) & (1 downto 0 => '0');
fmc_adc_mezzanine_o.sel <= (others => '1');
fmc_adc_mezzanine_o.we <= fmc_adc_mezzanine_wt;
fmc_adc_mezzanine_o.dat <= wb_i.dat;
-- Process for write requests. -- Process for write requests.
process (clk_i) begin process (clk_i) begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_n_i = '0' then if rst_n_i = '0' then
wr_ack_int <= '0'; wr_ack_int <= '0';
ctrl_fp_leds_man_reg <= "0000000000000000"; metadata_wt <= '0';
rst_fmc0_reg <= '0'; fmc_adc_mezzanine_wt <= '0';
rst_fmc1_reg <= '0';
else else
wr_ack_int <= '0'; wr_ack_int <= '0';
case wb_i.adr(3 downto 2) is metadata_wt <= '0';
when "00" => fmc_adc_mezzanine_wt <= '0';
-- Register carrier case wb_i.adr(14 downto 13) is
when "01" => when "01" =>
-- Register stat -- Submap metadata
metadata_wt <= (metadata_wt or wr_int) and not metadata_wack;
wr_ack_int <= metadata_wack;
when "10" => when "10" =>
-- Register ctrl -- Submap fmc_adc_mezzanine
if wr_int = '1' then fmc_adc_mezzanine_wt <= (fmc_adc_mezzanine_wt or wr_int) and not fmc_adc_mezzanine_wack;
ctrl_fp_leds_man_reg <= wb_i.dat(15 downto 0); wr_ack_int <= fmc_adc_mezzanine_wack;
end if;
wr_ack_int <= wr_int;
when "11" =>
-- Register rst
if wr_int = '1' then
rst_fmc0_reg <= wb_i.dat(0);
rst_fmc1_reg <= wb_i.dat(1);
end if;
wr_ack_int <= wr_int;
when others => when others =>
wr_ack_int <= wr_int; wr_ack_int <= wr_int;
end case; end case;
...@@ -140,28 +155,9 @@ begin ...@@ -140,28 +155,9 @@ begin
rd_ack1_int <= '0'; rd_ack1_int <= '0';
else else
reg_rdat_int <= (others => '0'); reg_rdat_int <= (others => '0');
case wb_i.adr(3 downto 2) is case wb_i.adr(14 downto 13) is
when "00" =>
-- carrier
reg_rdat_int(4 downto 0) <= carrier_csr_i.carrier_pcb_rev;
reg_rdat_int(15 downto 5) <= carrier_csr_i.carrier_reserved;
reg_rdat_int(31 downto 16) <= carrier_csr_i.carrier_type;
rd_ack1_int <= rd_int;
when "01" => when "01" =>
-- stat
reg_rdat_int(0) <= carrier_csr_i.stat_fmc0_pres;
reg_rdat_int(1) <= carrier_csr_i.stat_fmc1_pres;
reg_rdat_int(2) <= carrier_csr_i.stat_sys_pll_lck;
reg_rdat_int(3) <= carrier_csr_i.stat_ddr0_cal_done;
reg_rdat_int(4) <= carrier_csr_i.stat_ddr1_cal_done;
rd_ack1_int <= rd_int;
when "10" => when "10" =>
-- ctrl
reg_rdat_int(15 downto 0) <= ctrl_fp_leds_man_reg;
rd_ack1_int <= rd_int;
when "11" =>
-- rst
rd_ack1_int <= rd_int;
when others => when others =>
reg_rdat_int <= (others => 'X'); reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int; rd_ack1_int <= rd_int;
...@@ -171,26 +167,22 @@ begin ...@@ -171,26 +167,22 @@ begin
end process; end process;
-- Process for read requests. -- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int, rd_int, metadata_i.dat, metadata_rack, metadata_rt, rd_int, fmc_adc_mezzanine_i.dat, fmc_adc_mezzanine_rack, fmc_adc_mezzanine_rt) begin
-- By default ack read requests -- By default ack read requests
wb_o.dat <= (others => '0'); wb_o.dat <= (others => '0');
case wb_i.adr(3 downto 2) is metadata_re <= '0';
when "00" => fmc_adc_mezzanine_re <= '0';
-- carrier case wb_i.adr(14 downto 13) is
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" => when "01" =>
-- stat -- Submap metadata
wb_o.dat <= reg_rdat_int; metadata_re <= rd_int;
rd_ack_int <= rd_ack1_int; wb_o.dat <= metadata_i.dat;
rd_ack_int <= metadata_rack;
when "10" => when "10" =>
-- ctrl -- Submap fmc_adc_mezzanine
wb_o.dat <= reg_rdat_int; fmc_adc_mezzanine_re <= rd_int;
rd_ack_int <= rd_ack1_int; wb_o.dat <= fmc_adc_mezzanine_i.dat;
when "11" => rd_ack_int <= fmc_adc_mezzanine_rack;
-- rst
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others => when others =>
rd_ack_int <= rd_int; rd_ack_int <= rd_int;
end case; end case;
......
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby 0 → 100644
View file @ 4e6378bd
memory-map:
name: svec_ref_fmc_adc_100m_mmap
bus: wb-32-be
description: SPEC FMC-ADC-100M memory map
size: 0x8000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
address: 0x2000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
description: a ROM containing the application metadata
- submap:
name: fmc1_adc_mezzanine
address: 0x4000
description: FMC ADC Mezzanine slot 1
filename: fmc_adc_mezzanine_mmap.cheby
- submap:
name: fmc2_adc_mezzanine
address: 0x6000
description: FMC ADC Mezzanine slot 2
filename: fmc_adc_mezzanine_mmap.cheby
hdl/top/spec_ref_design/spec_carrier_csr.vhd → hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
View file @ 4e6378bd
-- Do not edit; this file was generated by Cheby using these options: -- Do not edit; this file was generated by Cheby using these options:
-- -i spec_carrier_csr.cheby --gen-hdl=spec_carrier_csr.vhd -- -i svec_ref_fmc_adc_100Ms_mmap.cheby --gen-hdl=svec_ref_fmc_adc_100Ms_mmap.vhd
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
package spec_carrier_csr_pkg is entity svec_ref_fmc_adc_100m_mmap is
type t_carrier_csr_master_out is record
ctrl_led_green : std_logic;
ctrl_led_red : std_logic;
rst_fmc0 : std_logic;
end record t_carrier_csr_master_out;
subtype t_carrier_csr_slave_in is t_carrier_csr_master_out;
type t_carrier_csr_slave_out is record
carrier_pcb_rev : std_logic_vector(3 downto 0);
carrier_reserved : std_logic_vector(11 downto 0);
carrier_type : std_logic_vector(15 downto 0);
stat_fmc_pres : std_logic;
stat_p2l_pll_lck : std_logic;
stat_sys_pll_lck : std_logic;
stat_ddr3_cal_done : std_logic;
end record t_carrier_csr_slave_out;
subtype t_carrier_csr_master_in is t_carrier_csr_slave_out;
end spec_carrier_csr_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.spec_carrier_csr_pkg.all;
entity spec_carrier_csr is
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
clk_i : in std_logic; clk_i : in std_logic;
wb_i : in t_wishbone_slave_in; wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out; wb_o : out t_wishbone_slave_out;
-- Wires and registers -- a ROM containing the application metadata
carrier_csr_i : in t_carrier_csr_master_in; metadata_i : in t_wishbone_master_in;
carrier_csr_o : out t_carrier_csr_master_out metadata_o : out t_wishbone_master_out;
-- FMC ADC Mezzanine slot 1
fmc1_adc_mezzanine_i : in t_wishbone_master_in;
fmc1_adc_mezzanine_o : out t_wishbone_master_out;
-- FMC ADC Mezzanine slot 2
fmc2_adc_mezzanine_i : in t_wishbone_master_in;
fmc2_adc_mezzanine_o : out t_wishbone_master_out
); );
end spec_carrier_csr; end svec_ref_fmc_adc_100m_mmap;
architecture syn of spec_carrier_csr is architecture syn of svec_ref_fmc_adc_100m_mmap is
signal rd_int : std_logic; signal rd_int : std_logic;
signal wr_int : std_logic; signal wr_int : std_logic;
signal rd_ack_int : std_logic; signal rd_ack_int : std_logic;
...@@ -54,9 +36,24 @@ architecture syn of spec_carrier_csr is ...@@ -54,9 +36,24 @@ architecture syn of spec_carrier_csr is
signal ack_int : std_logic; signal ack_int : std_logic;
signal wb_rip : std_logic; signal wb_rip : std_logic;
signal wb_wip : std_logic; signal wb_wip : std_logic;
signal ctrl_led_green_reg : std_logic; signal metadata_re : std_logic;
signal ctrl_led_red_reg : std_logic; signal metadata_wt : std_logic;
signal rst_fmc0_reg : std_logic; signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal fmc1_adc_mezzanine_re : std_logic;
signal fmc1_adc_mezzanine_wt : std_logic;
signal fmc1_adc_mezzanine_rt : std_logic;
signal fmc1_adc_mezzanine_tr : std_logic;
signal fmc1_adc_mezzanine_wack : std_logic;
signal fmc1_adc_mezzanine_rack : std_logic;
signal fmc2_adc_mezzanine_re : std_logic;
signal fmc2_adc_mezzanine_wt : std_logic;
signal fmc2_adc_mezzanine_rt : std_logic;
signal fmc2_adc_mezzanine_tr : std_logic;
signal fmc2_adc_mezzanine_wack : std_logic;
signal fmc2_adc_mezzanine_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0); signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic; signal rd_ack1_int : std_logic;
begin begin
...@@ -93,38 +90,93 @@ begin ...@@ -93,38 +90,93 @@ begin
wb_o.err <= '0'; wb_o.err <= '0';
-- Assign outputs -- Assign outputs
carrier_csr_o.ctrl_led_green <= ctrl_led_green_reg;
carrier_csr_o.ctrl_led_red <= ctrl_led_red_reg; -- Assignments for submap metadata
carrier_csr_o.rst_fmc0 <= rst_fmc0_reg; metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
end if;
end if;
end process;
metadata_o.cyc <= metadata_tr;
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & wb_i.adr(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= (others => '1');
metadata_o.we <= metadata_wt;
metadata_o.dat <= wb_i.dat;
-- Assignments for submap fmc1_adc_mezzanine
fmc1_adc_mezzanine_tr <= fmc1_adc_mezzanine_wt or fmc1_adc_mezzanine_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc1_adc_mezzanine_rt <= '0';
else
fmc1_adc_mezzanine_rt <= (fmc1_adc_mezzanine_rt or fmc1_adc_mezzanine_re) and not fmc1_adc_mezzanine_rack;
end if;
end if;
end process;
fmc1_adc_mezzanine_o.cyc <= fmc1_adc_mezzanine_tr;
fmc1_adc_mezzanine_o.stb <= fmc1_adc_mezzanine_tr;
fmc1_adc_mezzanine_wack <= fmc1_adc_mezzanine_i.ack and fmc1_adc_mezzanine_wt;
fmc1_adc_mezzanine_rack <= fmc1_adc_mezzanine_i.ack and fmc1_adc_mezzanine_rt;
fmc1_adc_mezzanine_o.adr <= ((18 downto 0 => '0') & wb_i.adr(12 downto 2)) & (1 downto 0 => '0');
fmc1_adc_mezzanine_o.sel <= (others => '1');
fmc1_adc_mezzanine_o.we <= fmc1_adc_mezzanine_wt;
fmc1_adc_mezzanine_o.dat <= wb_i.dat;
-- Assignments for submap fmc2_adc_mezzanine
fmc2_adc_mezzanine_tr <= fmc2_adc_mezzanine_wt or fmc2_adc_mezzanine_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc2_adc_mezzanine_rt <= '0';
else
fmc2_adc_mezzanine_rt <= (fmc2_adc_mezzanine_rt or fmc2_adc_mezzanine_re) and not fmc2_adc_mezzanine_rack;
end if;
end if;
end process;
fmc2_adc_mezzanine_o.cyc <= fmc2_adc_mezzanine_tr;
fmc2_adc_mezzanine_o.stb <= fmc2_adc_mezzanine_tr;
fmc2_adc_mezzanine_wack <= fmc2_adc_mezzanine_i.ack and fmc2_adc_mezzanine_wt;
fmc2_adc_mezzanine_rack <= fmc2_adc_mezzanine_i.ack and fmc2_adc_mezzanine_rt;
fmc2_adc_mezzanine_o.adr <= ((18 downto 0 => '0') & wb_i.adr(12 downto 2)) & (1 downto 0 => '0');
fmc2_adc_mezzanine_o.sel <= (others => '1');
fmc2_adc_mezzanine_o.we <= fmc2_adc_mezzanine_wt;
fmc2_adc_mezzanine_o.dat <= wb_i.dat;
-- Process for write requests. -- Process for write requests.
process (clk_i) begin process (clk_i) begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_n_i = '0' then if rst_n_i = '0' then
wr_ack_int <= '0'; wr_ack_int <= '0';
ctrl_led_green_reg <= '0'; metadata_wt <= '0';
ctrl_led_red_reg <= '0'; fmc1_adc_mezzanine_wt <= '0';
rst_fmc0_reg <= '0'; fmc2_adc_mezzanine_wt <= '0';
else else
wr_ack_int <= '0'; wr_ack_int <= '0';
case wb_i.adr(3 downto 2) is metadata_wt <= '0';
when "00" => fmc1_adc_mezzanine_wt <= '0';
-- Register carrier fmc2_adc_mezzanine_wt <= '0';
case wb_i.adr(14 downto 13) is
when "01" => when "01" =>
-- Register stat -- Submap metadata
metadata_wt <= (metadata_wt or wr_int) and not metadata_wack;
wr_ack_int <= metadata_wack;
when "10" => when "10" =>
-- Register ctrl -- Submap fmc1_adc_mezzanine
if wr_int = '1' then fmc1_adc_mezzanine_wt <= (fmc1_adc_mezzanine_wt or wr_int) and not fmc1_adc_mezzanine_wack;
ctrl_led_green_reg <= wb_i.dat(0); wr_ack_int <= fmc1_adc_mezzanine_wack;
ctrl_led_red_reg <= wb_i.dat(1);
end if;
wr_ack_int <= wr_int;
when "11" => when "11" =>
-- Register rst -- Submap fmc2_adc_mezzanine
if wr_int = '1' then fmc2_adc_mezzanine_wt <= (fmc2_adc_mezzanine_wt or wr_int) and not fmc2_adc_mezzanine_wack;
rst_fmc0_reg <= wb_i.dat(0); wr_ack_int <= fmc2_adc_mezzanine_wack;
end if;
wr_ack_int <= wr_int;
when others => when others =>
wr_ack_int <= wr_int; wr_ack_int <= wr_int;
end case; end case;
...@@ -139,28 +191,10 @@ begin ...@@ -139,28 +191,10 @@ begin
rd_ack1_int <= '0'; rd_ack1_int <= '0';
else else
reg_rdat_int <= (others => '0'); reg_rdat_int <= (others => '0');
case wb_i.adr(3 downto 2) is case wb_i.adr(14 downto 13) is
when "00" =>
-- carrier
reg_rdat_int(3 downto 0) <= carrier_csr_i.carrier_pcb_rev;
reg_rdat_int(15 downto 4) <= carrier_csr_i.carrier_reserved;
reg_rdat_int(31 downto 16) <= carrier_csr_i.carrier_type;
rd_ack1_int <= rd_int;
when "01" => when "01" =>
-- stat
reg_rdat_int(0) <= carrier_csr_i.stat_fmc_pres;
reg_rdat_int(1) <= carrier_csr_i.stat_p2l_pll_lck;
reg_rdat_int(2) <= carrier_csr_i.stat_sys_pll_lck;
reg_rdat_int(3) <= carrier_csr_i.stat_ddr3_cal_done;
rd_ack1_int <= rd_int;
when "10" => when "10" =>
-- ctrl
reg_rdat_int(0) <= ctrl_led_green_reg;
reg_rdat_int(1) <= ctrl_led_red_reg;
rd_ack1_int <= rd_int;
when "11" => when "11" =>
-- rst
rd_ack1_int <= rd_int;
when others => when others =>
reg_rdat_int <= (others => 'X'); reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int; rd_ack1_int <= rd_int;
...@@ -170,26 +204,28 @@ begin ...@@ -170,26 +204,28 @@ begin
end process; end process;
-- Process for read requests. -- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int, rd_int, metadata_i.dat, metadata_rack, metadata_rt, rd_int, fmc1_adc_mezzanine_i.dat, fmc1_adc_mezzanine_rack, fmc1_adc_mezzanine_rt, rd_int, fmc2_adc_mezzanine_i.dat, fmc2_adc_mezzanine_rack, fmc2_adc_mezzanine_rt) begin
-- By default ack read requests -- By default ack read requests
wb_o.dat <= (others => '0'); wb_o.dat <= (others => '0');
case wb_i.adr(3 downto 2) is metadata_re <= '0';
when "00" => fmc1_adc_mezzanine_re <= '0';
-- carrier fmc2_adc_mezzanine_re <= '0';
wb_o.dat <= reg_rdat_int; case wb_i.adr(14 downto 13) is
rd_ack_int <= rd_ack1_int;
when "01" => when "01" =>
-- stat -- Submap metadata
wb_o.dat <= reg_rdat_int; metadata_re <= rd_int;
rd_ack_int <= rd_ack1_int; wb_o.dat <= metadata_i.dat;
rd_ack_int <= metadata_rack;
when "10" => when "10" =>
-- ctrl -- Submap fmc1_adc_mezzanine
wb_o.dat <= reg_rdat_int; fmc1_adc_mezzanine_re <= rd_int;
rd_ack_int <= rd_ack1_int; wb_o.dat <= fmc1_adc_mezzanine_i.dat;
rd_ack_int <= fmc1_adc_mezzanine_rack;
when "11" => when "11" =>
-- rst -- Submap fmc2_adc_mezzanine
wb_o.dat <= reg_rdat_int; fmc2_adc_mezzanine_re <= rd_int;
rd_ack_int <= rd_ack1_int; wb_o.dat <= fmc2_adc_mezzanine_i.dat;
rd_ack_int <= fmc2_adc_mezzanine_rack;
when others => when others =>
rd_ack_int <= rd_int; rd_ack_int <= rd_int;
end case; end case;
......
hdl/rtl/timetag_core_regs.cheby → hdl/cheby/timetag_core_regs.cheby
View file @ 4e6378bd
...@@ -2,6 +2,7 @@ memory-map: ...@@ -2,6 +2,7 @@ memory-map:
bus: wb-32-be bus: wb-32-be
name: timetag_core_regs name: timetag_core_regs
description: Time-tagging core registers description: Time-tagging core registers
size: 0x80
comment: | comment: |
Wishbone slave for registers related to time-tagging core Wishbone slave for registers related to time-tagging core
x-hdl: x-hdl:
......
ddr3-sp6-core @ 1a129390
Subproject commit bb5b8f75e6f85335b43fef320375404686a74008 Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
general-cores @ 75d51c0b
Subproject commit eaacde903ef842af456c867947a0f1005f8bb4f3 Subproject commit 75d51c0b92015b48b176374f9a387b2d25fa8198
gn4124-core @ 91d5efac
Subproject commit 72adf76dab9a6fc33fbff7c86d786c31e175a46a Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
spec @ 4feaba67
Subproject commit 4feaba679fc13458a35066c9a5bfe9b31cb853cd
svec @ ce6b58a3
Subproject commit ce6b58a38c12da91494dafc2a77cce6f16c0762f
vme64x-core @ 6abee52c
Subproject commit 1204aeca29ec3c72b6fa615976f000c664c7d152 Subproject commit 6abee52c1b5f3c2a40e202eb9f5890c05e0d7f66
hdl/rtl/Manifest.py
View file @ 4e6378bd
...@@ -3,11 +3,12 @@ files = [ ...@@ -3,11 +3,12 @@ files = [
"fmc_adc_mezzanine_pkg.vhd", "fmc_adc_mezzanine_pkg.vhd",
"fmc_adc_100Ms_core.vhd", "fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_core_pkg.vhd", "fmc_adc_100Ms_core_pkg.vhd",
"fmc_adc_100Ms_csr.vhd",
"fmc_adc_aux_trigin.vhd",
"fmc_adc_aux_trigout.vhd",
"fmc_adc_eic.vhd", "fmc_adc_eic.vhd",
"offset_gain_s.vhd", "offset_gain_s.vhd",
"timetag_core_regs.vhd",
"timetag_core.vhd", "timetag_core.vhd",
"../cheby/fmc_adc_mezzanine_mmap.vhd",
"../cheby/fmc_adc_100Ms_csr.vhd",
"../cheby/fmc_adc_aux_trigin.vhd",
"../cheby/fmc_adc_aux_trigout.vhd",
"../cheby/timetag_core_regs.vhd",
] ]
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 4e6378bd
...@@ -350,7 +350,7 @@ begin ...@@ -350,7 +350,7 @@ begin
cmp_csr_wb_slave_adapter : wb_slave_adapter cmp_csr_wb_slave_adapter : wb_slave_adapter
generic map ( generic map (
g_master_use_struct => TRUE, g_master_use_struct => TRUE,
g_master_mode => CLASSIC, g_master_mode => PIPELINED,
g_master_granularity => BYTE, g_master_granularity => BYTE,
g_slave_use_struct => TRUE, g_slave_use_struct => TRUE,
g_slave_mode => g_WB_CSR_MODE, g_slave_mode => g_WB_CSR_MODE,
......
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 4e6378bd
...@@ -119,9 +119,6 @@ entity fmc_adc_mezzanine is ...@@ -119,9 +119,6 @@ entity fmc_adc_mezzanine is
mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID) mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic; -- Mezzanine system I2C data (EEPROM)
wr_tm_link_up_i : in std_logic; -- WR link status bit wr_tm_link_up_i : in std_logic; -- WR link status bit
wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit
wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds
...@@ -133,99 +130,27 @@ end fmc_adc_mezzanine; ...@@ -133,99 +130,27 @@ end fmc_adc_mezzanine;
architecture rtl of fmc_adc_mezzanine is architecture rtl of fmc_adc_mezzanine is
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- SDB crossbar constants declaration -- Constants declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves on the wishbone crossbar -- Number of slaves on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 7; constant c_NUM_WB_SLAVES : integer := 6;
-- Wishbone master(s)
constant c_WB_MASTER : integer := 0;
-- Wishbone slave(s) -- Wishbone slave(s)
constant c_WB_SLAVE_FMC_ADC : integer := 0; -- Mezzanine ADC core constant c_WB_SLAVE_FMC_ADC : integer := 0; -- Mezzanine ADC core
constant c_WB_SLAVE_FMC_SYS_I2C : integer := 1; -- Mezzanine system I2C interface (EEPROM) constant c_WB_SLAVE_FMC_EIC : integer := 1; -- Mezzanine interrupt controller
constant c_WB_SLAVE_FMC_EIC : integer := 2; -- Mezzanine interrupt controller constant c_WB_SLAVE_FMC_I2C : integer := 2; -- Mezzanine I2C controller
constant c_WB_SLAVE_FMC_I2C : integer := 3; -- Mezzanine I2C controller constant c_WB_SLAVE_FMC_ONEWIRE : integer := 3; -- Mezzanine onewire interface
constant c_WB_SLAVE_FMC_ONEWIRE : integer := 4; -- Mezzanine onewire interface constant c_WB_SLAVE_FMC_SPI : integer := 4; -- Mezzanine SPI interface
constant c_WB_SLAVE_FMC_SPI : integer := 5; -- Mezzanine SPI interface constant c_WB_SLAVE_TIMETAG : integer := 5; -- Mezzanine timetag core
constant c_WB_SLAVE_TIMETAG : integer := 6; -- Mezzanine timetag core
-- Devices sdb description
constant c_wb_adc_csr_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000001FF",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000608",
version => x"00000002",
date => x"20190730",
name => "WB-FMC-ADC-Core ")));
constant c_wb_timetag_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000007F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000604",
version => x"00000001",
date => x"20121116",
name => "WB-Timetag-Core ")));
constant c_wb_fmc_adc_eic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"26ec6086", -- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20131204",
name => "WB-FMC-ADC.EIC ")));
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) :=
(
c_WB_SLAVE_FMC_ADC => f_sdb_embed_device(c_wb_adc_csr_sdb, x"00001000"),
c_WB_SLAVE_FMC_SYS_I2C => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001400"),
c_WB_SLAVE_FMC_EIC => f_sdb_embed_device(c_wb_fmc_adc_eic_sdb, x"00001500"),
c_WB_SLAVE_FMC_I2C => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001600"),
c_WB_SLAVE_FMC_ONEWIRE => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001700"),
c_WB_SLAVE_FMC_SPI => f_sdb_embed_device(c_xwb_spi_sdb, x"00001800"),
c_WB_SLAVE_TIMETAG => f_sdb_embed_device(c_wb_timetag_sdb, x"00001900")
);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Signals declaration -- Signals declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Wishbone buse(s) from master(s) to crossbar slave port(s) -- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_out : t_wishbone_master_out;
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_in : t_wishbone_master_in;
-- Wishbone buse(s) from crossbar master port(s) to slave(s) -- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
...@@ -234,14 +159,6 @@ architecture rtl of fmc_adc_mezzanine is ...@@ -234,14 +159,6 @@ architecture rtl of fmc_adc_mezzanine is
signal wb_csr_out : t_wishbone_slave_in; signal wb_csr_out : t_wishbone_slave_in;
signal wb_csr_in : t_wishbone_slave_out; signal wb_csr_in : t_wishbone_slave_out;
-- Mezzanine system I2C for EEPROM
signal sys_scl_in : std_logic;
signal sys_scl_out : std_logic;
signal sys_scl_oe_n : std_logic;
signal sys_sda_in : std_logic;
signal sys_sda_out : std_logic;
signal sys_sda_oe_n : std_logic;
-- Mezzanine SPI -- Mezzanine SPI
signal spi_din_t : std_logic_vector(3 downto 0) := (others => '0'); signal spi_din_t : std_logic_vector(3 downto 0) := (others => '0');
signal spi_ss_t : std_logic_vector(7 downto 0); signal spi_ss_t : std_logic_vector(7 downto 0);
...@@ -254,10 +171,6 @@ architecture rtl of fmc_adc_mezzanine is ...@@ -254,10 +171,6 @@ architecture rtl of fmc_adc_mezzanine is
signal si570_sda_out : std_logic; signal si570_sda_out : std_logic;
signal si570_sda_oe_n : std_logic; signal si570_sda_oe_n : std_logic;
-- Mezzanine 1-wire
signal mezz_owr_en : std_logic_vector(0 downto 0);
signal mezz_owr_i : std_logic_vector(0 downto 0);
-- Interrupts (eic) -- Interrupts (eic)
signal ddr_wr_fifo_empty_d : std_logic; signal ddr_wr_fifo_empty_d : std_logic;
signal ddr_wr_fifo_empty_p : std_logic; signal ddr_wr_fifo_empty_p : std_logic;
...@@ -289,7 +202,7 @@ begin ...@@ -289,7 +202,7 @@ begin
cmp_fmc_wb_slave_adapter_in : wb_slave_adapter cmp_fmc_wb_slave_adapter_in : wb_slave_adapter
generic map ( generic map (
g_master_use_struct => TRUE, g_master_use_struct => TRUE,
g_master_mode => CLASSIC, g_master_mode => PIPELINED,
g_master_granularity => BYTE, g_master_granularity => BYTE,
g_slave_use_struct => TRUE, g_slave_use_struct => TRUE,
g_slave_mode => g_WB_MODE, g_slave_mode => g_WB_MODE,
...@@ -305,64 +218,33 @@ begin ...@@ -305,64 +218,33 @@ begin
-- Additional register to help timing -- Additional register to help timing
cmp_xwb_register : xwb_register cmp_xwb_register : xwb_register
generic map ( generic map (
g_WB_MODE => CLASSIC) g_WB_MODE => PIPELINED)
port map ( port map (
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i, clk_i => sys_clk_i,
slave_i => wb_csr_out, slave_i => wb_csr_out,
slave_o => wb_csr_in, slave_o => wb_csr_in,
master_i => cnx_master_in(c_WB_MASTER), master_i => cnx_master_in,
master_o => cnx_master_out(c_WB_MASTER)); master_o => cnx_master_out);
cmp_sdb_crossbar : xwb_sdb_crossbar cmp_crossbar : entity work.fmc_adc_mezzanine_mmap
generic map (
g_VERBOSE => FALSE,
g_num_masters => c_NUM_WB_MASTERS,
g_num_slaves => c_NUM_WB_SLAVES,
g_registered => TRUE,
g_wraparound => TRUE,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_wb_mode => PIPELINED,
g_sdb_addr => c_SDB_ADDRESS)
port map ( port map (
clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
slave_i => cnx_master_out, clk_i => sys_clk_i,
slave_o => cnx_master_in, wb_i => cnx_master_out,
master_i => cnx_slave_out, wb_o => cnx_master_in,
master_o => cnx_slave_in); fmc_adc_100m_csr_i => cnx_slave_out(c_WB_SLAVE_FMC_ADC),
fmc_adc_100m_csr_o => cnx_slave_in(c_WB_SLAVE_FMC_ADC),
------------------------------------------------------------------------------ fmc_adc_eic_i => cnx_slave_out(c_WB_SLAVE_FMC_EIC),
-- Mezzanine system managment I2C master fmc_adc_eic_o => cnx_slave_in(c_WB_SLAVE_FMC_EIC),
-- Access to mezzanine EEPROM si570_i2c_master_i => cnx_slave_out(c_WB_SLAVE_FMC_I2C),
------------------------------------------------------------------------------ si570_i2c_master_o => cnx_slave_in(c_WB_SLAVE_FMC_I2C),
cmp_fmc_sys_i2c : xwb_i2c_master ds18b20_onewire_master_i => cnx_slave_out(c_WB_SLAVE_FMC_ONEWIRE),
generic map( ds18b20_onewire_master_o => cnx_slave_in(c_WB_SLAVE_FMC_ONEWIRE),
g_interface_mode => CLASSIC, fmc_spi_master_i => cnx_slave_out(c_WB_SLAVE_FMC_SPI),
g_address_granularity => BYTE fmc_spi_master_o => cnx_slave_in(c_WB_SLAVE_FMC_SPI),
) timetag_core_i => cnx_slave_out(c_WB_SLAVE_TIMETAG),
port map ( timetag_core_o => cnx_slave_in(c_WB_SLAVE_TIMETAG));
clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_n_i,
slave_i => cnx_slave_in(c_WB_SLAVE_FMC_SYS_I2C),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC_SYS_I2C),
desc_o => open,
scl_pad_i(0) => sys_scl_in,
scl_pad_o(0) => sys_scl_out,
scl_padoen_o(0) => sys_scl_oe_n,
sda_pad_i(0) => sys_sda_in,
sda_pad_o(0) => sys_sda_out,
sda_padoen_o(0) => sys_sda_oe_n
);
-- Tri-state buffer for SDA and SCL
sys_scl_b <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
sys_scl_in <= sys_scl_b;
sys_sda_b <= sys_sda_out when sys_sda_oe_n = '0' else 'Z';
sys_sda_in <= sys_sda_b;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Mezzanine SPI master -- Mezzanine SPI master
...@@ -371,7 +253,7 @@ begin ...@@ -371,7 +253,7 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc_spi : xwb_spi cmp_fmc_spi : xwb_spi
generic map( generic map(
g_interface_mode => CLASSIC, g_interface_mode => PIPELINED,
g_address_granularity => BYTE g_address_granularity => BYTE
) )
port map ( port map (
...@@ -411,7 +293,7 @@ begin ...@@ -411,7 +293,7 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc_i2c : xwb_i2c_master cmp_fmc_i2c : xwb_i2c_master
generic map( generic map(
g_interface_mode => CLASSIC, g_interface_mode => PIPELINED,
g_address_granularity => BYTE g_address_granularity => BYTE
) )
port map ( port map (
...@@ -451,7 +333,7 @@ begin ...@@ -451,7 +333,7 @@ begin
g_SPARTAN6_USE_PLL => g_SPARTAN6_USE_PLL, g_SPARTAN6_USE_PLL => g_SPARTAN6_USE_PLL,
g_TRIG_DELAY_EXT => g_TRIG_DELAY_EXT, g_TRIG_DELAY_EXT => g_TRIG_DELAY_EXT,
g_TRIG_DELAY_SW => g_TRIG_DELAY_SW, g_TRIG_DELAY_SW => g_TRIG_DELAY_SW,
g_WB_CSR_MODE => CLASSIC, g_WB_CSR_MODE => PIPELINED,
g_WB_CSR_GRANULARITY => BYTE) g_WB_CSR_GRANULARITY => BYTE)
port map ( port map (
sys_clk_i => sys_clk_i, sys_clk_i => sys_clk_i,
...@@ -509,29 +391,17 @@ begin ...@@ -509,29 +391,17 @@ begin
-- DS18B20 (thermometer + unique ID) -- DS18B20 (thermometer + unique ID)
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc_onewire : xwb_onewire_master cmp_fmc_onewine : entity work.xwb_ds182x_readout
generic map( generic map (
g_interface_mode => CLASSIC, g_CLOCK_FREQ_KHZ => 125000,
g_address_granularity => BYTE, g_USE_INTERNAL_PPS => TRUE)
g_num_ports => 1, port map (
g_ow_btp_normal => "5.0", clk_i => sys_clk_i,
g_ow_btp_overdrive => "1.0"
)
port map(
clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
wb_i => cnx_slave_in(c_WB_SLAVE_FMC_ONEWIRE),
slave_i => cnx_slave_in(c_WB_SLAVE_FMC_ONEWIRE), wb_o => cnx_slave_out(c_WB_SLAVE_FMC_ONEWIRE),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC_ONEWIRE), pps_p_i => '0',
desc_o => open, onewire_b => mezz_one_wire_b);
owr_pwren_o => open,
owr_en_o => mezz_owr_en,
owr_i => mezz_owr_i
);
mezz_one_wire_b <= '0' when mezz_owr_en(0) = '1' else 'Z';
mezz_owr_i(0) <= mezz_one_wire_b;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- FMC0 interrupt controller -- FMC0 interrupt controller
......
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ 4e6378bd
...@@ -124,9 +124,6 @@ package fmc_adc_mezzanine_pkg is ...@@ -124,9 +124,6 @@ package fmc_adc_mezzanine_pkg is
mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID) mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic; -- Mezzanine system I2C data (EEPROM)
wr_tm_link_up_i : in std_logic; -- WR link status bit wr_tm_link_up_i : in std_logic; -- WR link status bit
wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit
wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds
......
hdl/syn/spec_ref_design_wr/Manifest.py
View file @ 4e6378bd
...@@ -9,29 +9,30 @@ syn_top = "spec_ref_fmc_adc_100Ms" ...@@ -9,29 +9,30 @@ syn_top = "spec_ref_fmc_adc_100Ms"
syn_project = syn_top + "_wr.xise" syn_project = syn_top + "_wr.xise"
syn_tool = "ise" syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
files = [ files = [
syn_top + "_wr.ucf", syn_top + "_wr.ucf",
"buildinfo_pkg.vhd",
] ]
modules = { modules = {
"local" : [ "local" : [
"../../top/spec_ref_design" "../../top/spec_ref_design"
], ],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
],
} }
fetchto="../../ip_cores" # Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank3_64b_32b" ] syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
syn_post_project_cmd = ( spec_base_ucf = ['wr', 'ddr3', 'onewire', 'spi']
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \ ctrls = ["bank3_64b_32b" ]
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
View file @ 4e6378bd
...@@ -2,292 +2,6 @@ ...@@ -2,292 +2,6 @@
# IO Constraints # IO Constraints
#=============================================================================== #===============================================================================
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "gn_rst_n_i" LOC = N20;
NET "gn_p2l_clk_n_i" LOC = M19;
NET "gn_p2l_clk_p_i" LOC = M20;
NET "gn_p2l_rdy_o" LOC = J16;
NET "gn_p2l_dframe_i" LOC = J22;
NET "gn_p2l_valid_i" LOC = L19;
NET "gn_p2l_data_i[15]" LOC = H19;
NET "gn_p2l_data_i[14]" LOC = F21;
NET "gn_p2l_data_i[13]" LOC = F22;
NET "gn_p2l_data_i[12]" LOC = E20;
NET "gn_p2l_data_i[11]" LOC = E22;
NET "gn_p2l_data_i[10]" LOC = J19;
NET "gn_p2l_data_i[9]" LOC = H20;
NET "gn_p2l_data_i[8]" LOC = K19;
NET "gn_p2l_data_i[7]" LOC = K18;
NET "gn_p2l_data_i[6]" LOC = G20;
NET "gn_p2l_data_i[5]" LOC = G22;
NET "gn_p2l_data_i[4]" LOC = K17;
NET "gn_p2l_data_i[3]" LOC = L17;
NET "gn_p2l_data_i[2]" LOC = H21;
NET "gn_p2l_data_i[1]" LOC = H22;
NET "gn_p2l_data_i[0]" LOC = K20;
NET "gn_p_wr_req_i[1]" LOC = M21;
NET "gn_p_wr_req_i[0]" LOC = M22;
NET "gn_p_wr_rdy_o[1]" LOC = K16;
NET "gn_p_wr_rdy_o[0]" LOC = L15;
NET "gn_rx_error_o" LOC = J17;
NET "gn_l2p_clk_n_o" LOC = K22;
NET "gn_l2p_clk_p_o" LOC = K21;
NET "gn_l2p_dframe_o" LOC = U22;
NET "gn_l2p_valid_o" LOC = T18;
NET "gn_l2p_edb_o" LOC = U20;
NET "gn_l2p_data_o[15]" LOC = Y21;
NET "gn_l2p_data_o[14]" LOC = W20;
NET "gn_l2p_data_o[13]" LOC = V20;
NET "gn_l2p_data_o[12]" LOC = V22;
NET "gn_l2p_data_o[11]" LOC = T19;
NET "gn_l2p_data_o[10]" LOC = T21;
NET "gn_l2p_data_o[9]" LOC = R22;
NET "gn_l2p_data_o[8]" LOC = P22;
NET "gn_l2p_data_o[7]" LOC = Y22;
NET "gn_l2p_data_o[6]" LOC = W22;
NET "gn_l2p_data_o[5]" LOC = V19;
NET "gn_l2p_data_o[4]" LOC = V21;
NET "gn_l2p_data_o[3]" LOC = T20;
NET "gn_l2p_data_o[2]" LOC = P18;
NET "gn_l2p_data_o[1]" LOC = P21;
NET "gn_l2p_data_o[0]" LOC = P16;
NET "gn_l2p_rdy_i" LOC = U19;
NET "gn_l_wr_rdy_i[1]" LOC = T22;
NET "gn_l_wr_rdy_i[0]" LOC = R20;
NET "gn_p_rd_d_rdy_i[1]" LOC = P19;
NET "gn_p_rd_d_rdy_i[0]" LOC = N16;
NET "gn_tx_error_i" LOC = M17;
NET "gn_vc_rdy_i[1]" LOC = B22;
NET "gn_vc_rdy_i[0]" LOC = B21;
NET "gn_gpio_b[1]" LOC = U16;
NET "gn_gpio_b[0]" LOC = AB19;
NET "gn_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "gn_p2l_clk_?_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_rx_error_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clk_?_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error_i" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_gpio_b[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# DDR Memory
#----------------------------------------
# DDR (bank 3)
NET "ddr_rzq_b" LOC = K7;
NET "ddr_we_n_o" LOC = H2;
NET "ddr_udqs_p_b" LOC = V2;
NET "ddr_udqs_n_b" LOC = V1;
NET "ddr_udm_o" LOC = P3;
NET "ddr_reset_n_o" LOC = E3;
NET "ddr_ras_n_o" LOC = M5;
NET "ddr_odt_o" LOC = L6;
NET "ddr_ldqs_p_b" LOC = N3;
NET "ddr_ldqs_n_b" LOC = N1;
NET "ddr_ldm_o" LOC = N4;
NET "ddr_cke_o" LOC = F2;
NET "ddr_ck_p_o" LOC = K4;
NET "ddr_ck_n_o" LOC = K3;
NET "ddr_cas_n_o" LOC = M4;
NET "ddr_dq_b[15]" LOC = Y1;
NET "ddr_dq_b[14]" LOC = Y2;
NET "ddr_dq_b[13]" LOC = W1;
NET "ddr_dq_b[12]" LOC = W3;
NET "ddr_dq_b[11]" LOC = U1;
NET "ddr_dq_b[10]" LOC = U3;
NET "ddr_dq_b[9]" LOC = T1;
NET "ddr_dq_b[8]" LOC = T2;
NET "ddr_dq_b[7]" LOC = M1;
NET "ddr_dq_b[6]" LOC = M2;
NET "ddr_dq_b[5]" LOC = L1;
NET "ddr_dq_b[4]" LOC = L3;
NET "ddr_dq_b[3]" LOC = P1;
NET "ddr_dq_b[2]" LOC = P2;
NET "ddr_dq_b[1]" LOC = R1;
NET "ddr_dq_b[0]" LOC = R3;
NET "ddr_ba_o[2]" LOC = H1;
NET "ddr_ba_o[1]" LOC = J1;
NET "ddr_ba_o[0]" LOC = J3;
NET "ddr_a_o[13]" LOC = J6;
NET "ddr_a_o[12]" LOC = F1;
NET "ddr_a_o[11]" LOC = E1;
NET "ddr_a_o[10]" LOC = J4;
NET "ddr_a_o[9]" LOC = G1;
NET "ddr_a_o[8]" LOC = G3;
NET "ddr_a_o[7]" LOC = K6;
NET "ddr_a_o[6]" LOC = L4;
NET "ddr_a_o[5]" LOC = M3;
NET "ddr_a_o[4]" LOC = H3;
NET "ddr_a_o[3]" LOC = M6;
NET "ddr_a_o[2]" LOC = K5;
NET "ddr_a_o[1]" LOC = K1;
NET "ddr_a_o[0]" LOC = K2;
# DDR IO standards and terminations
NET "ddr_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_p_b" IN_TERM = NONE;
NET "ddr_ldqs_n_b" IN_TERM = NONE;
NET "ddr_udqs_p_b" IN_TERM = NONE;
NET "ddr_udqs_n_b" IN_TERM = NONE;
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_rxn_i" LOC = C15;
NET "sfp_rxp_i" LOC = D15;
NET "sfp_txn_o" LOC = A16;
NET "sfp_txp_o" LOC = B16;
NET "sfp_los_i" LOC = D18;
NET "sfp_mod_def0_i" LOC = G15;
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_rate_select_o" LOC = H14;
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_fault_i" LOC = B18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "pll25dac_sync_n_o" LOC = A3;
NET "pll20dac_sync_n_o" LOC = B3;
NET "plldac_din_o" LOC = C4;
NET "plldac_sclk_o" LOC = A4;
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "spi_ncs_o" LOC = AA3;
NET "spi_sclk_o" LOC = Y20;
NET "spi_mosi_o" LOC = AB20;
NET "spi_miso_i" LOC = AA20;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS25";
NET "spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "spi_miso_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = B2;
NET "uart_rxd_i" LOC = A2;
NET "uart_txd_o" IOSTANDARD = "LVCMOS25";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer + unique ID
#----------------------------------------
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier front panel LEDs
#----------------------------------------
NET "led_sfp_red_o" LOC = D5;
NET "led_sfp_green_o" LOC = E5;
NET "led_sfp_red_o" IOSTANDARD = "LVCMOS25";
NET "led_sfp_green_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB revision
#----------------------------------------
NET "pcbrev_i[0]" LOC = P5;
NET "pcbrev_i[1]" LOC = P4;
NET "pcbrev_i[2]" LOC = AA2;
NET "pcbrev_i[3]" LOC = AA1;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# PCB Buttons and LEDs
#----------------------------------------
NET "button1_n_i" LOC = C22;
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;
NET "button1_n_i" IOSTANDARD = "LVCMOS18";
NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc_prsnt_m2c_n_i" LOC = AB14;
NET "fmc_scl_b" LOC = F7;
NET "fmc_sda_b" LOC = F8;
NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc_sda_b" IOSTANDARD = "LVCMOS25";
#---------------------------------------- #----------------------------------------
# FMC slot # FMC slot
#---------------------------------------- #----------------------------------------
...@@ -381,136 +95,50 @@ NET "adc_si570_sda_b" IOSTANDARD = "LVCMOS25"; ...@@ -381,136 +95,50 @@ NET "adc_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "adc_one_wire_b" IOSTANDARD = "LVCMOS25"; NET "adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#---------------------------------------- #----------------------------------------
# IOBs # PCB LEDs
#---------------------------------------- #----------------------------------------
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE; NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE;
#=============================================================================== #===============================================================================
# Timing Constraints # Timing constraints and exceptions
#=============================================================================== #===============================================================================
#---------------------------------------- # Tightly constrain the location and max delay from the external trigger input
# Clocks # to its synchroniser. This is needed to have consistent alignment between trigger
#---------------------------------------- # and data across implementations. Note that due to RLOC constraints in the
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_ref; # gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_ref; NET "cmp_fmc_adc_mezzanine/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 1.5 ns;
INST "cmp_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X30Y2;
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_ref" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp;
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
NET "adc_dco_p_i" TNM_NET = adc_dco;
NET "adc_dco_n_i" TNM_NET = adc_dco;
TIMESPEC TS_adc_dco = PERIOD "adc_dco" 2.5 ns HIGH 50%;
NET "gn_p2l_clk_p_i" TNM_NET = "p2l_clk";
NET "gn_p2l_clk_n_i" TNM_NET = "p2l_clk";
TIMESPEC TS_p2l_clk = PERIOD "p2l_clk" 5 ns HIGH 50%;
#----------------------------------------
# WR DMTD tweaks
#----------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#---------------------------------------- #----------------------------------------
# Xilinx MCB tweaks # IOB exceptions
#---------------------------------------- #----------------------------------------
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
# These are suggested by the Xilinx-generated MCB. INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "cmp_ddr_ctrl_bank?/*/c?_pll_lock" TIG;
NET "cmp_ddr_ctrl_bank?/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#---------------------------------------- #----------------------------------------
# Asynchronous resets # Clocks
#---------------------------------------- #----------------------------------------
NET "adc_dco_p_i" TNM_NET = adc_dco;
# GN4124 NET "adc_dco_n_i" TNM_NET = adc_dco;
NET "gn_rst_n_i" TIG; TIMESPEC TS_adc_dco = PERIOD "adc_dco" 2.5 ns HIGH 50%;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
# Ignore async reset to DDR controller
NET "ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#---------------------------------------- #----------------------------------------
# Cross-clock domain sync # Cross-clock domain sync
#---------------------------------------- #----------------------------------------
# Declaration of domains
NET "clk_sys_62m5" TNM_NET = sys_clk_62_5;
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_ddr_333m" TNM_NET = ddr_clk;
NET "cmp_xwrc_board_spec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk; NET "cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
#TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMEGRP "adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk"; TIMEGRP "adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk";
TIMESPEC TS_pci_sync_ffs = FROM pci_clk TO "pci_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
TIMESPEC TS_adc_sync_ffs = FROM fs_clk TO "adc_sync_ffs" TIG; TIMESPEC TS_adc_sync_ffs = FROM fs_clk TO "adc_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = "sync_reg";
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
#TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
TIMEGRP "adc_sync_reg" = "sync_reg" EXCEPT "fs_clk"; TIMEGRP "adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "adc_sync_reg" 10ns DATAPATHONLY; TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "adc_sync_reg" 10ns DATAPATHONLY;
# Tightly constrain the location and max delay from the external trigger input TIMESPEC TS_adc_sync_word = FROM sync_word TO fs_clk 30ns DATAPATHONLY;
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "cmp_fmc_adc_mezzanine/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 1.5 ns;
INST "cmp_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X30Y2;
hdl/syn/spec_ref_design_wr/syn_extra_steps.tcl
View file @ 4e6378bd
...@@ -27,6 +27,8 @@ xilinx::project set "Register Duplication Map" "On" ...@@ -27,6 +27,8 @@ xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal" #xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal" #xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project set "Keep Hierarchy" "Yes"
xilinx::project save xilinx::project save
xilinx::project close xilinx::project close
hdl/syn/svec_ref_design_wr/Manifest.py
View file @ 4e6378bd
...@@ -9,29 +9,30 @@ syn_top = "svec_ref_fmc_adc_100Ms" ...@@ -9,29 +9,30 @@ syn_top = "svec_ref_fmc_adc_100Ms"
syn_project = syn_top + "_wr.xise" syn_project = syn_top + "_wr.xise"
syn_tool = "ise" syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
files = [ files = [
syn_top + "_wr.ucf", syn_top + "_wr.ucf",
"buildinfo_pkg.vhd",
] ]
modules = { modules = {
"local" : [ "local" : [
"../../top/svec_ref_design" "../../top/svec_ref_design"
], ],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
],
} }
fetchto="../../ip_cores" # Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank4_64b_32b", "bank5_64b_32b"] syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
syn_post_project_cmd = ( svec_base_ucf = ['wr', 'ddr4', 'ddr5', 'led', 'gpio']
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \ ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
View file @ 4e6378bd
...@@ -2,424 +2,6 @@ ...@@ -2,424 +2,6 @@
# IO Constraints # IO Constraints
#=============================================================================== #===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_rst_n_i" LOC = P4;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y6;
NET "vme_ds_n_i[0]" LOC = Y7;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_o[7]" LOC = R7;
NET "vme_irq_o[6]" LOC = AH2;
NET "vme_irq_o[5]" LOC = AF2;
NET "vme_irq_o[4]" LOC = N9;
NET "vme_irq_o[3]" LOC = N10;
NET "vme_irq_o[2]" LOC = AH4;
NET "vme_irq_o[1]" LOC = AG4;
NET "vme_gap_i" LOC = M6;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[12]" LOC = T7;
NET "vme_data_b[11]" LOC = AG5;
NET "vme_data_b[10]" LOC = AE5;
NET "vme_data_b[9]" LOC = Y11;
NET "vme_data_b[8]" LOC = W11;
NET "vme_data_b[7]" LOC = AF6;
NET "vme_data_b[6]" LOC = AE6;
NET "vme_data_b[5]" LOC = Y8;
NET "vme_data_b[4]" LOC = Y9;
NET "vme_data_b[3]" LOC = AE7;
NET "vme_data_b[2]" LOC = AD7;
NET "vme_data_b[1]" LOC = AA9;
NET "vme_data_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[20]" LOC = AA4;
NET "vme_addr_b[19]" LOC = AA5;
NET "vme_addr_b[18]" LOC = Y1;
NET "vme_addr_b[17]" LOC = Y2;
NET "vme_addr_b[16]" LOC = Y3;
NET "vme_addr_b[15]" LOC = Y4;
NET "vme_addr_b[14]" LOC = AC1;
NET "vme_addr_b[13]" LOC = AC3;
NET "vme_addr_b[12]" LOC = AD1;
NET "vme_addr_b[11]" LOC = AD2;
NET "vme_addr_b[10]" LOC = AB3;
NET "vme_addr_b[9]" LOC = AB4;
NET "vme_addr_b[8]" LOC = AD3;
NET "vme_addr_b[7]" LOC = AD4;
NET "vme_addr_b[6]" LOC = AC4;
NET "vme_addr_b[5]" LOC = AC5;
NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_rst_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[*]" IOSTANDARD = "LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[*]" IOSTANDARD = "LVCMOS33";
NET "vme_gap_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[*]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[*]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[*]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[*]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# DDR Memory
#----------------------------------------
# DDR0 (bank 4)
NET "ddr_rzq_b[0]" LOC = L7;
NET "ddr_we_n_o[0]" LOC = F4;
NET "ddr_udqs_p_b[0]" LOC = K2;
NET "ddr_udqs_n_b[0]" LOC = K1;
NET "ddr_udm_o[0]" LOC = K4;
NET "ddr_reset_n_o[0]" LOC = G5;
NET "ddr_ras_n_o[0]" LOC = C1;
NET "ddr_odt_o[0]" LOC = E4;
NET "ddr_ldqs_p_b[0]" LOC = J5;
NET "ddr_ldqs_n_b[0]" LOC = J4;
NET "ddr_ldm_o[0]" LOC = K3;
NET "ddr_cke_o[0]" LOC = C4;
NET "ddr_ck_p_o[0]" LOC = E3;
NET "ddr_ck_n_o[0]" LOC = E1;
NET "ddr_cas_n_o[0]" LOC = B1;
NET "ddr_dq_b[15]" LOC = M1;
NET "ddr_dq_b[14]" LOC = M2;
NET "ddr_dq_b[13]" LOC = L1;
NET "ddr_dq_b[12]" LOC = L3;
NET "ddr_dq_b[11]" LOC = L4;
NET "ddr_dq_b[10]" LOC = L5;
NET "ddr_dq_b[9]" LOC = M3;
NET "ddr_dq_b[8]" LOC = M4;
NET "ddr_dq_b[7]" LOC = H1;
NET "ddr_dq_b[6]" LOC = H2;
NET "ddr_dq_b[5]" LOC = G1;
NET "ddr_dq_b[4]" LOC = G3;
NET "ddr_dq_b[3]" LOC = J1;
NET "ddr_dq_b[2]" LOC = J3;
NET "ddr_dq_b[1]" LOC = H3;
NET "ddr_dq_b[0]" LOC = H4;
NET "ddr_ba_o[2]" LOC = F3;
NET "ddr_ba_o[1]" LOC = D1;
NET "ddr_ba_o[0]" LOC = D2;
NET "ddr_a_o[13]" LOC = B5;
NET "ddr_a_o[12]" LOC = A4;
NET "ddr_a_o[11]" LOC = G4;
NET "ddr_a_o[10]" LOC = D5;
NET "ddr_a_o[9]" LOC = A2;
NET "ddr_a_o[8]" LOC = B2;
NET "ddr_a_o[7]" LOC = B3;
NET "ddr_a_o[6]" LOC = F1;
NET "ddr_a_o[5]" LOC = F2;
NET "ddr_a_o[4]" LOC = C5;
NET "ddr_a_o[3]" LOC = E5;
NET "ddr_a_o[2]" LOC = A3;
NET "ddr_a_o[1]" LOC = D3;
NET "ddr_a_o[0]" LOC = D4;
# DDR1 (bank 5)
NET "ddr_rzq_b[1]" LOC = G25;
NET "ddr_we_n_o[1]" LOC = E26;
NET "ddr_udqs_p_b[1]" LOC = K28;
NET "ddr_udqs_n_b[1]" LOC = K30;
NET "ddr_udm_o[1]" LOC = J27;
NET "ddr_reset_n_o[1]" LOC = C26;
NET "ddr_ras_n_o[1]" LOC = K26;
NET "ddr_odt_o[1]" LOC = E30;
NET "ddr_ldqs_p_b[1]" LOC = J29;
NET "ddr_ldqs_n_b[1]" LOC = J30;
NET "ddr_ldm_o[1]" LOC = J28;
NET "ddr_cke_o[1]" LOC = B29;
NET "ddr_ck_p_o[1]" LOC = E27;
NET "ddr_ck_n_o[1]" LOC = E28;
NET "ddr_cas_n_o[1]" LOC = K27;
NET "ddr_dq_b[31]" LOC = M30;
NET "ddr_dq_b[30]" LOC = M28;
NET "ddr_dq_b[29]" LOC = M27;
NET "ddr_dq_b[28]" LOC = M26;
NET "ddr_dq_b[27]" LOC = L30;
NET "ddr_dq_b[26]" LOC = L29;
NET "ddr_dq_b[25]" LOC = L28;
NET "ddr_dq_b[24]" LOC = L27;
NET "ddr_dq_b[23]" LOC = F30;
NET "ddr_dq_b[22]" LOC = F28;
NET "ddr_dq_b[21]" LOC = G28;
NET "ddr_dq_b[20]" LOC = G27;
NET "ddr_dq_b[19]" LOC = G30;
NET "ddr_dq_b[18]" LOC = G29;
NET "ddr_dq_b[17]" LOC = H30;
NET "ddr_dq_b[16]" LOC = H28;
NET "ddr_ba_o[5]" LOC = D26;
NET "ddr_ba_o[4]" LOC = C27;
NET "ddr_ba_o[3]" LOC = D27;
NET "ddr_a_o[27]" LOC = A28;
NET "ddr_a_o[26]" LOC = B30;
NET "ddr_a_o[25]" LOC = A26;
NET "ddr_a_o[24]" LOC = F26;
NET "ddr_a_o[23]" LOC = A27;
NET "ddr_a_o[22]" LOC = B27;
NET "ddr_a_o[21]" LOC = C29;
NET "ddr_a_o[20]" LOC = H27;
NET "ddr_a_o[19]" LOC = H26;
NET "ddr_a_o[18]" LOC = F27;
NET "ddr_a_o[17]" LOC = E29;
NET "ddr_a_o[16]" LOC = C30;
NET "ddr_a_o[15]" LOC = D30;
NET "ddr_a_o[14]" LOC = D28;
# DDR IO standards and terminations
NET "ddr_udqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_p_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_n_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_rzq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_we_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_udm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_reset_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ras_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_odt_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ldm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_cke_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_cas_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_p_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_n_b[*]" IN_TERM = NONE;
NET "ddr_udqs_p_b[*]" IN_TERM = NONE;
NET "ddr_udqs_n_b[*]" IN_TERM = NONE;
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" LOC = AD28;
NET "clk_20m_vcxo_i" LOC = V26;
NET "clk_125m_pllref_n_i" LOC = AB30;
NET "clk_125m_pllref_p_i" LOC = AB28;
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_txp_o" LOC = B23;
NET "sfp_txn_o" LOC = A23;
NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_i" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
NET "sfp_mod_def2_b" LOC = AA24;
NET "sfp_rate_select_o" LOC = W24;
NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "pll20dac_din_o" LOC = U28;
NET "pll20dac_sclk_o" LOC = AA28;
NET "pll20dac_sync_n_o" LOC = N28;
NET "pll25dac_din_o" LOC = P25;
NET "pll25dac_sclk_o" LOC = N27;
NET "pll25dac_sync_n_o" LOC = P26;
NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "spi_ncs_o" LOC = AG27;
NET "spi_sclk_o" LOC = AG26;
NET "spi_mosi_o" LOC = AH26;
NET "spi_miso_i" LOC = AH27;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS33";
NET "spi_sclk_o" IOSTANDARD = "LVCMOS33";
NET "spi_mosi_o" IOSTANDARD = "LVCMOS33";
NET "spi_miso_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = U27;
NET "uart_rxd_i" LOC = U25;
NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# 1-wire thermometer + unique ID
#----------------------------------------
NET "carrier_onewire_b" LOC = AC30;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Front panel LEDs
#----------------------------------------
NET "fp_led_line_oen_o[0]" LOC = AD26;
NET "fp_led_line_oen_o[1]" LOC = AD27;
NET "fp_led_line_o[0]" LOC = AC27;
NET "fp_led_line_o[1]" LOC = AC28;
NET "fp_led_column_o[0]" LOC = AE30;
NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_line_oen_o[*]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[*]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[*]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# Front panel IOs
#----------------------------------------
NET "fp_gpio1_o" LOC = T28;
NET "fp_gpio2_o" LOC = R30;
NET "fp_gpio3_o" LOC = V27;
NET "fp_gpio4_o" LOC = U29;
NET "fp_gpio1_a2b_o" LOC = T30;
NET "fp_gpio2_a2b_o" LOC = R29;
NET "fp_gpio34_a2b_o" LOC = V28;
NET "fp_term_en_o[1]" LOC = AB1;
NET "fp_term_en_o[2]" LOC = W5;
NET "fp_term_en_o[3]" LOC = W4;
NET "fp_term_en_o[4]" LOC = V4;
NET "fp_gpio1_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio2_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio3_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio4_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio1_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio2_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio34_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[*]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# PCB revision
#----------------------------------------
NET "pcbrev_i[4]" LOC = AF17;
NET "pcbrev_i[3]" LOC = AE17;
NET "pcbrev_i[2]" LOC = AD18;
NET "pcbrev_i[1]" LOC = AE20;
NET "pcbrev_i[0]" LOC = AD20;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier I2C EEPROM
#----------------------------------------
NET "carrier_scl_b" LOC = AC29;
NET "carrier_sda_b" LOC = AA30;
NET "carrier_scl_b" IOSTANDARD = "LVCMOS33";
NET "carrier_sda_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC slots management
#----------------------------------------
NET "fmc_prsnt_m2c_n_i[0]" LOC = N30;
NET "fmc_prsnt_m2c_n_i[1]" LOC = AE29;
NET "fmc_scl_b[0]" LOC = P28;
NET "fmc_scl_b[1]" LOC = W29;
NET "fmc_sda_b[0]" LOC = P30;
NET "fmc_sda_b[1]" LOC = V30;
NET "fmc_prsnt_m2c_n_i[*]" IOSTANDARD = "LVCMOS33";
NET "fmc_scl_b[*]" IOSTANDARD = "LVCMOS33";
NET "fmc_sda_b[*]" IOSTANDARD = "LVCMOS33";
#---------------------------------------- #----------------------------------------
# FMC slots # FMC slots
#---------------------------------------- #----------------------------------------
...@@ -577,136 +159,53 @@ NET "adc_si570_scl_b[*]" IOSTANDARD = "LVCMOS25"; ...@@ -577,136 +159,53 @@ NET "adc_si570_scl_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_si570_sda_b[*]" IOSTANDARD = "LVCMOS25"; NET "adc_si570_sda_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_one_wire_b[*]" IOSTANDARD = "LVCMOS25"; NET "adc_one_wire_b[*]" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "gen_fmc_mezzanine[?].*/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 2.0 ns;
INST "gen_fmc_mezzanine[0].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X66Y189;
INST "gen_fmc_mezzanine[1].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X69Y2;
#---------------------------------------- #----------------------------------------
# IOBs # IOB exceptions
#---------------------------------------- #----------------------------------------
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE; INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE; INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE;
#===============================================================================
# Timing Constraints
#===============================================================================
#---------------------------------------- #----------------------------------------
# Clocks # Clocks
#---------------------------------------- #----------------------------------------
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_ref;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_ref;
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_ref" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp;
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
NET "adc_dco_p_i[0]" TNM_NET = adc0_dco; NET "adc_dco_p_i[0]" TNM_NET = adc0_dco;
NET "adc_dco_n_i[0]" TNM_NET = adc0_dco; NET "adc_dco_n_i[0]" TNM_NET = adc0_dco;
TIMESPEC TS_adc0_dco = PERIOD "adc0_dco" 2.5 ns HIGH 50%; TIMESPEC TS_adc0_dco = PERIOD "adc0_dco" 2.5 ns HIGH 50%;
NET "adc_dco_p_i[1]" TNM_NET = adc1_dco; NET "adc_dco_p_i[1]" TNM_NET = adc1_dco;
NET "adc_dco_n_i[1]" TNM_NET = adc1_dco; NET "adc_dco_n_i[1]" TNM_NET = adc1_dco;
TIMESPEC TS_adc1_dco = PERIOD "adc1_dco" 2.5 ns HIGH 50%; TIMESPEC TS_adc1_dco = PERIOD "adc1_dco" 2.5 ns HIGH 50%;
#----------------------------------------
# WR DMTD tweaks
#----------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "gen_ddr_ctrl*/*/c?_pll_lock" TIG;
NET "gen_ddr_ctrl*/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "gen_ddr_ctrl*/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
NET "gen_ddr_ctrl*/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
# Ignore async reset to DDR controller
NET "ddr_rst[*]" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#---------------------------------------- #----------------------------------------
# Cross-clock domain sync # Cross-clock domain sync
#---------------------------------------- #----------------------------------------
# Declaration of domains
NET "clk_sys_62m5" TNM_NET = sys_clk_62_5;
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_ddr_333m" TNM_NET = ddr_clk;
NET "cmp_xwrc_board_svec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "gen_fmc_mezzanine[0].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk; NET "gen_fmc_mezzanine[0].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "gen_fmc_mezzanine[1].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk; NET "gen_fmc_mezzanine[1].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk;
NET "gen_ddr_ctrl[?].*/*/memc4_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "gen_ddr_ctrl[?].*/*/memc4_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMEGRP "adc0_sync_ffs" = "sync_ffs" EXCEPT "fs0_clk"; TIMEGRP "adc0_sync_ffs" = "sync_ffs" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_ffs" = "sync_ffs" EXCEPT "fs1_clk"; TIMEGRP "adc1_sync_ffs" = "sync_ffs" EXCEPT "fs1_clk";
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG; TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG; TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
#TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
TIMEGRP "adc0_sync_reg" = "sync_reg" EXCEPT "fs0_clk"; TIMEGRP "adc0_sync_reg" = "sync_reg" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_reg" = "sync_reg" EXCEPT "fs1_clk"; TIMEGRP "adc1_sync_reg" = "sync_reg" EXCEPT "fs1_clk";
TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 10ns DATAPATHONLY; TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc1_sync_reg = FROM fs1_clk TO "adc1_sync_reg" 10ns DATAPATHONLY; TIMESPEC TS_adc1_sync_reg = FROM fs1_clk TO "adc1_sync_reg" 10ns DATAPATHONLY;
# Tightly constrain the location and max delay from the external trigger input # No sync words used in FMC-ADC
# to its synchroniser. This is needed to have consistent alignment between trigger #TIMESPEC TS_adc0_sync_word = FROM sync_word TO fs0_clk 30ns DATAPATHONLY;
# and data across implementations. Note that due to RLOC constraints in the #TIMESPEC TS_adc1_sync_word = FROM sync_word TO fs1_clk 30ns DATAPATHONLY;
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "gen_fmc_mezzanine[?].*/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 2.0 ns;
INST "gen_fmc_mezzanine[0].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X66Y189;
INST "gen_fmc_mezzanine[1].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X69Y2;
hdl/syn/svec_ref_design_wr/syn_extra_steps.tcl
View file @ 4e6378bd
...@@ -27,6 +27,8 @@ xilinx::project set "Register Duplication Map" "On" ...@@ -27,6 +27,8 @@ xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal" #xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal" #xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
#xilinx::project set "Keep Hierarchy" "Yes"
xilinx::project save xilinx::project save
xilinx::project close xilinx::project close
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @ 4e6378bd
...@@ -92,8 +92,6 @@ module main; ...@@ -92,8 +92,6 @@ module main;
.si570_scl_b (), .si570_scl_b (),
.si570_sda_b (), .si570_sda_b (),
.mezz_one_wire_b (), .mezz_one_wire_b (),
.sys_scl_b (),
.sys_sda_b (),
.wr_tm_link_up_i (), .wr_tm_link_up_i (),
.wr_tm_time_valid_i (), .wr_tm_time_valid_i (),
.wr_tm_tai_i (), .wr_tm_tai_i (),
...@@ -180,12 +178,6 @@ module main; ...@@ -180,12 +178,6 @@ module main;
#1us; #1us;
// Check SDB
expected = 'h5344422d;
acc.read(`SDB_ADDR, val);
if (val != expected)
$fatal (1, "Unable to detect SDB header at offset 0x%8x.", `SDB_ADDR);
// Check status after reset // Check status after reset
expected = 'h19; expected = 'h19;
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val); acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
......
hdl/testbench/fmc_adc_mezzanine/run.do
View file @ 4e6378bd
vsim -quiet -L unisim work.main vsim -quiet -L unisim work.main -voptargs=+acc
set StdArithNoWarnings 1 set StdArithNoWarnings 1
set NumericStdNoWarnings 1 set NumericStdNoWarnings 1
......
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @ 4e6378bd
`define FMC_ADC_100MS_CSR_SIZE 344 `define FMC_ADC_100MS_CSR_SIZE 512
`define ADDR_FMC_ADC_100MS_CSR_CTL 'h0 `define ADDR_FMC_ADC_100MS_CSR_CTL 'h0
`define FMC_ADC_100MS_CSR_CTL_FSM_CMD_OFFSET 0 `define FMC_ADC_100MS_CSR_CTL_FSM_CMD_OFFSET 0
`define FMC_ADC_100MS_CSR_CTL_FSM_CMD 'h3 `define FMC_ADC_100MS_CSR_CTL_FSM_CMD 'h3
......
hdl/testbench/include/fmc_adc_mezzanine_mmap.v 0 → 100644
View file @ 4e6378bd
`define FMC_ADC_MEZZANINE_MMAP_SIZE 8192
`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 'h1000
`define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512
`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 'h1500
`define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC_SIZE 16
`define ADDR_FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 'h1600
`define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER_SIZE 256
`define ADDR_FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 'h1700
`define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 16
`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 'h1800
`define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER_SIZE 32
`define ADDR_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 'h1900
`define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE_SIZE 128
hdl/testbench/include/spec_ref_fmc_adc_100Ms_mmap.v 0 → 100644
View file @ 4e6378bd
`define SPEC_REF_FMC_ADC_100M_MMAP_SIZE 24576
`define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_METADATA 'h2000
`define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
`define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE 'h4000
`define SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE_SIZE 8192
hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v 0 → 100644
View file @ 4e6378bd
`define SVEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_METADATA 'h2000
`define SVEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 'h4000
`define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
`define ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 'h6000
`define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
hdl/testbench/include/timetag_core_regs.v
View file @ 4e6378bd
`define TIMETAG_CORE_REGS_SIZE 72 `define TIMETAG_CORE_REGS_SIZE 128
`define ADDR_TIMETAG_CORE_REGS_SECONDS_UPPER 'h0 `define ADDR_TIMETAG_CORE_REGS_SECONDS_UPPER 'h0
`define TIMETAG_CORE_REGS_SECONDS_UPPER_OFFSET 0 `define TIMETAG_CORE_REGS_SECONDS_UPPER_OFFSET 0
`define TIMETAG_CORE_REGS_SECONDS_UPPER 'hff `define TIMETAG_CORE_REGS_SECONDS_UPPER 'hff
......
hdl/testbench/svec_ref_design/.gitignore
View file @ 4e6378bd
...@@ -4,3 +4,4 @@ transcript ...@@ -4,3 +4,4 @@ transcript
vsim.wlf vsim.wlf
NullFile NullFile
modelsim.ini modelsim.ini
buildinfo_pkg.vhd
hdl/testbench/svec_ref_design/Manifest.py
View file @ 4e6378bd
board = "svec" board = "svec"
sim_tool = "modelsim" sim_tool = "modelsim"
top_module = "main" sim_top = "main"
action = "simulation" action = "simulation"
target = "xilinx" target = "xilinx"
syn_device = "xc6slx150t" syn_device = "xc6slx150t"
vcom_opt = "-93 -mixedsvvh" vcom_opt = "-93 -mixedsvvh"
fetchto = "../../ip_cores" # Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
include_dirs = [ include_dirs = [
"../include", "../include",
...@@ -19,19 +22,19 @@ include_dirs = [ ...@@ -19,19 +22,19 @@ include_dirs = [
files = [ files = [
"main.sv", "main.sv",
"synthesis_descriptor.vhd", "buildinfo_pkg.vhd",
] ]
modules = { modules = {
"local" : [ "local" : [
"../../top/svec_ref_design", "../../top/svec_ref_design",
], ],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
],
} }
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank4_64b_32b", "bank5_64b_32b"] ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/testbench/svec_ref_design/main.sv
View file @ 4e6378bd
...@@ -5,9 +5,8 @@ ...@@ -5,9 +5,8 @@
`include "fmc_adc_100Ms_csr.v" `include "fmc_adc_100Ms_csr.v"
`define VME_OFFSET 'h80000000 `define VME_OFFSET 'h80000000
`define ADC_OFFSET 'h2000 `define ADC_OFFSET 'h4000
`define SDB_ADDR `VME_OFFSET + 0
`define CSR_BASE `VME_OFFSET + `ADC_OFFSET + 'h1000 `define CSR_BASE `VME_OFFSET + `ADC_OFFSET + 'h1000
`define OWC_BASE `VME_OFFSET + `ADC_OFFSET + 'h1700 `define OWC_BASE `VME_OFFSET + `ADC_OFFSET + 'h1700
`define TAG_BASE `VME_OFFSET + `ADC_OFFSET + 'h1900 `define TAG_BASE `VME_OFFSET + `ADC_OFFSET + 'h1900
...@@ -62,8 +61,7 @@ module main; ...@@ -62,8 +61,7 @@ module main;
svec_ref_fmc_adc_100Ms svec_ref_fmc_adc_100Ms
#( #(
.g_SIMULATION(1), .g_SIMULATION(1)
.g_CALIB_SOFT_IP("FALSE")
) )
DUT DUT
( (
...@@ -83,7 +81,7 @@ module main; ...@@ -83,7 +81,7 @@ module main;
.adc_outb_p_i (adc_dat_even), .adc_outb_p_i (adc_dat_even),
.adc_outb_n_i (~adc_dat_even), .adc_outb_n_i (~adc_dat_even),
.vme_as_n_i (VME_AS_n), .vme_as_n_i (VME_AS_n),
.vme_rst_n_i (VME_RST_n), .vme_sysreset_n_i (VME_RST_n),
.vme_write_n_i (VME_WRITE_n), .vme_write_n_i (VME_WRITE_n),
.vme_am_i (VME_AM), .vme_am_i (VME_AM),
.vme_ds_n_i (VME_DS_n), .vme_ds_n_i (VME_DS_n),
...@@ -105,27 +103,50 @@ module main; ...@@ -105,27 +103,50 @@ module main;
.vme_data_oe_n_o (VME_DATA_OE_N), .vme_data_oe_n_o (VME_DATA_OE_N),
.vme_addr_dir_o (VME_ADDR_DIR), .vme_addr_dir_o (VME_ADDR_DIR),
.vme_addr_oe_n_o (VME_ADDR_OE_N), .vme_addr_oe_n_o (VME_ADDR_OE_N),
.ddr_reset_n_o (ddr_reset_n), .ddr4_reset_n_o (ddr_reset_n[0]),
.ddr_ck_p_o (ddr_ck_p), .ddr4_ck_p_o (ddr_ck_p[0]),
.ddr_ck_n_o (ddr_ck_n), .ddr4_ck_n_o (ddr_ck_n[0]),
.ddr_cke_o (ddr_cke), .ddr4_cke_o (ddr_cke[0]),
.ddr_ras_n_o (ddr_ras_n), .ddr4_ras_n_o (ddr_ras_n[0]),
.ddr_cas_n_o (ddr_cas_n), .ddr4_cas_n_o (ddr_cas_n[0]),
.ddr_we_n_o (ddr_we_n), .ddr4_we_n_o (ddr_we_n[0]),
.ddr_udm_o (ddr_dm[1]), .ddr4_udm_o (ddr_dm[1][0]),
.ddr_ldm_o (ddr_dm[0]), .ddr4_ldm_o (ddr_dm[0][0]),
.ddr_ba_o (ddr_ba), .ddr4_ba_o (ddr_ba[2:0]),
.ddr_a_o (ddr_a), .ddr4_a_o (ddr_a[13:0]),
.ddr_dq_b (ddr_dq), .ddr4_dq_b (ddr_dq[15:0]),
.ddr_udqs_p_b (ddr_dqs_p[1]), .ddr4_udqs_p_b (ddr_dqs_p[1][0]),
.ddr_udqs_n_b (ddr_dqs_n[1]), .ddr4_udqs_n_b (ddr_dqs_n[1][0]),
.ddr_ldqs_p_b (ddr_dqs_p[0]), .ddr4_ldqs_p_b (ddr_dqs_p[0][0]),
.ddr_ldqs_n_b (ddr_dqs_n[0]), .ddr4_ldqs_n_b (ddr_dqs_n[0][0]),
.ddr_odt_o (ddr_odt), .ddr4_odt_o (ddr_odt[0]),
.ddr_rzq_b (ddr_rzq) .ddr4_rzq_b (ddr_rzq[0]),
.ddr5_reset_n_o (ddr_reset_n[1]),
.ddr5_ck_p_o (ddr_ck_p[1]),
.ddr5_ck_n_o (ddr_ck_n[1]),
.ddr5_cke_o (ddr_cke[1]),
.ddr5_ras_n_o (ddr_ras_n[1]),
.ddr5_cas_n_o (ddr_cas_n[1]),
.ddr5_we_n_o (ddr_we_n[1]),
.ddr5_udm_o (ddr_dm[1][1]),
.ddr5_ldm_o (ddr_dm[0][1]),
.ddr5_ba_o (ddr_ba[5:3]),
.ddr5_a_o (ddr_a[27:14]),
.ddr5_dq_b (ddr_dq[31:16]),
.ddr5_udqs_p_b (ddr_dqs_p[1][1]),
.ddr5_udqs_n_b (ddr_dqs_n[1][1]),
.ddr5_ldqs_p_b (ddr_dqs_p[0][1]),
.ddr5_ldqs_n_b (ddr_dqs_n[0][1]),
.ddr5_odt_o (ddr_odt[1]),
.ddr5_rzq_b (ddr_rzq[1])
); );
ddr3 ddr3 #
(
.DEBUG(0),
.check_strict_timing(0),
.check_strict_mrbits(0)
)
cmp_ddr0 cmp_ddr0
( (
.rst_n (ddr_reset_n[0]), .rst_n (ddr_reset_n[0]),
...@@ -142,10 +163,16 @@ module main; ...@@ -142,10 +163,16 @@ module main;
.dq (ddr_dq[15:0]), .dq (ddr_dq[15:0]),
.dqs ({ddr_dqs_p[1][0],ddr_dqs_p[0][0]}), .dqs ({ddr_dqs_p[1][0],ddr_dqs_p[0][0]}),
.dqs_n ({ddr_dqs_n[1][0],ddr_dqs_n[0][0]}), .dqs_n ({ddr_dqs_n[1][0],ddr_dqs_n[0][0]}),
.odt (ddr_odt[0]) .odt (ddr_odt[0]),
.tdqs_n ()
); );
ddr3 ddr3 #
(
.DEBUG(0),
.check_strict_timing(0),
.check_strict_mrbits(0)
)
cmp_ddr1 cmp_ddr1
( (
.rst_n (ddr_reset_n[1]), .rst_n (ddr_reset_n[1]),
...@@ -162,7 +189,8 @@ module main; ...@@ -162,7 +189,8 @@ module main;
.dq (ddr_dq[31:16]), .dq (ddr_dq[31:16]),
.dqs ({ddr_dqs_p[1][1],ddr_dqs_p[0][1]}), .dqs ({ddr_dqs_p[1][1],ddr_dqs_p[0][1]}),
.dqs_n ({ddr_dqs_n[1][1],ddr_dqs_n[0][1]}), .dqs_n ({ddr_dqs_n[1][1],ddr_dqs_n[0][1]}),
.odt (ddr_odt[1]) .odt (ddr_odt[1]),
.tdqs_n ()
); );
int adc_div = 0; int adc_div = 0;
...@@ -233,6 +261,7 @@ module main; ...@@ -233,6 +261,7 @@ module main;
acc.set_default_modifiers(A32 | D32 | SINGLE); acc.set_default_modifiers(A32 | D32 | SINGLE);
endtask // init_vme64x_core endtask // init_vme64x_core
task adc_status_print (input uint64_t val); task adc_status_print (input uint64_t val);
string msg; string msg;
msg = $sformatf ("<%t> ADC STATUS: FSM_STATE=%0d, PLL_LOCKED=%0d, PLL_SYNCED=%0d, CFG_OK=%0d", msg = $sformatf ("<%t> ADC STATUS: FSM_STATE=%0d, PLL_LOCKED=%0d, PLL_SYNCED=%0d, CFG_OK=%0d",
...@@ -262,18 +291,6 @@ module main; ...@@ -262,18 +291,6 @@ module main;
#1us; #1us;
expected = 'h5344422d;
acc.read(`SDB_ADDR, val);
if (val != expected)
$fatal (1, "Unable to detect SDB header at offset 0x%8x (got 0x%8x, expected 0x%8x).",
`SDB_ADDR, val , expected);
expected = 'h5344422d;
acc.read(`ADC_OFFSET+`SDB_ADDR, val);
if (val != expected)
$fatal (1, "Unable to detect SDB header at offset 0x%8x (got 0x%8x, expected 0x%8x).",
`ADC_OFFSET+`SDB_ADDR, val , expected);
expected = 'h19; expected = 'h19;
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val); acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
if (val != expected) if (val != expected)
...@@ -383,7 +400,7 @@ module main; ...@@ -383,7 +400,7 @@ module main;
// set time trigger // set time trigger
acc.write(`TAG_BASE + 'h0c, 'h00000032); // timetag core seconds high acc.write(`TAG_BASE + 'h0c, 'h00000032); // timetag core seconds high
acc.write(`TAG_BASE + 'h10, 'h00005a34); // timetag core seconds low acc.write(`TAG_BASE + 'h10, 'h00005a34); // timetag core seconds low
acc.write(`TAG_BASE + 'h14, 'h00001000); // timetag core ticks acc.write(`TAG_BASE + 'h14, 'h00001100); // timetag core ticks
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000010); acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000010);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000080); acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000080);
...@@ -432,5 +449,17 @@ module main; ...@@ -432,5 +449,17 @@ module main;
end end
initial begin
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.inst_svec_base.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT.inst_svec_base.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT.inst_svec_base.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
end // initial begin
endmodule // main endmodule // main
hdl/testbench/svec_ref_design/run.do
View file @ 4e6378bd
vsim -quiet -t 10fs -L unisim work.main -novopt vsim -quiet -t 10fs -L unisim work.main -voptargs=+acc -suppress 143,1270,8617,8683,8684,8822
set StdArithNoWarnings 1 set StdArithNoWarnings 1
set NumericStdNoWarnings 1 set NumericStdNoWarnings 1
......
hdl/testbench/svec_ref_design/run_ci.do
View file @ 4e6378bd
vsim -quiet -t 10fs -L unisim work.main vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822
set StdArithNoWarnings 1 set StdArithNoWarnings 1
set NumericStdNoWarnings 1 set NumericStdNoWarnings 1
......
hdl/top/spec_ref_design/Makefile deleted 100644 → 0
View file @ d98dbd10
SIM =../../testbench/include
DOC =../../../doc/manual
SW =../../../software/include/hw
SOURCES = $(wildcard *.cheby)
TARGETS = $(SOURCES:.cheby=.vhd)
all: $(TARGETS)
.PHONY: $(TARGETS)
$(TARGETS): %.vhd : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@
@cheby -i $< \
--gen-doc=$(DOC)/$(@:.vhd=.html) \
--gen-consts=$(SIM)/$(@:.vhd=.v) \
--gen-c=$(SW)/$(@:.vhd=.h)
hdl/top/spec_ref_design/Manifest.py
View file @ 4e6378bd
files = [ files = [
"spec_ref_fmc_adc_100Ms.vhd", "spec_ref_fmc_adc_100Ms.vhd",
"spec_carrier_csr.vhd", "../../cheby/spec_ref_fmc_adc_100Ms_mmap.vhd",
"dma_eic.vhd",
] ]
fetchto = "../../ip_cores"
modules = { modules = {
"local" : [ "local" : [
"../../../", "../../../",
], ],
"git" : [
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/spec.git",
],
} }
hdl/top/spec_ref_design/dma_eic.vhd deleted 100644 → 0
View file @ d98dbd10
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for GN4124 DMA enhanced interrupt controller
---------------------------------------------------------------------------------------
-- File : ../rtl/dma_eic.vhd
-- Author : auto-generated by wbgen2 from dma_eic.wb
-- Created : Thu Jun 16 16:45:19 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dma_eic.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity dma_eic is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_dma_done_i : in std_logic;
irq_dma_error_i : in std_logic
);
end dma_eic;
architecture syn of dma_eic is
signal eic_idr_int : std_logic_vector(1 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(1 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(1 downto 0);
signal eic_isr_clear_int : std_logic_vector(1 downto 0);
signal eic_isr_status_int : std_logic_vector(1 downto 0);
signal eic_irq_ack_int : std_logic_vector(1 downto 0);
signal eic_isr_write_int : std_logic ;
signal irq_inputs_vector_int : std_logic_vector(1 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
end if;
rddata_reg(1 downto 0) <= eic_imr_int(1 downto 0);
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(1 downto 0) <= eic_isr_status_int(1 downto 0);
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(1 downto 0) <= wrdata_reg(1 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(1 downto 0) <= wrdata_reg(1 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(1 downto 0) <= wrdata_reg(1 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 2,
g_irq00_mode => 0,
g_irq01_mode => 0,
g_irq02_mode => 0,
g_irq03_mode => 0,
g_irq04_mode => 0,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
g_irq0d_mode => 0,
g_irq0e_mode => 0,
g_irq0f_mode => 0,
g_irq10_mode => 0,
g_irq11_mode => 0,
g_irq12_mode => 0,
g_irq13_mode => 0,
g_irq14_mode => 0,
g_irq15_mode => 0,
g_irq16_mode => 0,
g_irq17_mode => 0,
g_irq18_mode => 0,
g_irq19_mode => 0,
g_irq1a_mode => 0,
g_irq1b_mode => 0,
g_irq1c_mode => 0,
g_irq1d_mode => 0,
g_irq1e_mode => 0,
g_irq1f_mode => 0
)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int,
reg_imr_o => eic_imr_int,
reg_ier_i => eic_ier_int,
reg_ier_wr_stb_i => eic_ier_write_int,
reg_idr_i => eic_idr_int,
reg_idr_wr_stb_i => eic_idr_write_int,
reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_dma_done_i;
irq_inputs_vector_int(1) <= irq_dma_error_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/top/spec_ref_design/spec_carrier_csr.cheby deleted 100644 → 0
View file @ d98dbd10
memory-map:
bus: wb-32-be
name: spec_carrier_csr
description: Carrier control and status registers
comment: |
Wishbone slave for control and status registers related to the FMC carrier
x-hdl:
busgroup: True
iogroup: carrier_csr
children:
- reg:
name: carrier
address: 0x00000000
width: 32
access: ro
description: Carrier type and PCB version
children:
- field:
name: pcb_rev
range: 3-0
description: PCB revision
comment: |
Binary coded PCB layout revision.
- field:
name: reserved
range: 15-4
description: Reserved register
comment: |
Ignore on read, write with 0's.
- field:
name: type
range: 31-16
description: Carrier type
comment: |
Carrier type identifier
1 = SPEC
2 = SVEC
3 = VFC
4 = SPEXI
- reg:
name: stat
address: 0x00000004
width: 32
access: ro
description: Status
children:
- field:
name: fmc_pres
range: 0
description: FMC presence
comment: |
0: FMC slot is populated
1: FMC slot is not populated.
- field:
name: p2l_pll_lck
range: 1
description: GN4142 core P2L PLL status
comment: |
0: not locked
1: locked.
- field:
name: sys_pll_lck
range: 2
description: System clock PLL status
comment: |
0: not locked
1: locked.
- field:
name: ddr3_cal_done
range: 3
description: DDR3 calibration status
comment: |
0: not done
1: done.
- reg:
name: ctrl
address: 0x00000008
width: 32
access: rw
description: Control
children:
- field:
name: led_green
range: 0
description: Green LED
comment: |
Manual control of the front panel green LED (unused in the fmc-adc application)
- field:
name: led_red
range: 1
description: Red LED
comment: |
Manual control of the front panel red LED (unused in the fmc-adc application)
- reg:
name: rst
address: 0x0000000c
width: 32
access: wo
description: Reset Register
comment: |
Controls software reset of the mezzanine including the ddr interface and the time-tagging core.
children:
- field:
name: fmc0
range: 0
description: State of the reset line
comment: |
write 0: Normal FMC operation
write 1: FMC is held in reset
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
View file @ 4e6378bd
...@@ -35,22 +35,15 @@ use UNISIM.vcomponents.all; ...@@ -35,22 +35,15 @@ use UNISIM.vcomponents.all;
library work; library work;
use work.gn4124_core_pkg.all;
use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all; use work.fmc_adc_mezzanine_pkg.all;
use work.synthesis_descriptor.all;
use work.spec_carrier_csr_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all; use work.wr_board_pkg.all;
use work.wr_spec_pkg.all;
entity spec_ref_fmc_adc_100Ms is entity spec_ref_fmc_adc_100Ms is
generic( generic(
g_SIMULATION : integer := 0; g_SIMULATION : integer := 0;
g_MULTISHOT_RAM_SIZE : natural := 4096; g_MULTISHOT_RAM_SIZE : natural := 2048;
g_CALIB_SOFT_IP : string := "TRUE";
g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram"); g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram");
port port
( (
...@@ -67,14 +60,14 @@ entity spec_ref_fmc_adc_100Ms is ...@@ -67,14 +60,14 @@ entity spec_ref_fmc_adc_100Ms is
clk_125m_gtp_p_i : in std_logic; clk_125m_gtp_p_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO) -- DAC interface (20MHz and 25MHz VCXO)
pll25dac_sync_n_o : out std_logic; -- 25MHz VCXO pll25dac_cs_n_o : out std_logic; -- 25MHz VCXO
pll20dac_sync_n_o : out std_logic; -- 20MHz VCXO pll20dac_cs_n_o : out std_logic; -- 20MHz VCXO
plldac_din_o : out std_logic; plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic; plldac_sclk_o : out std_logic;
-- Carrier front panel LEDs -- Carrier front panel LEDs
led_sfp_red_o : out std_logic; led_act_o : out std_logic;
led_sfp_green_o : out std_logic; led_link_o : out std_logic;
-- Auxiliary pins -- Auxiliary pins
aux_leds_o : out std_logic_vector(3 downto 0); aux_leds_o : out std_logic_vector(3 downto 0);
...@@ -83,7 +76,7 @@ entity spec_ref_fmc_adc_100Ms is ...@@ -83,7 +76,7 @@ entity spec_ref_fmc_adc_100Ms is
pcbrev_i : in std_logic_vector(3 downto 0); pcbrev_i : in std_logic_vector(3 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID) -- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
carrier_onewire_b : inout std_logic; onewire_b : inout std_logic;
-- SFP -- SFP
sfp_txp_o : out std_logic; sfp_txp_o : out std_logic;
...@@ -111,8 +104,8 @@ entity spec_ref_fmc_adc_100Ms is ...@@ -111,8 +104,8 @@ entity spec_ref_fmc_adc_100Ms is
------------------------------------------ ------------------------------------------
-- GN4124 interface -- GN4124 interface
-- --
-- gn_gpio_b[0] -> AB19 -> GN4124 GPIO9 -- gn_gpio_b[1] -> AB19 -> GN4124 GPIO9
-- gn_gpio_b[1] -> U16 -> GN4124 GPIO8 -- gn_gpio_b[0] -> U16 -> GN4124 GPIO8
------------------------------------------ ------------------------------------------
gn_rst_n_i : in std_logic; gn_rst_n_i : in std_logic;
gn_p2l_clk_n_i : in std_logic; gn_p2l_clk_n_i : in std_logic;
...@@ -200,137 +193,29 @@ entity spec_ref_fmc_adc_100Ms is ...@@ -200,137 +193,29 @@ entity spec_ref_fmc_adc_100Ms is
------------------------------------------ ------------------------------------------
-- FMC slot management -- FMC slot management
------------------------------------------ ------------------------------------------
fmc_prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low) fmc0_prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low)
fmc_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM) fmc0_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
fmc_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM) fmc0_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM)
); );
end spec_ref_fmc_adc_100Ms; end spec_ref_fmc_adc_100Ms;
architecture rtl of spec_ref_fmc_adc_100Ms is architecture arch of spec_ref_fmc_adc_100Ms is
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- SDB crossbar constants declaration -- Constants declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves on the wishbone crossbar -- Number of slaves on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 6; constant c_NUM_WB_SLAVES : integer := 2;
-- Wishbone master(s)
constant c_WB_MASTER_GENNUM : integer := 0;
-- Wishbone slave(s) -- Wishbone slave(s)
constant c_WB_SLAVE_DMA : integer := 0; -- DMA controller in the Gennum core constant c_WB_SLAVE_METADATA : integer := 0;
constant c_WB_SLAVE_SPEC_CSR : integer := 1; -- SPEC control and status registers constant c_WB_SLAVE_FMC_ADC : integer := 1; -- FMC ADC mezzanine
constant c_WB_SLAVE_VIC : integer := 2; -- Vectored interrupt controller
constant c_WB_SLAVE_DMA_EIC : integer := 3; -- DMA interrupt controller
constant c_WB_SLAVE_FMC_ADC : integer := 4; -- FMC ADC mezzanine
constant c_WB_SLAVE_WR_CORE : integer := 5; -- WR PTP core
-- SDB meta info
constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_SLAVES;
constant c_SDB_SYNTHESIS : integer := c_NUM_WB_SLAVES + 1;
-- Devices sdb description
constant c_WB_DMA_CTRL_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000003F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000601",
version => x"00000001",
date => x"20121116",
name => "WB-DMA.Control ")));
constant c_WB_SPEC_CSR_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603",
version => x"00000001",
date => x"20121116",
name => "WB-SPEC-CSR ")));
constant c_WB_DMA_EIC_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"d5735ab4", -- echo "WB-DMA.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20131204",
name => "WB-DMA.EIC ")));
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_FMC_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_WR_CORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) :=
(
c_WB_SLAVE_DMA => f_sdb_embed_device(c_WB_DMA_CTRL_SDB, x"00001000"),
c_WB_SLAVE_SPEC_CSR => f_sdb_embed_device(c_WB_SPEC_CSR_SDB, x"00001200"),
c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00001300"),
c_WB_SLAVE_DMA_EIC => f_sdb_embed_device(c_WB_DMA_EIC_SDB, x"00001400"),
c_WB_SLAVE_FMC_ADC => f_sdb_embed_bridge(c_FMC_BRIDGE_SDB, x"00002000"),
c_WB_SLAVE_WR_CORE => f_sdb_embed_bridge(c_WR_CORE_BRIDGE_SDB, x"00040000"),
c_SDB_GIT_REPO_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL),
c_SDB_SYNTHESIS => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO));
-- VIC default vector setting
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00003500",
1 => x"00001400");
------------------------------------------------------------------------------
-- Other constants declaration
------------------------------------------------------------------------------
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock -- Convention metadata base address
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := ( constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
others => c_AUXPLL_CFG_DEFAULT);
-- SPEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
-- Conversion of g_simulation to string needed for DDR controller
function f_int2string (n : natural) return string is
begin
if n = 0 then
return "FALSE";
else
return "TRUE ";
end if;
end;
constant c_SIMULATION_STR : string := f_int2string(g_SIMULATION);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Signals declaration -- Signals declaration
...@@ -339,33 +224,13 @@ architecture rtl of spec_ref_fmc_adc_100Ms is ...@@ -339,33 +224,13 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
-- Clocks and resets -- Clocks and resets
signal clk_sys_62m5 : std_logic; signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic; signal clk_ref_125m : std_logic;
signal sys_clk_pll_locked : std_logic;
signal clk_ddr_333m : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal rst_pll_aux_n : std_logic_vector(3 downto 0) := (others => '0');
signal rst_sys_62m5_n : std_logic := '0'; signal rst_sys_62m5_n : std_logic := '0';
signal rst_ref_125m_n : std_logic := '0'; signal rst_ref_125m_n : std_logic := '0';
signal rst_ddr_333m_n : std_logic := '0';
signal sw_rst_fmc : std_logic := '1';
signal sw_rst_fmc_sync : std_logic := '1';
signal fmc_rst_ref_n : std_logic := '0';
signal fmc_rst_sys_n : std_logic := '0';
signal ddr_rst : std_logic := '1';
attribute keep : string;
attribute keep of clk_sys_62m5 : signal is "TRUE";
attribute keep of clk_ref_125m : signal is "TRUE";
attribute keep of clk_ddr_333m : signal is "TRUE";
attribute keep of ddr_rst : signal is "TRUE";
-- GN4124
signal gn4124_status : std_logic_vector(31 downto 0);
signal gn4124_access : std_logic;
-- Wishbone buse(s) from master(s) to crossbar slave port(s) -- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_out : t_wishbone_master_out;
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_in : t_wishbone_master_in;
-- Wishbone buse(s) from crossbar master port(s) to slave(s) -- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
...@@ -375,336 +240,179 @@ architecture rtl of spec_ref_fmc_adc_100Ms is ...@@ -375,336 +240,179 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
signal cnx_fmc_sync_master_out : t_wishbone_master_out; signal cnx_fmc_sync_master_out : t_wishbone_master_out;
signal cnx_fmc_sync_master_in : t_wishbone_master_in; signal cnx_fmc_sync_master_in : t_wishbone_master_in;
-- GN4124 core DMA port to DDR wishbone bus
signal gn_wb_ddr_in : t_wishbone_master_in;
signal gn_wb_ddr_out : t_wishbone_master_out;
-- FMC ADC core to DDR wishbone bus -- FMC ADC core to DDR wishbone bus
signal fmc_wb_ddr_in : t_wishbone_master_data64_in; signal fmc_wb_ddr_in : t_wishbone_master_data64_in;
signal fmc_wb_ddr_out : t_wishbone_master_data64_out; signal fmc_wb_ddr_out : t_wishbone_master_data64_out;
-- Interrupts and status -- Interrupts and status
signal dma_irq : std_logic_vector(1 downto 0);
signal irq_sources : std_logic_vector(3 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_sources_2_led : std_logic_vector(3 downto 0);
signal ddr_wr_fifo_empty : std_logic; signal ddr_wr_fifo_empty : std_logic;
signal dma_eic_irq : std_logic; signal ddr_wr_fifo_empty_sync : std_logic;
signal fmc_irq : std_logic; signal fmc_irq : std_logic;
signal fmc_acq_cfg_ok : std_logic; signal fmc_acq_cfg_ok : std_logic;
signal irq_vector : std_logic_vector(0 downto 0);
-- Resync interrupts to sys domain signal gn4124_access : std_logic;
signal dma_irq_sync : std_logic_vector(1 downto 0);
signal ddr_wr_fifo_empty_sync : std_logic;
signal fmc_irq_sync : std_logic;
-- Front panel LED control
signal led_red : std_logic;
signal led_green : std_logic;
-- DDR
signal ddr_status : std_logic_vector(31 downto 0);
signal ddr_calib_done : std_logic;
-- SFP
signal sfp_scl_out : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_sda_in : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- White Rabbit
signal wrabbit_en : std_logic;
signal wrc_scl_out : std_logic;
signal wrc_scl_in : std_logic;
signal wrc_sda_out : std_logic;
signal wrc_sda_in : std_logic;
signal pps_led : std_logic;
signal wr_led_act : std_logic;
signal wr_led_link : std_logic;
-- WR PTP core timing interface -- WR PTP core timing interface
signal tm_link_up : std_logic; signal tm_link_up : std_logic;
signal tm_tai : std_logic_vector(39 downto 0); signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0); signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic; signal tm_time_valid : std_logic;
signal tm_time_valid_sync : std_logic;
signal wrabbit_en : std_logic;
signal pps_led : std_logic;
-- IO for CSR registers begin -- architecture arch
signal csr_regin : t_carrier_csr_master_in;
signal csr_regout : t_carrier_csr_master_out;
begin
------------------------------------------------------------------------------
-- Reset logic
------------------------------------------------------------------------------
sys_clk_pll_locked <= '1';
-- reset for mezzanine
-- including soft reset, with re-sync from 62.5MHz domain
-- and registers to help with timing
cmp_fmc_sw_reset_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => sw_rst_fmc,
synced_o => sw_rst_fmc_sync);
fmc_rst_ref_n <= rst_ref_125m_n and not sw_rst_fmc_sync;
fmc_rst_sys_n <= rst_sys_62m5_n and not sw_rst_fmc;
-- reset for DDR including soft reset.
-- This is treated as async and will be re-synced by the DDR controller
ddr_rst <= not rst_ddr_333m_n or sw_rst_fmc;
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
-- Reduce the default FIFO sizes to make it easier for the 45T Spartan6.
cmp_gn4124_core : xwb_gn4124_core
generic map (
g_WBM_TO_WB_FIFO_SIZE => 16,
g_WBM_TO_WB_FIFO_FULL_THRES => 12,
g_WBM_FROM_WB_FIFO_SIZE => 16,
g_WBM_FROM_WB_FIFO_FULL_THRES => 12,
g_P2L_FIFO_SIZE => 256,
g_P2L_FIFO_FULL_THRES => 175,
g_L2P_ADDR_FIFO_FULL_SIZE => 256,
g_L2P_ADDR_FIFO_FULL_THRES => 175,
g_L2P_DATA_FIFO_FULL_SIZE => 256,
g_L2P_DATA_FIFO_FULL_THRES => 175)
port map (
rst_n_a_i => gn_rst_n_i,
status_o => gn4124_status,
p2l_clk_p_i => gn_p2l_clk_p_i,
p2l_clk_n_i => gn_p2l_clk_n_i,
p2l_data_i => gn_p2l_data_i,
p2l_dframe_i => gn_p2l_dframe_i,
p2l_valid_i => gn_p2l_valid_i,
p2l_rdy_o => gn_p2l_rdy_o,
p_wr_req_i => gn_p_wr_req_i,
p_wr_rdy_o => gn_p_wr_rdy_o,
rx_error_o => gn_rx_error_o,
l2p_clk_p_o => gn_l2p_clk_p_o,
l2p_clk_n_o => gn_l2p_clk_n_o,
l2p_data_o => gn_l2p_data_o,
l2p_dframe_o => gn_l2p_dframe_o,
l2p_valid_o => gn_l2p_valid_o,
l2p_edb_o => gn_l2p_edb_o,
l2p_rdy_i => gn_l2p_rdy_i,
l_wr_rdy_i => gn_l_wr_rdy_i,
p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
tx_error_i => gn_tx_error_i,
vc_rdy_i => gn_vc_rdy_i,
dma_irq_o => dma_irq,
irq_p_i => irq_to_gn4124,
irq_p_o => gn_gpio_b(1),
wb_master_clk_i => clk_sys_62m5,
wb_master_rst_n_i => rst_sys_62m5_n,
wb_master_i => cnx_master_in(c_WB_MASTER_GENNUM),
wb_master_o => cnx_master_out(c_WB_MASTER_GENNUM),
wb_dma_cfg_clk_i => clk_sys_62m5,
wb_dma_cfg_rst_n_i => rst_sys_62m5_n,
wb_dma_cfg_i => cnx_slave_in(c_WB_SLAVE_DMA),
wb_dma_cfg_o => cnx_slave_out(c_WB_SLAVE_DMA),
wb_dma_dat_clk_i => clk_sys_62m5,
wb_dma_dat_rst_n_i => rst_sys_62m5_n,
wb_dma_dat_i => gn_wb_ddr_in,
wb_dma_dat_o => gn_wb_ddr_out);
-- Assign unused outputs
gn_gpio_b(0) <= '0';
------------------------------------------------------------------------------ inst_spec_base : entity work.spec_base_wr
-- Primary wishbone crossbar
------------------------------------------------------------------------------
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map (
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_WRAPAROUND => TRUE,
g_LAYOUT => c_INTERCONNECT_LAYOUT,
g_SDB_ADDR => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
-------------------------------------------------------------------------------
-- White Rabbit Core (SPEC board package)
-------------------------------------------------------------------------------
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- Tristates for Carrier OneWire
carrier_onewire_b <= '0' when onewire_oe = '1' else 'Z';
onewire_data <= carrier_onewire_b;
cmp_xwrc_board_spec : xwrc_board_spec
generic map ( generic map (
g_SIMULATION => g_SIMULATION, g_WITH_VIC => TRUE,
g_WITH_EXTERNAL_CLOCK_INPUT => FALSE, g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_WR => TRUE,
g_WITH_DDR => TRUE,
g_DDR_DATA_SIZE => 64,
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 1,
g_DPRAM_INITF => g_WRPC_INITF, g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG, g_AUX_CLKS => 0,
g_FABRIC_IFACE => PLAIN) g_FABRIC_IFACE => plain,
g_SIMULATION => f_int2bool(g_SIMULATION))
port map ( port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i, clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i, clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i, clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i, clk_125m_gtp_p_i => clk_125m_gtp_p_i,
areset_n_i => button1_n_i, gn_rst_n_i => gn_rst_n_i,
areset_edge_n_i => gn_rst_n_i, gn_p2l_clk_n_i => gn_p2l_clk_n_i,
clk_sys_62m5_o => clk_sys_62m5, gn_p2l_clk_p_i => gn_p2l_clk_p_i,
clk_ref_125m_o => clk_ref_125m, gn_p2l_rdy_o => gn_p2l_rdy_o,
clk_pll_aux_o => clk_pll_aux, gn_p2l_dframe_i => gn_p2l_dframe_i,
rst_sys_62m5_n_o => rst_sys_62m5_n, gn_p2l_valid_i => gn_p2l_valid_i,
rst_ref_125m_n_o => rst_ref_125m_n, gn_p2l_data_i => gn_p2l_data_i,
rst_pll_aux_n_o => rst_pll_aux_n, gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
plldac_sclk_o => plldac_sclk_o, plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o, plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_sync_n_o, pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_sync_n_o, pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o, sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o, sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i, sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i, sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i, sfp_mod_def0_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in, sfp_mod_def1_b => sfp_mod_def1_b,
sfp_sda_o => sfp_sda_out, sfp_mod_def2_b => sfp_mod_def2_b,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o, sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i, sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o, sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i, sfp_los_i => sfp_los_i,
onewire_i => onewire_data, ddr_a_o => ddr_a_o,
onewire_oen_o => onewire_oe, ddr_ba_o => ddr_ba_o,
uart_rxd_i => uart_rxd_i, ddr_cas_n_o => ddr_cas_n_o,
uart_txd_o => uart_txd_o, ddr_ck_n_o => ddr_ck_n_o,
flash_sclk_o => spi_sclk_o, ddr_ck_p_o => ddr_ck_p_o,
flash_ncs_o => spi_ncs_o, ddr_cke_o => ddr_cke_o,
flash_mosi_o => spi_mosi_o, ddr_dq_b => ddr_dq_b,
flash_miso_i => spi_miso_i, ddr_ldm_o => ddr_ldm_o,
wb_slave_o => cnx_slave_out(c_WB_SLAVE_WR_CORE), ddr_ldqs_n_b => ddr_ldqs_n_b,
wb_slave_i => cnx_slave_in(c_WB_SLAVE_WR_CORE), ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
ddr_dma_clk_i => clk_ref_125m,
ddr_dma_rst_n_i => rst_ref_125m_n,
ddr_dma_wb_cyc_i => fmc_wb_ddr_out.cyc,
ddr_dma_wb_stb_i => fmc_wb_ddr_out.stb,
ddr_dma_wb_adr_i => fmc_wb_ddr_out.adr,
ddr_dma_wb_sel_i => fmc_wb_ddr_out.sel,
ddr_dma_wb_we_i => fmc_wb_ddr_out.we,
ddr_dma_wb_dat_i => fmc_wb_ddr_out.dat,
ddr_dma_wb_ack_o => fmc_wb_ddr_in.ack,
ddr_dma_wb_stall_o => fmc_wb_ddr_in.stall,
ddr_dma_wb_dat_o => fmc_wb_ddr_in.dat,
ddr_wr_fifo_empty_o => ddr_wr_fifo_empty,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
clk_125m_ref_o => clk_ref_125m,
rst_125m_ref_n_o => rst_ref_125m_n,
irq_user_i => irq_vector,
tm_link_up_o => tm_link_up, tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid, tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai, tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles, tm_cycles_o => tm_cycles,
pps_p_o => open, pps_p_o => open,
pps_led_o => pps_led, pps_led_o => pps_led,
led_link_o => wr_led_link, link_ok_o => wrabbit_en,
led_act_o => wr_led_act, app_wb_o => cnx_master_out,
link_ok_o => wrabbit_en); app_wb_i => cnx_master_in);
clk_ddr_333m <= clk_pll_aux(0); fmc_wb_ddr_in.err <= '0';
rst_ddr_333m_n <= rst_pll_aux_n(0); fmc_wb_ddr_in.rty <= '0';
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Carrier CSR -- Primary wishbone crossbar
-- Carrier type and PCB version
-- Bitstream (firmware) type and date
-- Release tag
-- VCXO DAC control (CLR_N)
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_carrier_csr : entity work.spec_carrier_csr
cmp_crossbar : entity work.spec_ref_fmc_adc_100m_mmap
port map ( port map (
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5, clk_i => clk_sys_62m5,
wb_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR), wb_i => cnx_master_out,
wb_o => cnx_slave_out(c_WB_SLAVE_SPEC_CSR), wb_o => cnx_master_in,
carrier_csr_i => csr_regin, metadata_i => cnx_slave_out(c_WB_SLAVE_METADATA),
carrier_csr_o => csr_regout); metadata_o => cnx_slave_in(c_WB_SLAVE_METADATA),
fmc_adc_mezzanine_i => cnx_slave_out(c_WB_SLAVE_FMC_ADC),
csr_regin.carrier_pcb_rev <= pcbrev_i; fmc_adc_mezzanine_o => cnx_slave_in(c_WB_SLAVE_FMC_ADC));
csr_regin.carrier_reserved <= (others => '0');
csr_regin.carrier_type <= c_CARRIER_TYPE;
csr_regin.stat_fmc_pres <= fmc_prsnt_m2c_n_i;
csr_regin.stat_p2l_pll_lck <= gn4124_status(0);
csr_regin.stat_sys_pll_lck <= sys_clk_pll_locked;
csr_regin.stat_ddr3_cal_done <= ddr_calib_done;
led_red <= csr_regout.ctrl_led_red;
led_green <= csr_regout.ctrl_led_green;
sw_rst_fmc <= csr_regout.rst_fmc0;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC) -- Application-specific metadata ROM
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc_irq_sync : gc_sync_ffs cmp_xwb_metadata : entity work.xwb_metadata
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc_irq,
synced_o => fmc_irq_sync);
cmp_vic : xwb_vic
generic map ( generic map (
g_INTERFACE_MODE => PIPELINED, g_VENDOR_ID => x"0000_10DC",
g_ADDRESS_GRANULARITY => BYTE, g_DEVICE_ID => x"4144_4301", -- "ADC1"
g_NUM_INTERRUPTS => 2, g_VERSION => x"0100_0000",
g_INIT_VECTORS => c_VIC_VECTOR_TABLE) g_CAPABILITIES => x"0000_0000",
port map ( g_COMMIT_ID => (others => '0'))
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in(c_WB_SLAVE_VIC),
slave_o => cnx_slave_out(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_irq_sync,
irqs_i(1) => dma_eic_irq,
irq_master_o => irq_to_gn4124);
------------------------------------------------------------------------------
-- GN4124 DMA interrupt controller
------------------------------------------------------------------------------
gen_dma_irq : for I in 0 to 1 generate
cmp_dma_irq_sync : gc_sync_ffs
port map ( port map (
clk_i => clk_sys_62m5, clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => dma_irq(I),
synced_o => dma_irq_sync(I));
end generate gen_dma_irq;
cmp_dma_eic : entity work.dma_eic
port map (
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
clk_sys_i => clk_sys_62m5, wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_adr_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).adr(3 downto 2), -- cnx_slave_in.adr is byte address wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
wb_dat_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).dat,
wb_dat_o => cnx_slave_out(c_WB_SLAVE_DMA_EIC).dat,
wb_cyc_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).cyc,
wb_sel_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).sel,
wb_stb_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).stb,
wb_we_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).we,
wb_ack_o => cnx_slave_out(c_WB_SLAVE_DMA_EIC).ack,
wb_stall_o => cnx_slave_out(c_WB_SLAVE_DMA_EIC).stall,
wb_int_o => dma_eic_irq,
irq_dma_done_i => dma_irq_sync(0),
irq_dma_error_i => dma_irq_sync(1)
);
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_DMA_EIC).err <= '0';
cnx_slave_out(c_WB_SLAVE_DMA_EIC).rty <= '0';
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- FMC ADC mezzanines (wb bridge with cross-clocking) -- FMC ADC mezzanines (wb bridge with cross-clocking)
...@@ -716,16 +424,25 @@ begin ...@@ -716,16 +424,25 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_xwb_clock_bridge : xwb_clock_bridge cmp_xwb_clock_bridge : xwb_clock_bridge
generic map (
g_SLAVE_PORT_WB_MODE => CLASSIC,
g_MASTER_PORT_WB_MODE => PIPELINED)
port map ( port map (
slave_clk_i => clk_sys_62m5, slave_clk_i => clk_sys_62m5,
slave_rst_n_i => fmc_rst_sys_n, slave_rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in(c_WB_SLAVE_FMC_ADC), slave_i => cnx_slave_in(c_WB_SLAVE_FMC_ADC),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC_ADC), slave_o => cnx_slave_out(c_WB_SLAVE_FMC_ADC),
master_clk_i => clk_ref_125m, master_clk_i => clk_ref_125m,
master_rst_n_i => fmc_rst_ref_n, master_rst_n_i => rst_ref_125m_n,
master_i => cnx_fmc_sync_master_in, master_i => cnx_fmc_sync_master_in,
master_o => cnx_fmc_sync_master_out master_o => cnx_fmc_sync_master_out);
);
cmp_tm_time_valid_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => tm_time_valid,
synced_o => tm_time_valid_sync);
cmp_fmc_ddr_wr_fifo_sync : gc_sync_ffs cmp_fmc_ddr_wr_fifo_sync : gc_sync_ffs
port map ( port map (
...@@ -734,6 +451,13 @@ begin ...@@ -734,6 +451,13 @@ begin
data_i => ddr_wr_fifo_empty, data_i => ddr_wr_fifo_empty,
synced_o => ddr_wr_fifo_empty_sync); synced_o => ddr_wr_fifo_empty_sync);
cmp_fmc_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc_irq,
synced_o => irq_vector(0));
cmp_fmc_adc_mezzanine : fmc_adc_mezzanine cmp_fmc_adc_mezzanine : fmc_adc_mezzanine
generic map ( generic map (
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE, g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE,
...@@ -742,13 +466,13 @@ begin ...@@ -742,13 +466,13 @@ begin
g_WB_GRANULARITY => BYTE) g_WB_GRANULARITY => BYTE)
port map ( port map (
sys_clk_i => clk_ref_125m, sys_clk_i => clk_ref_125m,
sys_rst_n_i => fmc_rst_ref_n, sys_rst_n_i => rst_ref_125m_n,
wb_csr_slave_i => cnx_fmc_sync_master_out, wb_csr_slave_i => cnx_fmc_sync_master_out,
wb_csr_slave_o => cnx_fmc_sync_master_in, wb_csr_slave_o => cnx_fmc_sync_master_in,
wb_ddr_clk_i => clk_ref_125m, wb_ddr_clk_i => clk_ref_125m,
wb_ddr_rst_n_i => fmc_rst_ref_n, wb_ddr_rst_n_i => rst_ref_125m_n,
wb_ddr_master_i => fmc_wb_ddr_in, wb_ddr_master_i => fmc_wb_ddr_in,
wb_ddr_master_o => fmc_wb_ddr_out, wb_ddr_master_o => fmc_wb_ddr_out,
...@@ -793,119 +517,13 @@ begin ...@@ -793,119 +517,13 @@ begin
mezz_one_wire_b => adc_one_wire_b, mezz_one_wire_b => adc_one_wire_b,
sys_scl_b => fmc_scl_b,
sys_sda_b => fmc_sda_b,
wr_tm_link_up_i => tm_link_up, wr_tm_link_up_i => tm_link_up,
wr_tm_time_valid_i => tm_time_valid, wr_tm_time_valid_i => tm_time_valid_sync,
wr_tm_tai_i => tm_tai, wr_tm_tai_i => tm_tai,
wr_tm_cycles_i => tm_cycles, wr_tm_cycles_i => tm_cycles,
wr_enable_i => wrabbit_en wr_enable_i => wrabbit_en
); );
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
------------------------------------------------------------------------------
cmp_ddr_ctrl_bank3 : ddr3_ctrl
generic map(
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
g_BANK_PORT_SELECT => "SPEC_BANK3_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => c_SIMULATION_STR,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => clk_ddr_333m,
rst_n_i => ddr_rst,
status_o => ddr_status,
ddr3_dq_b => ddr_dq_b,
ddr3_a_o => ddr_a_o,
ddr3_ba_o => ddr_ba_o,
ddr3_ras_n_o => ddr_ras_n_o,
ddr3_cas_n_o => ddr_cas_n_o,
ddr3_we_n_o => ddr_we_n_o,
ddr3_odt_o => ddr_odt_o,
ddr3_rst_n_o => ddr_reset_n_o,
ddr3_cke_o => ddr_cke_o,
ddr3_dm_o => ddr_ldm_o,
ddr3_udm_o => ddr_udm_o,
ddr3_dqs_p_b => ddr_ldqs_p_b,
ddr3_dqs_n_b => ddr_ldqs_n_b,
ddr3_udqs_p_b => ddr_udqs_p_b,
ddr3_udqs_n_b => ddr_udqs_n_b,
ddr3_clk_p_o => ddr_ck_p_o,
ddr3_clk_n_o => ddr_ck_n_o,
ddr3_rzq_b => ddr_rzq_b,
wb0_rst_n_i => fmc_rst_ref_n,
wb0_clk_i => clk_ref_125m,
wb0_sel_i => fmc_wb_ddr_out.sel,
wb0_cyc_i => fmc_wb_ddr_out.cyc,
wb0_stb_i => fmc_wb_ddr_out.stb,
wb0_we_i => fmc_wb_ddr_out.we,
wb0_addr_i => fmc_wb_ddr_out.adr,
wb0_data_i => fmc_wb_ddr_out.dat,
wb0_data_o => fmc_wb_ddr_in.dat,
wb0_ack_o => fmc_wb_ddr_in.ack,
wb0_stall_o => fmc_wb_ddr_in.stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr_wr_fifo_empty,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_sys_62m5_n,
wb1_clk_i => clk_sys_62m5,
wb1_sel_i => gn_wb_ddr_out.sel,
wb1_cyc_i => gn_wb_ddr_out.cyc,
wb1_stb_i => gn_wb_ddr_out.stb,
wb1_we_i => gn_wb_ddr_out.we,
wb1_addr_i => gn_wb_ddr_out.adr,
wb1_data_i => gn_wb_ddr_out.dat,
wb1_data_o => gn_wb_ddr_in.dat,
wb1_ack_o => gn_wb_ddr_in.ack,
wb1_stall_o => gn_wb_ddr_in.stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
ddr_calib_done <= ddr_status(0);
-- unused Wishbone signals
gn_wb_ddr_in.err <= '0';
gn_wb_ddr_in.rty <= '0';
fmc_wb_ddr_in.err <= '0';
fmc_wb_ddr_in.rty <= '0';
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Carrier LEDs -- Carrier LEDs
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -916,7 +534,7 @@ begin ...@@ -916,7 +534,7 @@ begin
port map ( port map (
clk_i => clk_sys_62m5, clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_WB_MASTER_GENNUM).cyc, pulse_i => cnx_master_out.cyc,
extended_o => gn4124_access); extended_o => gn4124_access);
aux_leds_o(0) <= not gn4124_access; aux_leds_o(0) <= not gn4124_access;
...@@ -924,8 +542,4 @@ begin ...@@ -924,8 +542,4 @@ begin
aux_leds_o(2) <= not tm_time_valid; aux_leds_o(2) <= not tm_time_valid;
aux_leds_o(3) <= not pps_led; aux_leds_o(3) <= not pps_led;
-- SPEC front panel leds end architecture arch;
led_sfp_red_o <= led_red or wr_led_act;
led_sfp_green_o <= led_green or wr_led_link;
end rtl;
hdl/top/spec_ref_design/wb_gen/Makefile deleted 100644 → 0
View file @ d98dbd10
WBGEN2=$(shell which wbgen2)
RTL=../
TEX=../../../../doc/manual/spec/
all: dma_eic
dma_eic:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
hdl/top/spec_ref_design/wb_gen/dma_eic.h deleted 100644 → 0
View file @ d98dbd10
/*
Register definitions for slave core: GN4124 DMA enhanced interrupt controller
* File : dma_eic.h
* Author : auto-generated by wbgen2 from dma_eic.wb
* Created : Thu Jun 16 16:45:19 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dma_eic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_DMA_EIC_WB
#define __WBGEN2_REGDEFS_DMA_EIC_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Interrupt disable register */
/* definitions for field: DMA done interrupt in reg: Interrupt disable register */
#define DMA_EIC_EIC_IDR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt disable register */
#define DMA_EIC_EIC_IDR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: DMA done interrupt in reg: Interrupt enable register */
#define DMA_EIC_EIC_IER_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt enable register */
#define DMA_EIC_EIC_IER_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: DMA done interrupt in reg: Interrupt mask register */
#define DMA_EIC_EIC_IMR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt mask register */
#define DMA_EIC_EIC_IMR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: DMA done interrupt in reg: Interrupt status register */
#define DMA_EIC_EIC_ISR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt status register */
#define DMA_EIC_EIC_ISR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
PACKED struct DMA_EIC_WB {
/* [0x0]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x4]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x8]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0xc]: REG Interrupt status register */
uint32_t EIC_ISR;
};
#endif
hdl/top/spec_ref_design/wb_gen/dma_eic.htm deleted 100644 → 0
View file @ d98dbd10
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<HEAD>
<TITLE>dma_eic</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
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.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
</STYLE>
</HEAD>
<BODY>
<h1 class="heading">dma_eic</h1>
<h3>GN4124 DMA enhanced interrupt controller</h3>
<p>Enhanced interrrupt controller for GN4124 DMA.</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Interrupt disable register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Interrupt enable register</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Interrupt mask register</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Interrupt status register</a></span><br/>
<span style="margin-left: 0px; ">5. <A href="#sect_5_0">Interrupts</a></span><br/>
<span style="margin-left: 20px; ">5.1. <A href="#sect_5_1">DMA done interrupt</a></span><br/>
<span style="margin-left: 20px; ">5.2. <A href="#sect_5_2">DMA error interrupt</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#EIC_IDR">Interrupt disable register</a>
</td>
<td class="td_code">
dma_eic_eic_idr
</td>
<td class="td_code">
EIC_IDR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#EIC_IER">Interrupt enable register</a>
</td>
<td class="td_code">
dma_eic_eic_ier
</td>
<td class="td_code">
EIC_IER
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#EIC_IMR">Interrupt mask register</a>
</td>
<td class="td_code">
dma_eic_eic_imr
</td>
<td class="td_code">
EIC_IMR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#EIC_ISR">Interrupt status register</a>
</td>
<td class="td_code">
dma_eic_eic_isr
</td>
<td class="td_code">
EIC_ISR
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>DMA done interrupt:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
clk_sys_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_dma_done_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[1:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>DMA error interrupt:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_dma_error_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_int_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="EIC_IDR"></a>
<h3><a name="sect_3_1">3.1. Interrupt disable register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_eic_eic_idr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EIC_IDR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_ERROR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_DONE
</td>
</tr>
</table>
<ul>
<li><b>
DMA_DONE
</b>[<i>write-only</i>]: DMA done interrupt
<br>write 1: disable interrupt 'DMA done interrupt'<br>write 0: no effect
<li><b>
DMA_ERROR
</b>[<i>write-only</i>]: DMA error interrupt
<br>write 1: disable interrupt 'DMA error interrupt'<br>write 0: no effect
</ul>
<a name="EIC_IER"></a>
<h3><a name="sect_3_2">3.2. Interrupt enable register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_eic_eic_ier
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EIC_IER
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_ERROR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_DONE
</td>
</tr>
</table>
<ul>
<li><b>
DMA_DONE
</b>[<i>write-only</i>]: DMA done interrupt
<br>write 1: enable interrupt 'DMA done interrupt'<br>write 0: no effect
<li><b>
DMA_ERROR
</b>[<i>write-only</i>]: DMA error interrupt
<br>write 1: enable interrupt 'DMA error interrupt'<br>write 0: no effect
</ul>
<a name="EIC_IMR"></a>
<h3><a name="sect_3_3">3.3. Interrupt mask register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_eic_eic_imr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EIC_IMR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<p>
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_ERROR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_DONE
</td>
</tr>
</table>
<ul>
<li><b>
DMA_DONE
</b>[<i>read-only</i>]: DMA done interrupt
<br>read 1: interrupt 'DMA done interrupt' is enabled<br>read 0: interrupt 'DMA done interrupt' is disabled
<li><b>
DMA_ERROR
</b>[<i>read-only</i>]: DMA error interrupt
<br>read 1: interrupt 'DMA error interrupt' is enabled<br>read 0: interrupt 'DMA error interrupt' is disabled
</ul>
<a name="EIC_ISR"></a>
<h3><a name="sect_3_4">3.4. Interrupt status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_eic_eic_isr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EIC_ISR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<p>
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_ERROR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_DONE
</td>
</tr>
</table>
<ul>
<li><b>
DMA_DONE
</b>[<i>read/write</i>]: DMA done interrupt
<br>read 1: interrupt 'DMA done interrupt' is pending<br>read 0: interrupt not pending<br>write 1: clear interrupt 'DMA done interrupt'<br>write 0: no effect
<li><b>
DMA_ERROR
</b>[<i>read/write</i>]: DMA error interrupt
<br>read 1: interrupt 'DMA error interrupt' is pending<br>read 0: interrupt not pending<br>write 1: clear interrupt 'DMA error interrupt'<br>write 0: no effect
</ul>
<h3><a name="sect_5_0">5. Interrupts</a></h3>
<a name="DMA_DONE"></a>
<h3><a name="sect_5_1">5.1. DMA done interrupt</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td >
dma_eic_dma_done
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td >
DMA_DONE
</td>
</tr>
<tr>
<td >
<b>Trigger: </b>
</td>
<td >
rising edge
</td>
</tr>
</table>
<p>DMA done interrupt line (rising edge sensitive).</p>
<a name="DMA_ERROR"></a>
<h3><a name="sect_5_2">5.2. DMA error interrupt</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td >
dma_eic_dma_error
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td >
DMA_ERROR
</td>
</tr>
<tr>
<td >
<b>Trigger: </b>
</td>
<td >
rising edge
</td>
</tr>
</table>
<p>DMA error interrupt line (rising edge sensitive).</p>
</BODY>
</HTML>
hdl/top/spec_ref_design/wb_gen/dma_eic.wb deleted 100644 → 0
View file @ d98dbd10
peripheral {
name = "GN4124 DMA enhanced interrupt controller";
description = "Enhanced interrrupt controller for GN4124 DMA.";
hdl_entity = "dma_eic";
prefix = "dma_eic";
irq {
name = "DMA done interrupt";
description = "DMA done interrupt line (rising edge sensitive).";
prefix = "dma_done";
trigger = EDGE_RISING;
};
irq {
name = "DMA error interrupt";
description = "DMA error interrupt line (rising edge sensitive).";
prefix = "dma_error";
trigger = EDGE_RISING;
};
};
hdl/top/svec_ref_design/Manifest.py
View file @ 4e6378bd
files = [ files = [
"svec_ref_fmc_adc_100Ms.vhd", "svec_ref_fmc_adc_100Ms.vhd",
"svec_carrier_csr.vhd", "../../cheby/svec_ref_fmc_adc_100Ms_mmap.vhd",
] ]
fetchto = "../../ip_cores"
modules = { modules = {
"local" : [ "local" : [
"../../../", "../../../",
], ],
"git" : [
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/svec.git",
],
} }
hdl/top/svec_ref_design/svec_carrier_csr.cheby deleted 100644 → 0
View file @ d98dbd10
memory-map:
bus: wb-32-be
name: svec_carrier_csr
description: SVEC carrier control and status registers
comment: |
Wishbone slave for control and status registers related to the SVEC FMC carrier
x-hdl:
busgroup: True
iogroup: carrier_csr
children:
- reg:
name: carrier
address: 0x00000000
width: 32
access: ro
description: Carrier type and PCB version
children:
- field:
name: pcb_rev
range: 4-0
description: PCB revision
comment: |
Binary coded PCB layout revision.
- field:
name: reserved
range: 15-5
description: Reserved register
comment: |
Ignore on read, write with 0's.
- field:
name: type
range: 31-16
description: Carrier type
comment: |
Carrier type identifier
1 = SPEC
2 = SVEC
3 = VFC
4 = SPEXI
- reg:
name: stat
address: 0x00000004
width: 32
access: ro
description: Status
children:
- field:
name: fmc0_pres
range: 0
description: FMC 1 presence
comment: |
0: FMC slot 1 is populated
1: FMC slot 1 is not populated.
- field:
name: fmc1_pres
range: 1
description: FMC 2 presence
comment: |
0: FMC slot 2 is populated
1: FMC slot 2 is not populated.
- field:
name: sys_pll_lck
range: 2
description: System clock PLL status
comment: |
0: not locked
1: locked.
- field:
name: ddr0_cal_done
range: 3
description: DDR3 bank 4 calibration status
comment: |
0: not done
1: done.
- field:
name: ddr1_cal_done
range: 4
description: DDR3 bank 5 calibration status
comment: |
0: not done
1: done.
- reg:
name: ctrl
address: 0x00000008
width: 32
access: rw
description: Control
children:
- field:
name: fp_leds_man
range: 15-0
description: Front panel LED manual control
comment: |
Height front panel LED, two bits per LED.
00 = OFF
01 = Green
10 = Red
11 = Orange
- reg:
name: rst
address: 0x0000000c
width: 32
access: wo
description: Reset Register
comment: |
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
children:
- field:
name: fmc0
range: 0
description: State of the FMC 1 reset line
comment: |
write 0: Normal FMC operation
write 1: FMC is held in reset
- field:
name: fmc1
range: 1
description: State of the FMC 2 reset line
comment: |
write 0: Normal FMC operation
write 1: FMC is held in reset
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ 4e6378bd
...@@ -35,23 +35,16 @@ use UNISIM.vcomponents.all; ...@@ -35,23 +35,16 @@ use UNISIM.vcomponents.all;
library work; library work;
use work.vme64x_pkg.all;
use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all; use work.fmc_adc_mezzanine_pkg.all;
use work.synthesis_descriptor.all;
use work.svec_carrier_csr_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all; use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
entity svec_ref_fmc_adc_100Ms is entity svec_ref_fmc_adc_100Ms is
generic( generic(
g_SIMULATION : integer := 0; g_SIMULATION : integer := 0;
g_NB_FMC_SLOTS : natural := 2; g_NB_FMC_SLOTS : natural := 2;
g_MULTISHOT_RAM_SIZE : natural := 8192; g_MULTISHOT_RAM_SIZE : natural := 8192;
g_CALIB_SOFT_IP : string := "TRUE";
g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram"); g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram");
port port
( (
...@@ -88,7 +81,7 @@ entity svec_ref_fmc_adc_100Ms is ...@@ -88,7 +81,7 @@ entity svec_ref_fmc_adc_100Ms is
pcbrev_i : in std_logic_vector(4 downto 0); pcbrev_i : in std_logic_vector(4 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID) -- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
carrier_onewire_b : inout std_logic; onewire_b : inout std_logic;
-- SFP -- SFP
sfp_txp_o : out std_logic; sfp_txp_o : out std_logic;
...@@ -114,10 +107,10 @@ entity svec_ref_fmc_adc_100Ms is ...@@ -114,10 +107,10 @@ entity svec_ref_fmc_adc_100Ms is
uart_txd_o : out std_logic; uart_txd_o : out std_logic;
-- GPIO -- GPIO
fp_gpio1_o : out std_logic; -- PPS output fp_gpio1_b : out std_logic; -- PPS output
fp_gpio2_o : out std_logic; -- not used fp_gpio2_b : out std_logic; -- not used
fp_gpio3_o : out std_logic; -- not used fp_gpio3_b : in std_logic; -- ext 10MHz clock input
fp_gpio4_o : out std_logic; -- not used fp_gpio4_b : in std_logic; -- ext PPS input
fp_term_en_o : out std_logic_vector(4 downto 1); fp_term_en_o : out std_logic_vector(4 downto 1);
fp_gpio1_a2b_o : out std_logic; fp_gpio1_a2b_o : out std_logic;
fp_gpio2_a2b_o : out std_logic; fp_gpio2_a2b_o : out std_logic;
...@@ -127,7 +120,7 @@ entity svec_ref_fmc_adc_100Ms is ...@@ -127,7 +120,7 @@ entity svec_ref_fmc_adc_100Ms is
-- VME interface -- VME interface
------------------------------------------ ------------------------------------------
vme_write_n_i : in std_logic; vme_write_n_i : in std_logic;
vme_rst_n_i : in std_logic; vme_sysreset_n_i : in std_logic;
vme_retry_oe_o : out std_logic; vme_retry_oe_o : out std_logic;
vme_retry_n_o : out std_logic; vme_retry_n_o : out std_logic;
vme_lword_n_b : inout std_logic; vme_lword_n_b : inout std_logic;
...@@ -153,24 +146,43 @@ entity svec_ref_fmc_adc_100Ms is ...@@ -153,24 +146,43 @@ entity svec_ref_fmc_adc_100Ms is
------------------------------------------ ------------------------------------------
-- DDR (banks 4 and 5) -- DDR (banks 4 and 5)
------------------------------------------ ------------------------------------------
ddr_a_o : out std_logic_vector(14*g_NB_FMC_SLOTS-1 downto 0); ddr4_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(3*g_NB_FMC_SLOTS-1 downto 0); ddr4_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_ck_p_o : out std_logic;
ddr_cke_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(16*g_NB_FMC_SLOTS-1 downto 0); ddr4_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_odt_o : out std_logic;
ddr_ras_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_rzq_b : inout std_logic;
ddr_udm_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); ddr4_we_n_o : out std_logic;
ddr5_a_o : out std_logic_vector(13 downto 0);
ddr5_ba_o : out std_logic_vector(2 downto 0);
ddr5_cas_n_o : out std_logic;
ddr5_ck_n_o : out std_logic;
ddr5_ck_p_o : out std_logic;
ddr5_cke_o : out std_logic;
ddr5_dq_b : inout std_logic_vector(15 downto 0);
ddr5_ldm_o : out std_logic;
ddr5_ldqs_n_b : inout std_logic;
ddr5_ldqs_p_b : inout std_logic;
ddr5_odt_o : out std_logic;
ddr5_ras_n_o : out std_logic;
ddr5_reset_n_o : out std_logic;
ddr5_rzq_b : inout std_logic;
ddr5_udm_o : out std_logic;
ddr5_udqs_n_b : inout std_logic;
ddr5_udqs_p_b : inout std_logic;
ddr5_we_n_o : out std_logic;
------------------------------------------ ------------------------------------------
-- FMC slots -- FMC slots
...@@ -213,156 +225,33 @@ entity svec_ref_fmc_adc_100Ms is ...@@ -213,156 +225,33 @@ entity svec_ref_fmc_adc_100Ms is
------------------------------------------ ------------------------------------------
-- FMC slot management -- FMC slot management
------------------------------------------ ------------------------------------------
fmc_prsnt_m2c_n_i : in std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); -- Mezzanine present (active low) fmc0_prsnt_m2c_n_i : in std_logic;
fmc_scl_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0); -- Mezzanine system I2C clock (EEPROM) fmc1_prsnt_m2c_n_i : in std_logic;
fmc_sda_b : inout std_logic_vector(g_NB_FMC_SLOTS-1 downto 0)); -- Mezzanine system I2C data (EEPROM)
end svec_ref_fmc_adc_100Ms;
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
fmc1_scl_b : inout std_logic;
fmc1_sda_b : inout std_logic);
architecture rtl of svec_ref_fmc_adc_100Ms is end svec_ref_fmc_adc_100Ms;
function f_ddr_bank_sel (
constant idx : natural) architecture arch of svec_ref_fmc_adc_100Ms is
return string is
begin
if idx = 0 then
return "SVEC_BANK4_64B_32B";
else
return "SVEC_BANK5_64B_32B";
end if;
end function f_ddr_bank_sel;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- SDB crossbar constants declaration -- Constants declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves on the wishbone crossbar -- Number of slaves on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 9; constant c_NUM_WB_SLAVES : integer := 3;
-- Wishbone master(s)
constant c_WB_MASTER_VME : integer := 0;
-- Wishbone slave(s) -- Wishbone slave(s)
-- IMPORTANT: FMC1 peripherals need always be at +3 index offset from the constant c_WB_SLAVE_METADATA : integer := 0;
-- respective FMC0 ones, in order for the FMC+DDR generating loop to work constant c_WB_SLAVE_FMC0_ADC : integer := 1; -- FMC slot 1 ADC mezzanine
constant c_WB_SLAVE_SVEC_CSR : integer := 0; -- SVEC control and status registers constant c_WB_SLAVE_FMC1_ADC : integer := 2; -- FMC slot 2 ADC mezzanine
constant c_WB_SLAVE_VIC : integer := 1; -- Vectored interrupt controller
constant c_WB_SLAVE_FMC0_ADC : integer := 2; -- FMC slot 1 ADC mezzanine
constant c_WB_SLAVE_FMC0_DDR_ADR : integer := 3; -- FMC slot 1 DDR address
constant c_WB_SLAVE_FMC0_DDR_DAT : integer := 4; -- FMC slot 1 DDR data
constant c_WB_SLAVE_FMC1_ADC : integer := 5; -- FMC slot 2 ADC mezzanine
constant c_WB_SLAVE_FMC1_DDR_ADR : integer := 6; -- FMC slot 2 DDR address
constant c_WB_SLAVE_FMC1_DDR_DAT : integer := 7; -- FMC slot 2 DDR data
constant c_WB_SLAVE_WR_CORE : integer := 8; -- WR PTP core
-- SDB meta info
constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_SLAVES;
constant c_SDB_SYNTHESIS : integer := c_NUM_WB_SLAVES + 1;
-- Devices sdb description
constant c_WB_SVEC_CSR_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00006603",
version => x"00000001",
date => x"20121116",
name => "WB-SVEC-CSR ")));
constant c_WB_DDR_DAT_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000FFF",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"10006610",
version => x"00000001",
date => x"20130704",
name => "WB-DDR-Data-Access ")));
constant c_WB_DDR_ADR_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000003",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"10006611",
version => x"00000001",
date => x"20130704",
name => "WB-DDR-Addr-Access ")));
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_FMC0_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_FMC1_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_WR_CORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) :=
(
c_WB_SLAVE_SVEC_CSR => f_sdb_embed_device(c_WB_SVEC_CSR_SDB, x"00001200"),
c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00001300"),
c_WB_SLAVE_FMC0_ADC => f_sdb_embed_bridge(c_FMC0_BRIDGE_SDB, x"00002000"),
c_WB_SLAVE_FMC0_DDR_ADR => f_sdb_embed_device(c_WB_DDR_ADR_SDB, x"00004000"),
c_WB_SLAVE_FMC0_DDR_DAT => f_sdb_embed_device(c_WB_DDR_DAT_SDB, x"00005000"),
c_WB_SLAVE_FMC1_ADC => f_sdb_embed_bridge(c_FMC1_BRIDGE_SDB, x"00006000"),
c_WB_SLAVE_FMC1_DDR_ADR => f_sdb_embed_device(c_WB_DDR_ADR_SDB, x"00008000"),
c_WB_SLAVE_FMC1_DDR_DAT => f_sdb_embed_device(c_WB_DDR_DAT_SDB, x"00009000"),
c_WB_SLAVE_WR_CORE => f_sdb_embed_bridge(c_WR_CORE_BRIDGE_SDB, x"00040000"),
c_SDB_GIT_REPO_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL),
c_SDB_SYNTHESIS => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO));
-- VIC default vector setting
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00003500",
1 => x"00007500");
------------------------------------------------------------------------------ -- Convention metadata base address
-- Other constants declaration constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
------------------------------------------------------------------------------
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
others => c_AUXPLL_CFG_DEFAULT);
-- SVEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0002";
-- Conversion of g_simulation to string needed for DDR controller
function f_int2string (n : natural) return string is
begin
if n = 0 then
return "FALSE";
else
return "TRUE ";
end if;
end;
constant c_SIMULATION_STR : string := f_int2string(g_SIMULATION);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Signals declaration -- Signals declaration
...@@ -373,41 +262,15 @@ architecture rtl of svec_ref_fmc_adc_100Ms is ...@@ -373,41 +262,15 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
-- Clocks and resets -- Clocks and resets
signal clk_sys_62m5 : std_logic; signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic; signal clk_ref_125m : std_logic;
signal sys_clk_pll_locked : std_logic; signal clk_ext_ref : std_logic;
signal clk_ddr_333m : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal rst_pll_aux_n : std_logic_vector(3 downto 0) := (others => '0');
signal areset_n : std_logic := '0';
signal rst_sys_62m5_n : std_logic := '0'; signal rst_sys_62m5_n : std_logic := '0';
signal rst_ref_125m_n : std_logic := '0'; signal rst_ref_125m_n : std_logic := '0';
signal rst_ddr_333m_n : std_logic := '0'; signal areset_n : std_logic := '0';
signal sw_rst_fmc : t_fmc_slot_vec := (others => '1');
signal sw_rst_fmc_sync : t_fmc_slot_vec := (others => '1');
signal fmc_rst_ref_n : t_fmc_slot_vec := (others => '0');
signal fmc_rst_sys_n : t_fmc_slot_vec := (others => '0');
signal ddr_rst : t_fmc_slot_vec := (others => '1');
attribute keep : string;
attribute keep of clk_sys_62m5 : signal is "TRUE";
attribute keep of clk_ref_125m : signal is "TRUE";
attribute keep of clk_ddr_333m : signal is "TRUE";
attribute keep of ddr_rst : signal is "TRUE";
-- VME
signal vme_data_b_out : std_logic_vector(31 downto 0);
signal vme_addr_b_out : std_logic_vector(31 downto 1);
signal vme_lword_n_b_out : std_logic;
signal Vme_data_dir_int : std_logic;
signal vme_addr_dir_int : std_logic;
signal vme_ga : std_logic_vector(5 downto 0);
signal vme_berr_n : std_logic;
signal vme_irq_n : std_logic_vector(7 downto 1);
signal vme_access : std_logic;
-- Wishbone buse(s) from master(s) to crossbar slave port(s) -- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_out : t_wishbone_master_out;
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_in : t_wishbone_master_in;
-- Wishbone buse(s) from crossbar master port(s) to slave(s) -- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
...@@ -421,210 +284,103 @@ architecture rtl of svec_ref_fmc_adc_100Ms is ...@@ -421,210 +284,103 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
signal fmc_wb_ddr_in : t_wishbone_master_data64_in_array(g_NB_FMC_SLOTS-1 downto 0); signal fmc_wb_ddr_in : t_wishbone_master_data64_in_array(g_NB_FMC_SLOTS-1 downto 0);
signal fmc_wb_ddr_out : t_wishbone_master_data64_out_array(g_NB_FMC_SLOTS-1 downto 0); signal fmc_wb_ddr_out : t_wishbone_master_data64_out_array(g_NB_FMC_SLOTS-1 downto 0);
type t_fmc_acq_led is array (0 to g_NB_FMC_SLOTS-1) of std_logic_vector(1 downto 0);
-- Interrupts and status -- Interrupts and status
signal ddr_wr_fifo_empty : t_fmc_slot_vec; signal ddr_wr_fifo_empty : t_fmc_slot_vec;
signal irq_to_vme : std_logic; signal ddr_wr_fifo_empty_sync : t_fmc_slot_vec;
signal fmc_irq : t_fmc_slot_vec; signal fmc_irq : t_fmc_slot_vec;
signal fmc_acq_trig : t_fmc_slot_vec;
signal fmc_acq_trig_sync : t_fmc_slot_vec;
signal fmc_acq_cfg_ok : t_fmc_slot_vec; signal fmc_acq_cfg_ok : t_fmc_slot_vec;
-- Resync interrupts to sys domain
signal ddr_wr_fifo_empty_sync : t_fmc_slot_vec;
signal fmc_irq_sync : t_fmc_slot_vec;
signal fmc_acq_cfg_ok_sync : t_fmc_slot_vec; signal fmc_acq_cfg_ok_sync : t_fmc_slot_vec;
signal fmc_acq_led : t_fmc_acq_led;
signal irq_vector : t_fmc_slot_vec;
signal vme_access : std_logic;
-- Front panel LED control -- Front panel LED control
signal svec_led : std_logic_vector(15 downto 0); signal svec_led : std_logic_vector(15 downto 0);
signal led_state : std_logic_vector(15 downto 0);
signal led_state_csr : std_logic_vector(15 downto 0);
-- DDR
type t_fmc_adc_ddr_status_array is array (natural range <>) of std_logic_vector(31 downto 0);
type t_fmc_adc_ddr_addr_cnt_array is array (natural range <>) of unsigned(31 downto 0);
signal ddr_status : t_fmc_adc_ddr_status_array(g_NB_FMC_SLOTS-1 downto 0);
signal ddr_calib_done : t_fmc_slot_vec;
signal ddr_addr_cnt : t_fmc_adc_ddr_addr_cnt_array(g_NB_FMC_SLOTS-1 downto 0);
signal ddr_dat_cyc_d : t_fmc_slot_vec;
signal ddr_addr_cnt_en : t_fmc_slot_vec;
-- SFP
signal sfp_scl_out : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_sda_in : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- White Rabbit
signal wrabbit_en : std_logic;
signal wrc_scl_out : std_logic;
signal wrc_scl_in : std_logic;
signal wrc_sda_out : std_logic;
signal wrc_sda_in : std_logic;
signal pps : std_logic;
signal pps_led : std_logic;
signal wr_led_act : std_logic;
signal wr_led_link : std_logic;
-- WR PTP core timing interface -- WR PTP core timing interface
signal tm_link_up : std_logic; signal tm_link_up : std_logic;
signal tm_tai : std_logic_vector(39 downto 0); signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0); signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic; signal tm_time_valid : std_logic;
signal tm_time_valid_sync : std_logic;
signal wrabbit_en : std_logic;
signal pps : std_logic;
signal pps_led : std_logic;
signal pps_ext_in : std_logic;
signal wr_led_link : std_logic;
signal wr_led_act : std_logic;
-- IO for CSR registers begin -- architecture arch
signal csr_regin : t_carrier_csr_master_in;
signal csr_regout : t_carrier_csr_master_out;
begin
------------------------------------------------------------------------------
-- Reset logic
------------------------------------------------------------------------------
areset_n <= vme_rst_n_i and rst_n_i;
sys_clk_pll_locked <= '1';
gen_fmc_rst : for I in 0 to g_NB_FMC_SLOTS-1 generate
-- reset for mezzanines
-- including soft reset, with re-sync from 62.5MHz domain
cmp_fmc_sw_reset_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => sw_rst_fmc(I),
synced_o => sw_rst_fmc_sync(I));
fmc_rst_ref_n(I) <= rst_ref_125m_n and not sw_rst_fmc_sync(I);
fmc_rst_sys_n(I) <= rst_sys_62m5_n and not sw_rst_fmc(I);
-- reset for DDR including soft reset.
-- This is treated as async and will be re-synced by the DDR controller
ddr_rst(I) <= not rst_ddr_333m_n or sw_rst_fmc(I);
end generate gen_fmc_rst;
------------------------------------------------------------------------------
-- VME interface
------------------------------------------------------------------------------
cmp_vme_core : xvme64x_core areset_n <= vme_sysreset_n_i and rst_n_i;
generic map (
g_CLOCK_PERIOD => 16,
g_DECODE_AM => TRUE,
g_USER_CSR_EXT => FALSE,
g_WB_GRANULARITY => BYTE,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
vme_i.as_n => vme_as_n_i,
vme_i.rst_n => vme_rst_n_i,
vme_i.write_n => vme_write_n_i,
vme_i.am => vme_am_i,
vme_i.ds_n => vme_ds_n_i,
vme_i.ga => vme_ga,
vme_i.lword_n => vme_lword_n_b,
vme_i.addr => vme_addr_b,
vme_i.data => vme_data_b,
vme_i.iack_n => vme_iack_n_i,
vme_i.iackin_n => vme_iackin_n_i,
vme_o.berr_n => vme_berr_n,
vme_o.dtack_n => vme_dtack_n_o,
vme_o.retry_n => vme_retry_n_o,
vme_o.retry_oe => vme_retry_oe_o,
vme_o.lword_n => vme_lword_n_b_out,
vme_o.data => vme_data_b_out,
vme_o.addr => vme_addr_b_out,
vme_o.irq_n => vme_irq_n,
vme_o.iackout_n => vme_iackout_n_o,
vme_o.dtack_oe => vme_dtack_oe_o,
vme_o.data_dir => vme_data_dir_int,
vme_o.data_oe_n => vme_data_oe_n_o,
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_o => cnx_master_out(c_WB_MASTER_VME),
wb_i => cnx_master_in(c_WB_MASTER_VME),
int_i => irq_to_vme);
vme_ga <= vme_gap_i & vme_ga_i;
vme_berr_o <= not vme_berr_n;
vme_irq_o <= not vme_irq_n;
-- VME tri-state buffers
vme_data_b <= vme_data_b_out when vme_data_dir_int = '1' else (others => 'Z');
vme_addr_b <= vme_addr_b_out when vme_addr_dir_int = '1' else (others => 'Z');
vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
vme_addr_dir_o <= vme_addr_dir_int;
vme_data_dir_o <= vme_data_dir_int;
------------------------------------------------------------------------------ inst_svec_base : entity work.svec_base_wr
-- Primary wishbone crossbar
------------------------------------------------------------------------------
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map (
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_WRAPAROUND => TRUE,
g_LAYOUT => c_INTERCONNECT_LAYOUT,
g_SDB_ADDR => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
-------------------------------------------------------------------------------
-- White Rabbit Core (SVEC board package)
-------------------------------------------------------------------------------
-- Tristates for Carrier EEPROM
carrier_scl_b <= '0' when (wrc_scl_out = '0') else 'Z';
carrier_sda_b <= '0' when (wrc_sda_out = '0') else 'Z';
wrc_scl_in <= carrier_scl_b;
wrc_sda_in <= carrier_sda_b;
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- Tristates for Carrier OneWire
carrier_onewire_b <= '0' when onewire_oe = '1' else 'Z';
onewire_data <= carrier_onewire_b;
cmp_xwrc_board_svec : xwrc_board_svec
generic map ( generic map (
g_SIMULATION => g_SIMULATION, g_WITH_VIC => TRUE,
g_WITH_EXTERNAL_CLOCK_INPUT => FALSE, g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_WR => TRUE,
g_WITH_DDR4 => TRUE,
g_WITH_DDR5 => TRUE,
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 2,
g_DPRAM_INITF => g_WRPC_INITF, g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG, g_AUX_CLKS => 0,
g_FABRIC_IFACE => PLAIN) g_FABRIC_IFACE => plain,
g_SIMULATION => g_SIMULATION)
port map ( port map (
clk_20m_vcxo_i => clk_20m_vcxo_i, rst_n_i => areset_n,
clk_125m_pllref_p_i => clk_125m_pllref_p_i, clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i, clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i, clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i, clk_125m_gtp_p_i => clk_125m_gtp_p_i,
areset_n_i => areset_n, clk_10m_ext_i => clk_ext_ref,
clk_sys_62m5_o => clk_sys_62m5, pps_ext_i => pps_ext_in,
clk_ref_125m_o => clk_ref_125m, vme_write_n_i => vme_write_n_i,
clk_pll_aux_o => clk_pll_aux, vme_sysreset_n_i => vme_sysreset_n_i,
rst_sys_62m5_n_o => rst_sys_62m5_n, vme_retry_oe_o => vme_retry_oe_o,
rst_ref_125m_n_o => rst_ref_125m_n, vme_retry_n_o => vme_retry_n_o,
rst_pll_aux_n_o => rst_pll_aux_n, vme_lword_n_b => vme_lword_n_b,
vme_iackout_n_o => vme_iackout_n_o,
vme_iackin_n_i => vme_iackin_n_i,
vme_iack_n_i => vme_iack_n_i,
vme_gap_i => vme_gap_i,
vme_dtack_oe_o => vme_dtack_oe_o,
vme_dtack_n_o => vme_dtack_n_o,
vme_ds_n_i => vme_ds_n_i,
vme_data_oe_n_o => vme_data_oe_n_o,
vme_data_dir_o => vme_data_dir_o,
vme_berr_o => vme_berr_o,
vme_as_n_i => vme_as_n_i,
vme_addr_oe_n_o => vme_addr_oe_n_o,
vme_addr_dir_o => vme_addr_dir_o,
vme_irq_o => vme_irq_o,
vme_ga_i => vme_ga_i,
vme_data_b => vme_data_b,
vme_am_i => vme_am_i,
vme_addr_b => vme_addr_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc1_scl_b => fmc1_scl_b,
fmc1_sda_b => fmc1_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
fmc1_prsnt_m2c_n_i => fmc1_prsnt_m2c_n_i,
onewire_b => onewire_b,
carrier_scl_b => carrier_scl_b,
carrier_sda_b => carrier_sda_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
plldac_sclk_o => pll20dac_sclk_o,
plldac_din_o => pll20dac_din_o,
pll20dac_din_o => pll20dac_din_o, pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o, pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o, pll20dac_sync_n_o => pll20dac_sync_n_o,
...@@ -635,99 +391,109 @@ begin ...@@ -635,99 +391,109 @@ begin
sfp_txn_o => sfp_txn_o, sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i, sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i, sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i, sfp_mod_def0_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in, sfp_mod_def1_b => sfp_mod_def1_b,
sfp_sda_o => sfp_sda_out, sfp_mod_def2_b => sfp_mod_def2_b,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o, sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i, sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o, sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i, sfp_los_i => sfp_los_i,
eeprom_sda_i => wrc_sda_in, ddr4_a_o => ddr4_a_o,
eeprom_sda_o => wrc_sda_out, ddr4_ba_o => ddr4_ba_o,
eeprom_scl_i => wrc_scl_in, ddr4_cas_n_o => ddr4_cas_n_o,
eeprom_scl_o => wrc_scl_out, ddr4_ck_n_o => ddr4_ck_n_o,
onewire_i => onewire_data, ddr4_ck_p_o => ddr4_ck_p_o,
onewire_oen_o => onewire_oe, ddr4_cke_o => ddr4_cke_o,
uart_rxd_i => uart_rxd_i, ddr4_dq_b => ddr4_dq_b,
uart_txd_o => uart_txd_o, ddr4_ldm_o => ddr4_ldm_o,
spi_sclk_o => spi_sclk_o, ddr4_ldqs_n_b => ddr4_ldqs_n_b,
spi_ncs_o => spi_ncs_o, ddr4_ldqs_p_b => ddr4_ldqs_p_b,
spi_mosi_o => spi_mosi_o, ddr4_odt_o => ddr4_odt_o,
spi_miso_i => spi_miso_i, ddr4_ras_n_o => ddr4_ras_n_o,
wb_slave_o => cnx_slave_out(c_WB_SLAVE_WR_CORE), ddr4_reset_n_o => ddr4_reset_n_o,
wb_slave_i => cnx_slave_in(c_WB_SLAVE_WR_CORE), ddr4_rzq_b => ddr4_rzq_b,
ddr4_udm_o => ddr4_udm_o,
ddr4_udqs_n_b => ddr4_udqs_n_b,
ddr4_udqs_p_b => ddr4_udqs_p_b,
ddr4_we_n_o => ddr4_we_n_o,
ddr5_a_o => ddr5_a_o,
ddr5_ba_o => ddr5_ba_o,
ddr5_cas_n_o => ddr5_cas_n_o,
ddr5_ck_n_o => ddr5_ck_n_o,
ddr5_ck_p_o => ddr5_ck_p_o,
ddr5_cke_o => ddr5_cke_o,
ddr5_dq_b => ddr5_dq_b,
ddr5_ldm_o => ddr5_ldm_o,
ddr5_ldqs_n_b => ddr5_ldqs_n_b,
ddr5_ldqs_p_b => ddr5_ldqs_p_b,
ddr5_odt_o => ddr5_odt_o,
ddr5_ras_n_o => ddr5_ras_n_o,
ddr5_reset_n_o => ddr5_reset_n_o,
ddr5_rzq_b => ddr5_rzq_b,
ddr5_udm_o => ddr5_udm_o,
ddr5_udqs_n_b => ddr5_udqs_n_b,
ddr5_udqs_p_b => ddr5_udqs_p_b,
ddr5_we_n_o => ddr5_we_n_o,
pcbrev_i => pcbrev_i,
ddr4_clk_i => clk_ref_125m,
ddr4_rst_n_i => rst_ref_125m_n,
ddr4_wb_i => fmc_wb_ddr_out(0),
ddr4_wb_o => fmc_wb_ddr_in(0),
ddr5_clk_i => clk_ref_125m,
ddr5_rst_n_i => rst_ref_125m_n,
ddr5_wb_i => fmc_wb_ddr_out(1),
ddr5_wb_o => fmc_wb_ddr_in(1),
ddr4_wr_fifo_empty_o => ddr_wr_fifo_empty(0),
ddr5_wr_fifo_empty_o => ddr_wr_fifo_empty(1),
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => clk_ref_125m,
rst_ref_125m_n_o => rst_ref_125m_n,
irq_user_i => irq_vector,
tm_link_up_o => tm_link_up, tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid, tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai, tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles, tm_cycles_o => tm_cycles,
pps_p_o => pps, pps_p_o => pps,
pps_led_o => pps_led, pps_led_o => pps_led,
link_ok_o => wrabbit_en,
led_link_o => wr_led_link, led_link_o => wr_led_link,
led_act_o => wr_led_act, led_act_o => wr_led_act,
link_ok_o => wrabbit_en); app_wb_o => cnx_master_out,
app_wb_i => cnx_master_in);
clk_ddr_333m <= clk_pll_aux(0);
rst_ddr_333m_n <= rst_pll_aux_n(0);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Carrier CSR -- Primary wishbone crossbar
-- Carrier type and PCB version
-- Carrier status (PLL, FMC presence)
-- Front panel LED manual control
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_carrier_csr : entity work.svec_carrier_csr cmp_crossbar : entity work.svec_ref_fmc_adc_100m_mmap
port map ( port map (
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5, clk_i => clk_sys_62m5,
wb_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR), wb_i => cnx_master_out,
wb_o => cnx_slave_out(c_WB_SLAVE_SVEC_CSR), wb_o => cnx_master_in,
carrier_csr_i => csr_regin, metadata_i => cnx_slave_out(c_WB_SLAVE_METADATA),
carrier_csr_o => csr_regout); metadata_o => cnx_slave_in(c_WB_SLAVE_METADATA),
fmc1_adc_mezzanine_i => cnx_slave_out(c_WB_SLAVE_FMC0_ADC),
csr_regin.carrier_pcb_rev <= pcbrev_i; fmc1_adc_mezzanine_o => cnx_slave_in(c_WB_SLAVE_FMC0_ADC),
csr_regin.carrier_reserved <= (others => '0'); fmc2_adc_mezzanine_i => cnx_slave_out(c_WB_SLAVE_FMC1_ADC),
csr_regin.carrier_type <= c_CARRIER_TYPE; fmc2_adc_mezzanine_o => cnx_slave_in(c_WB_SLAVE_FMC1_ADC));
csr_regin.stat_fmc0_pres <= fmc_prsnt_m2c_n_i(0);
csr_regin.stat_fmc1_pres <= fmc_prsnt_m2c_n_i(1);
csr_regin.stat_sys_pll_lck <= sys_clk_pll_locked;
csr_regin.stat_ddr0_cal_done <= ddr_calib_done(0);
csr_regin.stat_ddr1_cal_done <= ddr_calib_done(1);
led_state_csr <= csr_regout.ctrl_fp_leds_man;
sw_rst_fmc(0) <= csr_regout.rst_fmc0;
sw_rst_fmc(1) <= csr_regout.rst_fmc1;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC) -- Application-specific metadata ROM
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
gen_fmc_irq : for I in 0 to g_NB_FMC_SLOTS - 1 generate cmp_xwb_metadata : entity work.xwb_metadata
cmp_fmc_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc_irq(I),
synced_o => fmc_irq_sync(I));
end generate gen_fmc_irq;
cmp_vic : xwb_vic
generic map ( generic map (
g_INTERFACE_MODE => PIPELINED, g_VENDOR_ID => x"0000_10DC",
g_ADDRESS_GRANULARITY => BYTE, g_DEVICE_ID => x"4144_4302", -- "ADC2"
g_NUM_INTERRUPTS => 2, g_VERSION => x"0100_0000",
g_INIT_VECTORS => c_VIC_VECTOR_TABLE) g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map ( port map (
clk_sys_i => clk_sys_62m5, clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in(c_WB_SLAVE_VIC), wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
slave_o => cnx_slave_out(c_WB_SLAVE_VIC), wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
irqs_i(0) => fmc_irq_sync(0),
irqs_i(1) => fmc_irq_sync(1),
irq_master_o => irq_to_vme);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- FMC ADC mezzanines (wb bridge with cross-clocking) -- FMC ADC mezzanines (wb bridge with cross-clocking)
...@@ -738,16 +504,26 @@ begin ...@@ -738,16 +504,26 @@ begin
-- Mezzanine 1-wire master -- Mezzanine 1-wire master
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_tm_time_valid_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => tm_time_valid,
synced_o => tm_time_valid_sync);
gen_fmc_mezzanine : for I in 0 to g_NB_FMC_SLOTS - 1 generate gen_fmc_mezzanine : for I in 0 to g_NB_FMC_SLOTS - 1 generate
cmp_xwb_clock_bridge : xwb_clock_bridge cmp_xwb_clock_bridge : xwb_clock_bridge
generic map (
g_SLAVE_PORT_WB_MODE => CLASSIC,
g_MASTER_PORT_WB_MODE => PIPELINED)
port map ( port map (
slave_clk_i => clk_sys_62m5, slave_clk_i => clk_sys_62m5,
slave_rst_n_i => fmc_rst_sys_n(I), slave_rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in(c_WB_SLAVE_FMC0_ADC + 3*I), slave_i => cnx_slave_in(c_WB_SLAVE_FMC0_ADC + I),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC0_ADC + 3*I), slave_o => cnx_slave_out(c_WB_SLAVE_FMC0_ADC + I),
master_clk_i => clk_ref_125m, master_clk_i => clk_ref_125m,
master_rst_n_i => fmc_rst_ref_n(I), master_rst_n_i => rst_ref_125m_n,
master_i => cnx_fmc_sync_master_in(I), master_i => cnx_fmc_sync_master_in(I),
master_o => cnx_fmc_sync_master_out(I)); master_o => cnx_fmc_sync_master_out(I));
...@@ -758,25 +534,33 @@ begin ...@@ -758,25 +534,33 @@ begin
data_i => ddr_wr_fifo_empty(I), data_i => ddr_wr_fifo_empty(I),
synced_o => ddr_wr_fifo_empty_sync(I)); synced_o => ddr_wr_fifo_empty_sync(I));
cmp_fmc_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc_irq(I),
synced_o => irq_vector(I));
cmp_fmc_adc_mezzanine : fmc_adc_mezzanine cmp_fmc_adc_mezzanine : fmc_adc_mezzanine
generic map ( generic map (
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE, g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE,
g_SPARTAN6_USE_PLL => TRUE,
g_WB_MODE => PIPELINED, g_WB_MODE => PIPELINED,
g_WB_GRANULARITY => BYTE) g_WB_GRANULARITY => BYTE)
port map ( port map (
sys_clk_i => clk_ref_125m, sys_clk_i => clk_ref_125m,
sys_rst_n_i => fmc_rst_ref_n(I), sys_rst_n_i => rst_ref_125m_n,
wb_csr_slave_i => cnx_fmc_sync_master_out(I), wb_csr_slave_i => cnx_fmc_sync_master_out(I),
wb_csr_slave_o => cnx_fmc_sync_master_in(I), wb_csr_slave_o => cnx_fmc_sync_master_in(I),
wb_ddr_clk_i => clk_ref_125m, wb_ddr_clk_i => clk_ref_125m,
wb_ddr_rst_n_i => fmc_rst_ref_n(I), wb_ddr_rst_n_i => rst_ref_125m_n,
wb_ddr_master_i => fmc_wb_ddr_in(I), wb_ddr_master_i => fmc_wb_ddr_in(I),
wb_ddr_master_o => fmc_wb_ddr_out(I), wb_ddr_master_o => fmc_wb_ddr_out(I),
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty_sync(I), ddr_wr_fifo_empty_i => ddr_wr_fifo_empty_sync(I),
trig_irq_o => open, trig_irq_o => fmc_acq_trig(I),
acq_end_irq_o => open, acq_end_irq_o => open,
eic_irq_o => fmc_irq(I), eic_irq_o => fmc_irq(I),
acq_cfg_ok_o => fmc_acq_cfg_ok(I), acq_cfg_ok_o => fmc_acq_cfg_ok(I),
...@@ -816,179 +600,14 @@ begin ...@@ -816,179 +600,14 @@ begin
mezz_one_wire_b => adc_one_wire_b(I), mezz_one_wire_b => adc_one_wire_b(I),
sys_scl_b => fmc_scl_b(I),
sys_sda_b => fmc_sda_b(I),
wr_tm_link_up_i => tm_link_up, wr_tm_link_up_i => tm_link_up,
wr_tm_time_valid_i => tm_time_valid, wr_tm_time_valid_i => tm_time_valid_sync,
wr_tm_tai_i => tm_tai, wr_tm_tai_i => tm_tai,
wr_tm_cycles_i => tm_cycles, wr_tm_cycles_i => tm_cycles,
wr_enable_i => wrabbit_en); wr_enable_i => wrabbit_en);
end generate gen_fmc_mezzanine; end generate gen_fmc_mezzanine;
------------------------------------------------------------------------------
-- DDR controllers (banks 4 and 5)
------------------------------------------------------------------------------
gen_ddr_ctrl : for I in 0 to g_NB_FMC_SLOTS - 1 generate
cmp_ddr_ctrl_bank : ddr3_ctrl
generic map (
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
g_BANK_PORT_SELECT => f_ddr_bank_sel(I),
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => c_SIMULATION_STR,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => clk_ddr_333m,
rst_n_i => ddr_rst(I),
status_o => ddr_status(I),
ddr3_dq_b => ddr_dq_b(16*(I+1)-1 downto 16*I),
ddr3_a_o => ddr_a_o(14*(I+1)-1 downto 14*I),
ddr3_ba_o => ddr_ba_o(3*(I+1)-1 downto 3*I),
ddr3_ras_n_o => ddr_ras_n_o(I),
ddr3_cas_n_o => ddr_cas_n_o(I),
ddr3_we_n_o => ddr_we_n_o(I),
ddr3_odt_o => ddr_odt_o(I),
ddr3_rst_n_o => ddr_reset_n_o(I),
ddr3_cke_o => ddr_cke_o(I),
ddr3_dm_o => ddr_ldm_o(I),
ddr3_udm_o => ddr_udm_o(I),
ddr3_dqs_p_b => ddr_ldqs_p_b(I),
ddr3_dqs_n_b => ddr_ldqs_n_b(I),
ddr3_udqs_p_b => ddr_udqs_p_b(I),
ddr3_udqs_n_b => ddr_udqs_n_b(I),
ddr3_clk_p_o => ddr_ck_p_o(I),
ddr3_clk_n_o => ddr_ck_n_o(I),
ddr3_rzq_b => ddr_rzq_b(I),
wb0_rst_n_i => fmc_rst_ref_n(I),
wb0_clk_i => clk_ref_125m,
wb0_sel_i => fmc_wb_ddr_out(I).sel,
wb0_cyc_i => fmc_wb_ddr_out(I).cyc,
wb0_stb_i => fmc_wb_ddr_out(I).stb,
wb0_we_i => fmc_wb_ddr_out(I).we,
wb0_addr_i => fmc_wb_ddr_out(I).adr,
wb0_data_i => fmc_wb_ddr_out(I).dat,
wb0_data_o => fmc_wb_ddr_in(I).dat,
wb0_ack_o => fmc_wb_ddr_in(I).ack,
wb0_stall_o => fmc_wb_ddr_in(I).stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr_wr_fifo_empty(I),
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_sys_62m5_n,
wb1_clk_i => clk_sys_62m5,
wb1_sel_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).sel,
wb1_cyc_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).cyc,
wb1_stb_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).stb,
wb1_we_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).we,
wb1_data_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).dat,
wb1_addr_i => std_logic_vector(ddr_addr_cnt(I)),
wb1_data_o => cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).dat,
wb1_ack_o => cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).ack,
wb1_stall_o => cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
fmc_wb_ddr_in(I).err <= '0';
fmc_wb_ddr_in(I).rty <= '0';
ddr_calib_done(I) <= ddr_status(I)(0);
-- DDR address counter
-- The address counter is set by writing to the c_WB_SLAVE_FMC_DDR_ADR wb peripheral.
-- Then the counter is incremented on every access to the c_WB_SLAVE_FMC_DDR_DAT wb peripheral.
-- The counter is incremented on the falling edge of cyc. This is because the ddr controller
-- samples the address on (cyc_re and stb)+1
p_ddr_dat_cyc : process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
ddr_dat_cyc_d(I) <= '0';
else
ddr_dat_cyc_d(I) <= cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).cyc;
end if;
end if;
end process p_ddr_dat_cyc;
ddr_addr_cnt_en(I) <= not(cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).cyc) and ddr_dat_cyc_d(I);
-- address counter
p_ddr_addr_cnt : process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
ddr_addr_cnt(I) <= (others => '0');
elsif (cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).we = '1' and
cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).stb = '1' and
cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).cyc = '1') then
ddr_addr_cnt(I) <= unsigned(cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).dat);
elsif (ddr_addr_cnt_en(I) = '1') then
ddr_addr_cnt(I) <= ddr_addr_cnt(I) + 1;
end if;
end if;
end process p_ddr_addr_cnt;
-- ack generation
p_ddr_addr_ack : process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).ack <= '0';
elsif (cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).stb = '1' and
cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).cyc = '1') then
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).ack <= '1';
else
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).ack <= '0';
end if;
end if;
end process p_ddr_addr_ack;
-- Address counter read back
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).dat <= std_logic_vector(ddr_addr_cnt(I));
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).err <= '0';
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT + 3*I).rty <= '0';
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).err <= '0';
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).rty <= '0';
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR + 3*I).stall <= '0';
end generate gen_ddr_ctrl;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs -- Carrier front panel LEDs and LEMOs
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -1013,7 +632,7 @@ begin ...@@ -1013,7 +632,7 @@ begin
port map ( port map (
clk_i => clk_sys_62m5, clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_WB_MASTER_VME).cyc, pulse_i => cnx_master_out.cyc,
extended_o => vme_access); extended_o => vme_access);
gen_fmc_led : for I in 0 to g_NB_FMC_SLOTS - 1 generate gen_fmc_led : for I in 0 to g_NB_FMC_SLOTS - 1 generate
...@@ -1025,33 +644,48 @@ begin ...@@ -1025,33 +644,48 @@ begin
data_i => fmc_acq_cfg_ok(I), data_i => fmc_acq_cfg_ok(I),
synced_o => fmc_acq_cfg_ok_sync(I)); synced_o => fmc_acq_cfg_ok_sync(I));
end generate gen_fmc_led; cmp_fmc_trig_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc_acq_trig(I),
synced_o => fmc_acq_trig_sync(I));
-- Logic OR of signals and CSR register for LED control p_fmc_acq_led: process (fmc_acq_cfg_ok_sync) is
svec_led <= led_state or led_state_csr; begin
if fmc_acq_cfg_ok_sync(I) = '0' then
fmc_acq_led(I) <= c_LED_RED;
elsif fmc_acq_trig_sync(I) = '1' then
fmc_acq_led(I) <= c_LED_RED_GREEN;
else
fmc_acq_led(I) <= c_LED_GREEN;
end if;
end process p_fmc_acq_led;
end generate gen_fmc_led;
-- LED order on front panel (top to bottom) -- LED order on front panel (top to bottom)
-- 1..0 | 9..8 -- 1..0 | 9..8
-- 3..2 | 11..10 -- 3..2 | 11..10
-- 5..4 | 13..12 -- 5..4 | 13..12
-- 7..6 | 15..14 -- 7..6 | 15..14
led_state(1 downto 0) <= c_led_off; svec_led(1 downto 0) <= c_LED_GREEN when wr_led_link = '1' else c_LED_RED;
led_state(3 downto 2) <= c_led_green when fmc_acq_cfg_ok_sync(0) = '1' else c_led_red; svec_led(3 downto 2) <= fmc_acq_led(1);
led_state(5 downto 4) <= c_led_green when pps_led = '1' else c_led_off; svec_led(5 downto 4) <= c_LED_GREEN when tm_time_valid = '1'else c_LED_RED;
led_state(7 downto 6) <= c_led_green when wr_led_link = '1' else c_led_red; svec_led(7 downto 6) <= c_LED_RED_GREEN when vme_access = '1' else c_LED_OFF;
led_state(9 downto 8) <= c_led_red_green when vme_access = '1' else c_led_off; svec_led(9 downto 8) <= c_LED_RED_GREEN when wr_led_act = '1' else c_LED_OFF;
led_state(11 downto 10) <= c_led_green when fmc_acq_cfg_ok_sync(1) = '1' else c_led_red; svec_led(11 downto 10) <= fmc_acq_led(0);
led_state(13 downto 12) <= c_led_green when tm_time_valid = '1' else c_led_red; svec_led(13 downto 12) <= c_LED_OFF;
led_state(15 downto 14) <= c_led_red_green when wr_led_act = '1' else c_led_off; svec_led(15 downto 14) <= c_LED_GREEN when pps_led = '1' else c_LED_OFF;
-- Front panel IO configuration -- Front panel IO configuration
fp_gpio1_o <= pps; fp_gpio1_b <= pps;
fp_gpio2_o <= '0'; fp_gpio2_b <= '0';
fp_gpio3_o <= '0'; clk_ext_ref <= fp_gpio3_b;
fp_gpio4_o <= '0'; pps_ext_in <= fp_gpio4_b;
fp_term_en_o <= (others => '0'); fp_term_en_o <= (others => '0');
fp_gpio1_a2b_o <= '1'; fp_gpio1_a2b_o <= '1';
fp_gpio2_a2b_o <= '1'; fp_gpio2_a2b_o <= '1';
fp_gpio34_a2b_o <= '1'; fp_gpio34_a2b_o <= '0';
end rtl; end architecture arch;
software/Makefile 0 → 100644
View file @ 4e6378bd
-include Makefile.specific
# include parent_common.mk for buildsystem's defines
# use absolute path for REPO_PARENT
CURDIR:=$(shell /bin/pwd)
REPO_PARENT ?= $(CURDIR)/..
-include $(REPO_PARENT)/parent_common.mk
DIRS = drivers
all clean install: $(DIRS)
.PHONY: all clean install $(DIRS)
clean: TARGET = clean
install: TARGET = install
$(DIRS):
$(MAKE) -C $@ $(TARGET)
software/drivers/.gitignore 0 → 100644
View file @ 4e6378bd
.tmp_versions
*.ko
*.mod.c
*.o
*.o.cmd
*.ko.cmd
Module.symvers
modules.order
software/drivers/Kbuild 0 → 100644
View file @ 4e6378bd
# add versions of supermodule. It is useful when svec-sw is included as sub-module
# of a bigger project that we want to track
ifdef CONFIG_SUPER_REPO
ifdef CONFIG_SUPER_REPO_VERSION
SUBMODULE_VERSIONS += MODULE_INFO(version_$(CONFIG_SUPER_REPO),\"$(CONFIG_SUPER_REPO_VERSION)\");
endif
endif
# add versions of used submodules
ccflags-y += -DADDITIONAL_VERSIONS="$(SUBMODULE_VERSIONS)"
ccflags-y += -DDRV_VERSION=\"$(DRV_VERSION)\"
ccflags-y += -Wall -Werror
obj-$(CONFIG_FMC_ADC_SPEC) := fmc-adc-100m-ref-spec.o
obj-$(CONFIG_FMC_ADC_SVEC) := fmc-adc-100m-ref-svec.o
fmc-adc-100m-ref-spec-objs := fmc-adc-100m-ref-spec-core.o
fmc-adc-100m-ref-svec-objs := fmc-adc-100m-ref-svec-core.o
software/drivers/Makefile 0 → 100644
View file @ 4e6378bd
-include Makefile.specific
# include parent_common.mk for buildsystem's defines
#use absolute path for REPO_PARENT
REPO_PARENT ?= $(shell /bin/pwd)/../..
-include $(REPO_PARENT)/parent_common.mk
LINUX ?= /lib/modules/$(shell uname -r)/build
DRV_VERSION := $(shell git describe --always --dirty --long --tags)
all: modules
.PHONY: all modules clean help install modules_install
modules help modules_install:
$(MAKE) -C $(LINUX) M=$(shell pwd) DRV_VERSION=$(DRV_VERSION) $@
install:
$(MAKE) -C $(LINUX) M=$(shell pwd) DRV_VERSION=$(DRV_VERSION) modules_install
# be able to run the "clean" rule even if $(LINUX) is not valid
clean:
rm -rf *.o *~ .*.cmd *.ko *.mod.c .tmp_versions Module.symvers \
Module.markers modules.order
software/drivers/fmc-adc-100m-ref-spec-core.c 0 → 100644
View file @ 4e6378bd
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mod_devicetable.h>
enum ft_spec_dev_offsets {
FT_SPEC_FA100_MEM_START = 0x00002000,
FT_SPEC_FA100_MEM_END = 0x00003A00,
};
/* MFD devices */
enum spec_fpga_mfd_devs_enum {
FT_SPEC_MFD_FA100,
};
static struct resource ft_spec_fdt_res[] = {
{
.name = "fmc-adc-100m14b4ch-mem",
.flags = IORESOURCE_MEM,
.start = FT_SPEC_FA100_MEM_START,
.end = FT_SPEC_FA100_MEM_END,
}, {
.name = "fmc-adc-100m14b4ch-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = 0,
.end = 0,
},
};
static const struct mfd_cell ft_spec_mfd_devs[] = {
[FT_SPEC_MFD_FA100] = {
.name = "adc-100m-spec",
.platform_data = NULL,
.pdata_size = 0,
.num_resources = ARRAY_SIZE(ft_spec_fdt_res),
.resources = ft_spec_fdt_res,
},
};
static int ft_spec_probe(struct platform_device *pdev)
{
struct resource *rmem;
int irq;
rmem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!rmem) {
dev_err(&pdev->dev, "Missing memory resource\n");
return -EINVAL;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "Missing IRQ number\n");
return -EINVAL;
}
/*
* We know that this design uses the HTVIC IRQ controller.
* This IRQ controller has a linear mapping, so it is enough
* to give the first one as input
*/
return mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
ft_spec_mfd_devs,
ARRAY_SIZE(ft_spec_mfd_devs),
rmem, irq, NULL);
}
static int ft_spec_remove(struct platform_device *pdev)
{
mfd_remove_devices(&pdev->dev);
return 0;
}
/**
* List of supported platform
*/
enum wrtd_s150a_version {
FT_SPEC_VER = 0,
};
static const struct platform_device_id ft_spec_id_table[] = {
{
.name = "fmc-adc-100m-spec",
.driver_data = FT_SPEC_VER,
}, {
.name = "id:000010DC41444301",
.driver_data = FT_SPEC_VER,
}, {
.name = "id:000010dc41444301",
.driver_data = FT_SPEC_VER,
},
{},
};
static struct platform_driver ft_spec_driver = {
.driver = {
.name = "fmc-adc-100m-spec",
.owner = THIS_MODULE,
},
.id_table = ft_spec_id_table,
.probe = ft_spec_probe,
.remove = ft_spec_remove,
};
module_platform_driver(ft_spec_driver);
MODULE_AUTHOR("Federico Vaga <federico.vaga@cern.ch>");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
MODULE_DESCRIPTION("Driver for the FMC ADC 100M SPEC REF");
MODULE_DEVICE_TABLE(platform, ft_spec_id_table);
MODULE_SOFTDEP("pre: spec_fmc_carrier fmc-adc-100m14b4ch");
software/drivers/fmc-adc-100m-ref-svec-core.c 0 → 100644
View file @ 4e6378bd
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mod_devicetable.h>
enum ft_svec_dev_offsets {
FT_SVEC_FA100_S1_MEM_START = 0x00002000,
FT_SVEC_FA100_S1_MEM_END = 0x00003A00,
FT_SVEC_FA100_S2_MEM_START = 0x00004000,
FT_SVEC_FA100_S2_MEM_END = 0x00005A00,
};
/* MFD devices */
enum svec_fpga_mfd_devs_enum {
FT_SVEC_MFD_FA100_S1,
FT_SVEC_MFD_FA100_S2,
};
static struct resource ft_svec_fdt100_res_s1[] = {
{
.name = "fmc-adc-100m14b4ch-mem",
.flags = IORESOURCE_MEM,
.start = FT_SVEC_FA100_S1_MEM_START,
.end = FT_SVEC_FA100_S1_MEM_END,
}, {
.name = "fmc-adc-100m14b4ch-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = 0,
.end = 0,
},
};
static struct resource ft_svec_fdt100_res_s2[] = {
{
.name = "fmc-adc-100m14b4ch-mem",
.flags = IORESOURCE_MEM,
.start = FT_SVEC_FA100_S2_MEM_START,
.end = FT_SVEC_FA100_S2_MEM_END,
}, {
.name = "fmc-adc-100m14b4ch-irq",
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.start = 1,
.end = 1,
},
};
static const struct mfd_cell ft_svec_mfd_devs[] = {
[FT_SVEC_MFD_FA100_S1] = {
.name = "adc-100m-svec",
.platform_data = NULL,
.pdata_size = 0,
.num_resources = ARRAY_SIZE(ft_svec_fdt100_res_s1),
.resources = ft_svec_fdt100_res_s1,
},
[FT_SVEC_MFD_FA100_S2] = {
.name = "adc-100m-svec",
.platform_data = NULL,
.pdata_size = 0,
.num_resources = ARRAY_SIZE(ft_svec_fdt100_res_s2),
.resources = ft_svec_fdt100_res_s2,
},
};
static int ft_svec_probe(struct platform_device *pdev)
{
struct resource *rmem;
int irq;
rmem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!rmem) {
dev_err(&pdev->dev, "Missing memory resource\n");
return -EINVAL;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "Missing IRQ number\n");
return -EINVAL;
}
/*
* We know that this design uses the HTVIC IRQ controller.
* This IRQ controller has a linear mapping, so it is enough
* to give the first one as input
*/
return mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
ft_svec_mfd_devs,
ARRAY_SIZE(ft_svec_mfd_devs),
rmem, irq, NULL);
}
static int ft_svec_remove(struct platform_device *pdev)
{
mfd_remove_devices(&pdev->dev);
return 0;
}
static const struct platform_device_id ft_svec_id_table[] = {
{
.name = "fmc-adc-100m-svec",
.driver_data = 0,
}, {
.name = "id:000010DC41444302",
.driver_data = 0,
}, {
.name = "id:000010dc41444302",
.driver_data = 0,
},
{},
};
static struct platform_driver ft_svec_driver = {
.driver = {
.name = "fmc-adc-100m-svec",
.owner = THIS_MODULE,
},
.id_table = ft_svec_id_table,
.probe = ft_svec_probe,
.remove = ft_svec_remove,
};
module_platform_driver(ft_svec_driver);
MODULE_AUTHOR("Federico Vaga <federico.vaga@cern.ch>");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
MODULE_DESCRIPTION("Driver for the FMC ADC 100M SVEC REF");
MODULE_DEVICE_TABLE(platform, ft_svec_id_table);
MODULE_SOFTDEP("pre: svec_fmc_carrier fmc-adc-100m14b4ch");
software/include/hw/fmc_adc_100Ms_csr.h
View file @ 4e6378bd
#ifndef __CHEBY__FMC_ADC_100MS_CSR__H__ #ifndef __CHEBY__FMC_ADC_100MS_CSR__H__
#define __CHEBY__FMC_ADC_100MS_CSR__H__ #define __CHEBY__FMC_ADC_100MS_CSR__H__
#define FMC_ADC_100MS_CSR_SIZE 512
/* Control register */ /* Control register */
#define FMC_ADC_100MS_CSR_CTL 0x0UL #define FMC_ADC_100MS_CSR_CTL 0x0UL
...@@ -341,6 +342,9 @@ struct fmc_adc_100ms_csr { ...@@ -341,6 +342,9 @@ struct fmc_adc_100ms_csr {
/* [0x154]: REG (rw) Channel 4 trigger delay */ /* [0x154]: REG (rw) Channel 4 trigger delay */
uint32_t ch4_trig_dly; uint32_t ch4_trig_dly;
/* padding to: 85 words */
uint32_t __padding_4[42];
}; };
#endif /* __CHEBY__FMC_ADC_100MS_CSR__H__ */ #endif /* __CHEBY__FMC_ADC_100MS_CSR__H__ */
software/include/hw/fmc_adc_aux_trigin.h
View file @ 4e6378bd
#ifndef __CHEBY__AUX_TRIGIN__H__ #ifndef __CHEBY__AUX_TRIGIN__H__
#define __CHEBY__AUX_TRIGIN__H__ #define __CHEBY__AUX_TRIGIN__H__
#define AUX_TRIGIN_SIZE 20
/* Core version */ /* Core version */
#define AUX_TRIGIN_VERSION 0x0UL #define AUX_TRIGIN_VERSION 0x0UL
......
software/include/hw/fmc_adc_aux_trigout.h
View file @ 4e6378bd
#ifndef __CHEBY__AUX_TRIGOUT__H__ #ifndef __CHEBY__AUX_TRIGOUT__H__
#define __CHEBY__AUX_TRIGOUT__H__ #define __CHEBY__AUX_TRIGOUT__H__
#define AUX_TRIGOUT_SIZE 20
/* Status register */ /* Status register */
#define AUX_TRIGOUT_STATUS 0x0UL #define AUX_TRIGOUT_STATUS 0x0UL
......
software/include/hw/fmc_adc_mezzanine_mmap.h 0 → 100644
View file @ 4e6378bd
#ifndef __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__
#define __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__
#include "timetag_core_regs.h"
#include "wb_ds182x_regs.h"
#include "fmc_adc_100ms_csr.h"
#define FMC_ADC_MEZZANINE_MMAP_SIZE 8192
/* FMC ADC 100M CSR */
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 0x1000UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512
/* FMC ADC Embedded Interrupt Controller */
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 0x1500UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC_SIZE 16
/* Si570 control I2C master */
#define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 0x1600UL
#define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER_SIZE 256
/* DS18B20 OneWire master */
#define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 0x1700UL
#define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 16
/* Mezzanine SPI master (ADC control + DAC offsets) */
#define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 0x1800UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER_SIZE 32
/* Timetag Core */
#define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 0x1900UL
#define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE_SIZE 128
struct fmc_adc_mezzanine_mmap {
/* padding to: 1024 words */
uint32_t __padding_0[1024];
/* [0x1000]: SUBMAP FMC ADC 100M CSR */
struct fmc_adc_100ms_csr fmc_adc_100m_csr;
/* padding to: 1344 words */
uint32_t __padding_1[192];
/* [0x1500]: SUBMAP FMC ADC Embedded Interrupt Controller */
uint32_t fmc_adc_eic[4];
/* padding to: 1408 words */
uint32_t __padding_2[60];
/* [0x1600]: SUBMAP Si570 control I2C master */
uint32_t si570_i2c_master[64];
/* [0x1700]: SUBMAP DS18B20 OneWire master */
struct wb_ds182x_regs ds18b20_onewire_master;
/* padding to: 1536 words */
uint32_t __padding_3[60];
/* [0x1800]: SUBMAP Mezzanine SPI master (ADC control + DAC offsets) */
uint32_t fmc_spi_master[8];
/* padding to: 1600 words */
uint32_t __padding_4[56];
/* [0x1900]: SUBMAP Timetag Core */
struct timetag_core_regs timetag_core;
/* padding to: 1600 words */
uint32_t __padding_5[416];
};
#endif /* __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__ */
software/include/hw/spec_carrier_csr.h deleted 100644 → 0
View file @ d98dbd10
#ifndef __CHEBY__SPEC_CARRIER_CSR__H__
#define __CHEBY__SPEC_CARRIER_CSR__H__
#define SPEC_CARRIER_CSR_SIZE 16
/* Carrier type and PCB version */
#define SPEC_CARRIER_CSR_CARRIER 0x0UL
#define SPEC_CARRIER_CSR_CARRIER_PCB_REV_MASK 0xfUL
#define SPEC_CARRIER_CSR_CARRIER_PCB_REV_SHIFT 0
#define SPEC_CARRIER_CSR_CARRIER_RESERVED_MASK 0xfff0UL
#define SPEC_CARRIER_CSR_CARRIER_RESERVED_SHIFT 4
#define SPEC_CARRIER_CSR_CARRIER_TYPE_MASK 0xffff0000UL
#define SPEC_CARRIER_CSR_CARRIER_TYPE_SHIFT 16
/* Status */
#define SPEC_CARRIER_CSR_STAT 0x4UL
#define SPEC_CARRIER_CSR_STAT_FMC_PRES 0x1UL
#define SPEC_CARRIER_CSR_STAT_P2L_PLL_LCK 0x2UL
#define SPEC_CARRIER_CSR_STAT_SYS_PLL_LCK 0x4UL
#define SPEC_CARRIER_CSR_STAT_DDR3_CAL_DONE 0x8UL
/* Control */
#define SPEC_CARRIER_CSR_CTRL 0x8UL
#define SPEC_CARRIER_CSR_CTRL_LED_GREEN 0x1UL
#define SPEC_CARRIER_CSR_CTRL_LED_RED 0x2UL
/* Reset Register */
#define SPEC_CARRIER_CSR_RST 0xcUL
#define SPEC_CARRIER_CSR_RST_FMC0 0x1UL
struct spec_carrier_csr {
/* [0x0]: REG (ro) Carrier type and PCB version */
uint32_t carrier;
/* [0x4]: REG (ro) Status */
uint32_t stat;
/* [0x8]: REG (rw) Control */
uint32_t ctrl;
/* [0xc]: REG (wo) Reset Register */
uint32_t rst;
};
#endif /* __CHEBY__SPEC_CARRIER_CSR__H__ */
software/include/hw/spec_ref_fmc_adc_100Ms_mmap.h 0 → 100644
View file @ 4e6378bd
#ifndef __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__
#define __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__
#include "fmc_adc_mezzanine_mmap.h"
#define SPEC_REF_FMC_ADC_100M_MMAP_SIZE 24576
/* a ROM containing the application metadata */
#define SPEC_REF_FMC_ADC_100M_MMAP_METADATA 0x2000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
/* FMC ADC Mezzanine */
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE 0x4000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE_SIZE 8192
struct spec_ref_fmc_adc_100m_mmap {
/* padding to: 2048 words */
uint32_t __padding_0[2048];
/* [0x2000]: SUBMAP a ROM containing the application metadata */
uint32_t metadata[16];
/* padding to: 4096 words */
uint32_t __padding_1[2032];
/* [0x4000]: SUBMAP FMC ADC Mezzanine */
struct fmc_adc_mezzanine_mmap fmc_adc_mezzanine;
};
#endif /* __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__ */
software/include/hw/svec_ref_fmc_adc_100Ms_mmap.h 0 → 100644
View file @ 4e6378bd
#ifndef __CHEBY__SVEC_REF_FMC_ADC_100M_MMAP__H__
#define __CHEBY__SVEC_REF_FMC_ADC_100M_MMAP__H__
#include "fmc_adc_mezzanine_mmap.h"
#define SVEC_REF_FMC_ADC_100M_MMAP_SIZE 32768
/* a ROM containing the application metadata */
#define SVEC_REF_FMC_ADC_100M_MMAP_METADATA 0x2000UL
#define SVEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
/* FMC ADC Mezzanine slot 1 */
#define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE 0x4000UL
#define SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
/* FMC ADC Mezzanine slot 2 */
#define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE 0x6000UL
#define SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
struct svec_ref_fmc_adc_100m_mmap {
/* padding to: 2048 words */
uint32_t __padding_0[2048];
/* [0x2000]: SUBMAP a ROM containing the application metadata */
uint32_t metadata[16];
/* padding to: 4096 words */
uint32_t __padding_1[2032];
/* [0x4000]: SUBMAP FMC ADC Mezzanine slot 1 */
struct fmc_adc_mezzanine_mmap fmc1_adc_mezzanine;
/* [0x6000]: SUBMAP FMC ADC Mezzanine slot 2 */
struct fmc_adc_mezzanine_mmap fmc2_adc_mezzanine;
};
#endif /* __CHEBY__SVEC_REF_FMC_ADC_100M_MMAP__H__ */
software/include/hw/timetag_core_regs.h
View file @ 4e6378bd
#ifndef __CHEBY__TIMETAG_CORE_REGS__H__ #ifndef __CHEBY__TIMETAG_CORE_REGS__H__
#define __CHEBY__TIMETAG_CORE_REGS__H__ #define __CHEBY__TIMETAG_CORE_REGS__H__
#define TIMETAG_CORE_REGS_SIZE 128
/* Timetag seconds register (upper) */ /* Timetag seconds register (upper) */
#define TIMETAG_CORE_REGS_SECONDS_UPPER 0x0UL #define TIMETAG_CORE_REGS_SECONDS_UPPER 0x0UL
...@@ -133,6 +134,9 @@ struct timetag_core_regs { ...@@ -133,6 +134,9 @@ struct timetag_core_regs {
/* [0x44]: REG (ro) Acquisition end time-tag coarse time (system clock ticks 125MHz) register */ /* [0x44]: REG (ro) Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
uint32_t acq_end_tag_coarse; uint32_t acq_end_tag_coarse;
/* padding to: 17 words */
uint32_t __padding_0[14];
}; };
#endif /* __CHEBY__TIMETAG_CORE_REGS__H__ */ #endif /* __CHEBY__TIMETAG_CORE_REGS__H__ */
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