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FMC ADC 100M 14b 4cha - Gateware
Commit 51ef6665 authored by mcattin's avatar mcattin
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Wishbone from adc core to ddr now 64-bit data width. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@52 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 4d155222
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hdl/spec/ip_cores/_xmsgs/pn_parser.xmsgs
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......@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/tmp/_cg/wb_sync_fifo.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/tmp/_cg/wb_ddr_fifo.vhd&quot; into library work</arg>
</msg>
</messages>
......
hdl/spec/ip_cores/_xmsgs/xst.xmsgs
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hdl/spec/ip_cores/coregen.cgc
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hdl/spec/ip_cores/wb_ddr_fifo.asy 0 → 100644
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Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 wb_ddr_fifo
RECTANGLE Normal 32 32 544 768
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName din[63:0]
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName wr_en
PINATTR Polarity IN
LINE Normal 0 240 32 240
PIN 0 240 LEFT 36
PINATTR PinName rd_en
PINATTR Polarity IN
LINE Normal 0 336 32 336
PIN 0 336 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Normal 144 800 144 768
PIN 144 800 BOTTOM 36
PINATTR PinName rst
PINATTR Polarity IN
LINE Wide 576 80 544 80
PIN 576 80 RIGHT 36
PINATTR PinName dout[63:0]
PINATTR Polarity OUT
LINE Normal 576 208 544 208
PIN 576 208 RIGHT 36
PINATTR PinName full
PINATTR Polarity OUT
LINE Normal 576 432 544 432
PIN 576 432 RIGHT 36
PINATTR PinName empty
PINATTR Polarity OUT
LINE Normal 576 528 544 528
PIN 576 528 RIGHT 36
PINATTR PinName valid
PINATTR Polarity OUT
hdl/spec/ip_cores/wb_ddr_fifo.gise 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="wb_ddr_fifo.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="wb_ddr_fifo.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="wb_ddr_fifo.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="wb_ddr_fifo.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/spec/ip_cores/wb_ddr_fifo.ngc 0 → 100644
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hdl/spec/ip_cores/wb_ddr_fifo.sym 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="wb_ddr_fifo">
<symboltype>BLOCK</symboltype>
<timestamp>2011-3-28T13:14:27</timestamp>
<pin polarity="Input" x="0" y="80" name="din[63:0]" />
<pin polarity="Input" x="0" y="144" name="wr_en" />
<pin polarity="Input" x="0" y="240" name="rd_en" />
<pin polarity="Input" x="0" y="336" name="clk" />
<pin polarity="Input" x="144" y="800" name="rst" />
<pin polarity="Output" x="576" y="80" name="dout[63:0]" />
<pin polarity="Output" x="576" y="208" name="full" />
<pin polarity="Output" x="576" y="432" name="empty" />
<pin polarity="Output" x="576" y="528" name="valid" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">wb_ddr_fifo</text>
<rect width="512" x="32" y="32" height="736" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin din[63:0]" />
<line x2="32" y1="144" y2="144" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin wr_en" />
<line x2="32" y1="240" y2="240" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="240" type="pin rd_en" />
<line x2="32" y1="336" y2="336" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="336" type="pin clk" />
<line x2="144" y1="800" y2="768" x1="144" />
<attrtext style="alignment:BCENTER;fontsize:24;fontname:Arial" attrname="PinName" x="144" y="764" type="pin rst" />
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin dout[63:0]" />
<line x2="544" y1="208" y2="208" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="208" type="pin full" />
<line x2="544" y1="432" y2="432" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="432" type="pin empty" />
<line x2="544" y1="528" y2="528" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="528" type="pin valid" />
</graph>
</symbol>
hdl/spec/ip_cores/wb_ddr_fifo.vhd 0 → 100644
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file wb_ddr_fifo.vhd when simulating
-- the core, wb_ddr_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY wb_ddr_fifo IS
port (
clk: IN std_logic;
rst: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(63 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic);
END wb_ddr_fifo;
ARCHITECTURE wb_ddr_fifo_a OF wb_ddr_fifo IS
-- synthesis translate_off
component wrapped_wb_ddr_fifo
port (
clk: IN std_logic;
rst: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(63 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_wb_ddr_fifo use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 64,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 0,
c_implementation_type => 0,
c_family => "spartan6",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 64,
c_msgon_val => 1,
c_rd_depth => 1024,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 10,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 1,
c_rd_pntr_width => 10,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 10,
c_enable_rlocs => 0,
c_wr_pntr_width => 10,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 10,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 1021,
c_wr_depth => 1024,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 1022,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "1kx36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_wb_ddr_fifo
port map (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
valid => valid);
-- synthesis translate_on
END wb_ddr_fifo_a;
hdl/spec/ip_cores/wb_ddr_fifo.vho 0 → 100644
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component wb_ddr_fifo
port (
clk: IN std_logic;
rst: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(63 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of wb_ddr_fifo: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : wb_ddr_fifo
port map (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
valid => valid);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file wb_ddr_fifo.vhd when simulating
-- the core, wb_ddr_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
hdl/spec/ip_cores/wb_ddr_fifo.xco 0 → 100644
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##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Mon Mar 28 13:17:52 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=wb_ddr_fifo
CSET data_count=false
CSET data_count_width=10
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=1022
CSET full_threshold_negate_value=1021
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=64
CSET input_depth=1024
CSET output_data_width=64
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
# END Parameters
GENERATE
# CRC: af2e406b
hdl/spec/ip_cores/wb_ddr_fifo.xise 0 → 100644
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hdl/spec/ip_cores/wb_ddr_fifo_flist.txt 0 → 100644
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# Output products list for <wb_ddr_fifo>
_xmsgs/pn_parser.xmsgs
fifo_generator_readme.txt
fifo_generator_ug175.pdf
wb_ddr_fifo.asy
wb_ddr_fifo.gise
wb_ddr_fifo.ngc
wb_ddr_fifo.sym
wb_ddr_fifo.vhd
wb_ddr_fifo.vho
wb_ddr_fifo.xco
wb_ddr_fifo.xise
wb_ddr_fifo_flist.txt
wb_ddr_fifo_xmdf.tcl
hdl/spec/ip_cores/wb_ddr_fifo_xmdf.tcl 0 → 100644
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# The package naming convention is <core_name>_xmdf
package provide wb_ddr_fifo_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::wb_ddr_fifo_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::wb_ddr_fifo_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name wb_ddr_fifo
}
# ::wb_ddr_fifo_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::wb_ddr_fifo_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_fifo.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_fifo.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_fifo.sym
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_fifo.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_fifo.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_fifo.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path wb_ddr_fifo_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module wb_ddr_fifo
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
hdl/spec/ip_cores/wb_sync_fifo.ngc
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hdl/spec/ip_cores/wb_sync_fifo.sym
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="wb_sync_fifo">
<symboltype>BLOCK</symboltype>
<timestamp>2011-3-24T8:0:54</timestamp>
<timestamp>2011-3-24T14:5:53</timestamp>
<pin polarity="Input" x="0" y="80" name="din[63:0]" />
<pin polarity="Input" x="0" y="144" name="wr_en" />
<pin polarity="Input" x="0" y="176" name="wr_clk" />
......
hdl/spec/ip_cores/wb_sync_fifo.vhd
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......@@ -94,7 +94,7 @@ end component;
c_preload_latency => 1,
c_dout_width => 32,
c_msgon_val => 1,
c_rd_depth => 128,
c_rd_depth => 2048,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
......@@ -102,35 +102,35 @@ end component;
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 6,
c_data_count_width => 10,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 7,
c_rd_pntr_width => 11,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 7,
c_rd_data_count_width => 11,
c_enable_rlocs => 0,
c_wr_pntr_width => 6,
c_wr_pntr_width => 10,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 6,
c_wr_data_count_width => 10,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 60,
c_wr_depth => 64,
c_prog_full_thresh_negate_val => 1020,
c_wr_depth => 1024,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 61,
c_prog_full_thresh_assert_val => 1021,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x72",
c_prim_fifo_type => "1kx36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
......
hdl/spec/ip_cores/wb_sync_fifo.xco
View file @ 51ef6665
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Thu Mar 24 08:04:16 2011
# Date: Thu Mar 24 14:09:13 2011
#
##############################################################
#
......@@ -39,7 +39,7 @@ CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=wb_sync_fifo
CSET data_count=false
CSET data_count_width=6
CSET data_count_width=10
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
......@@ -49,14 +49,14 @@ CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=61
CSET full_threshold_negate_value=60
CSET full_threshold_assert_value=1021
CSET full_threshold_negate_value=1020
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=64
CSET input_depth=64
CSET input_depth=1024
CSET output_data_width=32
CSET output_depth=128
CSET output_depth=2048
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
......@@ -64,7 +64,7 @@ CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=7
CSET read_data_count_width=11
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
......@@ -78,7 +78,7 @@ CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=6
CSET write_data_count_width=10
# END Parameters
GENERATE
# CRC: 5cec2fb3
# CRC: d8399107
hdl/spec/ip_cores/wb_sync_fifo.xise
View file @ 51ef6665
......@@ -370,8 +370,8 @@
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-03-24T09:04:24" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6542611C029AA541E8A3F85A38DEDEAB" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-03-24T15:09:21" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6849DBD497E5F3287E0C28DE76BBDCB9" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......
hdl/spec/ise_project/_xmsgs/pn_parser.xmsgs
View file @ 51ef6665
......@@ -8,8 +8,5 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/rtl/ddr3_ctrl.vhd&quot; into library work</arg>
</msg>
</messages>
hdl/spec/ise_project/spec_fmc_adc_100Ms.gise
View file @ 51ef6665
......@@ -111,35 +111,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1299483117" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1299483117">
<transform xil_pn:end_ts="1301056430" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1301056430">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1299776202" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5336720412813903745" xil_pn:start_ts="1299776202">
<transform xil_pn:end_ts="1301056430" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5336720412813903745" xil_pn:start_ts="1301056430">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1299776202" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6573690209299584574" xil_pn:start_ts="1299776202">
<transform xil_pn:end_ts="1301056430" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6573690209299584574" xil_pn:start_ts="1301056430">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1299483117" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1299483117">
<transform xil_pn:end_ts="1301056430" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1301056430">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1299776202" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-972982594196377663" xil_pn:start_ts="1299776202">
<transform xil_pn:end_ts="1301056430" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-972982594196377663" xil_pn:start_ts="1301056430">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1299483117" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1299483117">
<transform xil_pn:end_ts="1301056430" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1301056430">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1299776202" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="3375361665759590988" xil_pn:start_ts="1299776202">
<transform xil_pn:end_ts="1301056430" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="3375361665759590988" xil_pn:start_ts="1301056430">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1300903400" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1300903183">
<transform xil_pn:end_ts="1301321285" xil_pn:in_ck="7436421871160300883" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1301321048">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -157,11 +157,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1300788652" xil_pn:in_ck="2162529744943951648" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4337831395208791850" xil_pn:start_ts="1300788652">
<transform xil_pn:end_ts="1301056667" xil_pn:in_ck="2162529744943951648" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4337831395208791850" xil_pn:start_ts="1301056667">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1300903428" xil_pn:in_ck="6806541686375937701" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300903400">
<transform xil_pn:end_ts="1301321316" xil_pn:in_ck="3312797925576817273" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1301321285">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -171,7 +171,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ngd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1300903791" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1300903428">
<transform xil_pn:end_ts="1301321711" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1301321316">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -185,7 +185,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_summary.xml"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1300904000" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1300903791">
<transform xil_pn:end_ts="1301321933" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1301321711">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -200,7 +200,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_pad.txt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1300904068" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1300904000">
<transform xil_pn:end_ts="1301322002" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1301321933">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -221,7 +221,7 @@
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1300874535" xil_pn:in_ck="1401670161614890390" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300874535">
<transform xil_pn:end_ts="1301043716" xil_pn:in_ck="1401670161614890390" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1301043715">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
......@@ -229,7 +229,7 @@
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1300904000" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1300903955">
<transform xil_pn:end_ts="1301321933" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1301321890">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/spec/ise_project/spec_fmc_adc_100Ms.xise
View file @ 51ef6665
......@@ -79,107 +79,112 @@
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/ddr_controller_bank3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<file xil_pn:name="../../../../GN4124_core/hdl/spec/ip_cores/fifo_32x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<file xil_pn:name="../../../../GN4124_core/hdl/spec/ip_cores/fifo_64x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../monostable/monostable_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<file xil_pn:name="../spec_top_fmc_adc_100Ms.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/adc_serdes.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/spec/ip_cores/fifo_32x512.ngc" xil_pn:type="FILE_NGC">
<file xil_pn:name="../rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/spec/ip_cores/fifo_64x512.ngc" xil_pn:type="FILE_NGC">
<file xil_pn:name="../../../../ext_pulse_sync/ext_pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../monostable/monostable_rtl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../wb_spi_master/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../wb_spi_master/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../spec_top_fmc_adc_100Ms.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../../../../wb_spi_master/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../wb_i2c_master/rtl/vhdl/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/adc_serdes.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../wb_i2c_master/rtl/vhdl/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../wb_i2c_master/rtl/vhdl/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../utils/utils_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../ext_pulse_sync/ext_pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/adc_sync_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/test_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../wb_spi_master/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/ddr_controller_bank3_64b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../wb_spi_master/spi_shift.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../wb_spi_master/spi_top.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../wb_i2c_master/rtl/vhdl/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../wb_i2c_master/rtl/vhdl/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../wb_i2c_master/rtl/vhdl/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../utils/utils_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/adc_sync_fifo.ngc" xil_pn:type="FILE_NGC">
<file xil_pn:name="../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3_64b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/wb_sync_fifo.ngc" xil_pn:type="FILE_NGC">
<file xil_pn:name="../ip_cores/wb_ddr_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
</files>
......
hdl/spec/rtl/fmc_adc_100Ms_core.vhd
View file @ 51ef6665
This diff is collapsed.
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 51ef6665
......@@ -270,20 +270,20 @@ architecture rtl of spec_top_fmc_adc_100Ms is
wb0_cyc_i : in std_logic;
wb0_stb_i : in std_logic;
wb0_we_i : in std_logic;
wb0_addr_i : in std_logic_vector(27 downto 0);
wb0_addr_i : in std_logic_vector(26 downto 0);
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_ack_o : out std_logic;
wb0_stall_o : out std_logic;
wb1_clk_i : in std_logic;
wb1_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
wb1_cyc_i : in std_logic;
wb1_stb_i : in std_logic;
wb1_we_i : in std_logic;
wb1_addr_i : in std_logic_vector(27 downto 0);
wb1_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb1_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
wb1_ack_o : out std_logic;
wb1_stall_o : out std_logic
);
......@@ -400,12 +400,11 @@ architecture rtl of spec_top_fmc_adc_100Ms is
-- DDR wishbone interface
wb_ddr_clk_i : in std_logic;
wb_ddr_adr_o : out std_logic_vector(31 downto 0);
wb_ddr_dat_o : out std_logic_vector(31 downto 0);
wb_ddr_sel_o : out std_logic_vector(3 downto 0);
wb_ddr_dat_o : out std_logic_vector(63 downto 0);
wb_ddr_sel_o : out std_logic_vector(7 downto 0);
wb_ddr_stb_o : out std_logic;
wb_ddr_we_o : out std_logic;
wb_ddr_cyc_o : out std_logic;
wb_ddr_dat_i : in std_logic_vector(31 downto 0);
wb_ddr_ack_i : in std_logic;
wb_ddr_stall_i : in std_logic;
......@@ -433,6 +432,17 @@ architecture rtl of spec_top_fmc_adc_100Ms is
);
end component fmc_adc_100Ms_core;
component test_dpram
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(9 downto 0);
dina : in std_logic_vector(31 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(9 downto 0);
doutb : out std_logic_vector(31 downto 0));
end component test_dpram;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
......@@ -521,21 +531,20 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal wb_adr_fmc_adc_core : std_logic_vector(4 downto 0);
-- GN4124 DMA to DDR wishbone bus
signal wb_dma_adr : std_logic_vector(31 downto 0);
signal wb_dma_dat_i : std_logic_vector((32*c_DMA_WB_SLAVES_NB)-1 downto 0);
signal wb_dma_dat_o : std_logic_vector(31 downto 0);
signal wb_dma_sel : std_logic_vector(3 downto 0);
signal wb_dma_cyc : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal wb_dma_stb : std_logic;
signal wb_dma_we : std_logic;
signal wb_dma_ack : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal wb_dma_stall : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal wb_dma_adr : std_logic_vector(31 downto 0);
signal wb_dma_dat_i : std_logic_vector((32*c_DMA_WB_SLAVES_NB)-1 downto 0);
signal wb_dma_dat_o : std_logic_vector(31 downto 0);
signal wb_dma_sel : std_logic_vector(3 downto 0);
signal wb_dma_cyc : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal wb_dma_stb : std_logic;
signal wb_dma_we : std_logic;
signal wb_dma_ack : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal wb_dma_stall : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
-- FMC ADC core to DDR wishbone bus
signal wb_ddr_adr : std_logic_vector(31 downto 0);
signal wb_ddr_dat_i : std_logic_vector((32*c_DMA_WB_SLAVES_NB)-1 downto 0);
signal wb_ddr_dat_o : std_logic_vector(31 downto 0);
signal wb_ddr_sel : std_logic_vector(3 downto 0);
signal wb_ddr_dat_o : std_logic_vector(63 downto 0);
signal wb_ddr_sel : std_logic_vector(7 downto 0);
signal wb_ddr_cyc : std_logic;
signal wb_ddr_stb : std_logic;
signal wb_ddr_we : std_logic;
......@@ -570,8 +579,11 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal ddr3_calib_done : std_logic;
-- SPI
signal spi_din_t : std_logic_vector(3 downto 0);
signal spi_ss_t : std_logic_vector(7 downto 0);
signal spi_din_t : std_logic_vector(3 downto 0);
signal spi_ss_t : std_logic_vector(7 downto 0);
-- Tests
signal test_dpram_we : std_logic;
begin
......@@ -849,22 +861,22 @@ begin
------------------------------------------------------------------------------
cmp_fmc_spi : wb_spi_master
port map (
wb_clk_i => sys_clk_125,
wb_rst_i => sys_rst,
wb_adr_i => wb_adr_fmc_spi,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_fmc_spi,
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_cyc_i => wb_cyc_fmc_spi,
wb_we_i => wb_we,
wb_ack_o => wb_ack_fmc_spi,
wb_err_o => open,
wb_int_o => open,
ss_pad_o => spi_ss_t,
sclk_pad_o => spi_sck_o,
mosi_pad_o => spi_dout_o,
miso_pad_i => spi_din_t(spi_din_t'left)
wb_clk_i => sys_clk_125,
wb_rst_i => sys_rst,
wb_adr_i => wb_adr_fmc_spi,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_fmc_spi,
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_cyc_i => wb_cyc_fmc_spi,
wb_we_i => wb_we,
wb_ack_o => wb_ack_fmc_spi,
wb_err_o => open,
wb_int_o => open,
ss_pad_o => spi_ss_t,
sclk_pad_o => spi_sck_o,
mosi_pad_o => spi_dout_o,
miso_pad_i => spi_din_t(spi_din_t'left)
);
-- 32-bit word to byte address
......@@ -947,14 +959,13 @@ begin
wb_csr_we_i => wb_we,
wb_csr_ack_o => wb_ack_fmc_adc_core,
wb_ddr_clk_i => sys_clk_250,
wb_ddr_clk_i => sys_clk_125,
wb_ddr_adr_o => wb_ddr_adr,
wb_ddr_dat_o => wb_ddr_dat_o,
wb_ddr_sel_o => wb_ddr_sel,
wb_ddr_stb_o => wb_ddr_stb,
wb_ddr_we_o => wb_ddr_we,
wb_ddr_cyc_o => wb_ddr_cyc,
wb_ddr_dat_i => wb_ddr_dat_i,
wb_ddr_ack_i => wb_ddr_ack,
wb_ddr_stall_i => wb_ddr_stall,
......@@ -992,9 +1003,13 @@ begin
------------------------------------------------------------------------------
cmp_ddr_ctrl : ddr3_ctrl
generic map(
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => g_SIMULATION,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP)
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => g_SIMULATION,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32)
port map (
clk_i => ddr_clk,
rst_n_i => sys_rst_n,
......@@ -1021,14 +1036,36 @@ begin
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
wb0_clk_i => sys_clk_250,
--wb0_clk_i => '0',
--wb0_sel_i => "0000",
--wb0_cyc_i => '0',
--wb0_stb_i => '0',
--wb0_we_i => '0',
--wb0_addr_i => X"0000000",
--wb0_data_i => X"00000000",
--wb0_data_o => open,
--wb0_ack_o => open,
--wb0_stall_o => open,
--wb1_clk_i => '0',
--wb1_sel_i => "0000",
--wb1_cyc_i => '0',
--wb1_stb_i => '0',
--wb1_we_i => '0',
--wb1_addr_i => X"0000000",
--wb1_data_i => X"00000000",
--wb1_data_o => open,
--wb1_ack_o => open,
--wb1_stall_o => open);
wb0_clk_i => sys_clk_125,
wb0_sel_i => wb_ddr_sel,
wb0_cyc_i => wb_ddr_cyc,
wb0_stb_i => wb_ddr_stb,
wb0_we_i => wb_ddr_we,
wb0_addr_i => wb_ddr_adr(27 downto 0),
wb0_addr_i => wb_ddr_adr(26 downto 0),
wb0_data_i => wb_ddr_dat_o,
wb0_data_o => wb_ddr_dat_i,
wb0_data_o => open,
wb0_ack_o => wb_ddr_ack,
wb0_stall_o => wb_ddr_stall,
......@@ -1043,6 +1080,48 @@ begin
wb1_ack_o => wb_dma_ack,
wb1_stall_o => wb_dma_stall);
--wb_ddr_stall <= '0';
--test_dpram_we <= wb_ddr_we and wb_ddr_stb and wb_ddr_cyc;
--p_test_dpram_wr_ack : process (sys_clk_250)
--begin
-- if rising_edge(sys_clk_250) then
-- if sys_rst_n = '0' then
-- wb_ddr_ack <= '0';
-- elsif wb_ddr_cyc = '1' and wb_ddr_stb = '1' then
-- wb_ddr_ack <= '1';
-- else
-- wb_ddr_ack <= '0';
-- end if;
-- end if;
--end process p_test_dpram_wr_ack;
--cmp_test_dpram : test_dpram
-- port map(
-- clka => sys_clk_250,
-- wea(0) => test_dpram_we, --: in std_logic_vector(0 downto 0);
-- addra => wb_ddr_adr(9 downto 0), --: in std_logic_vector(9 downto 0);
-- dina => wb_ddr_dat_o, --: in std_logic_vector(31 downto 0);
-- clkb => sys_clk_125,
-- addrb => wb_dma_adr(9 downto 0), --: in std_logic_vector(9 downto 0);
-- doutb => wb_dma_dat_i); --: out std_logic_vector(31 downto 0));
--p_test_dpram_rd_ack : process (sys_clk_125)
--begin
-- if rising_edge(sys_clk_125) then
-- if sys_rst_n = '0' then
-- wb_dma_ack <= '0';
-- elsif wb_dma_cyc = '1' and wb_dma_stb = '1' then
-- wb_dma_ack <= '1';
-- else
-- wb_dma_ack <= '0';
-- end if;
-- end if;
--end process p_test_dpram_rd_ack;
--wb_dma_stall <= '0';
------------------------------------------------------------------------------
-- Assign unused outputs
------------------------------------------------------------------------------
......
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ 51ef6665
......@@ -557,11 +557,11 @@ NET "DDR3_UDQS_N" IN_TERM = NONE;
# GN4124
NET "L_CLKp" TNM_NET = "l_clkp_grp";
TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 10 ns HIGH 50%;
TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 6.25 ns HIGH 50%;
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 10 ns HIGH 50%;
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 6.25 ns HIGH 50%;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 10 ns HIGH 50%;
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 6.25 ns HIGH 50%;
# System clock
......
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