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FMC ADC 100M 14b 4cha - Gateware
Commit 877b153c authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: overhaul of WB interconnect 

 - switch to pipelined
 - replace xwb_register_link with new xwb_register
 - enable pipelined mode for SDB ROM
parent 4c3d5acd
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Showing with 53 additions and 31 deletions
ddr3-sp6-core @ 33b31655
Subproject commit 94a664ed3906079bf5a645a4a0face78d03839b9 Subproject commit 33b31655be05192c6a0fbb4f3c2d96cf55b3abb6
general-cores @ 8706ae25
Subproject commit 5c3207c0ea2d6a0e83ab691817bd87b4a6bac896 Subproject commit 8706ae258ca99f2f4265683cae94fc5bf193a7d3
vme64x-core @ a31b46e3
Subproject commit a120e2262e1cb23fa611dddb7fa3727b520a125c Subproject commit a31b46e346e88b728458a6db1c3c973bbccefc7f
wr-cores @ 8ed042d8
Subproject commit b6dfc740f4fe23564972ffefcc1caee8ee820b2b Subproject commit 8ed042d82021206f5fda2081e98d358467fd15f2
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 877b153c
...@@ -378,7 +378,7 @@ begin ...@@ -378,7 +378,7 @@ begin
cmp_csr_wb_slave_adapter : wb_slave_adapter cmp_csr_wb_slave_adapter : wb_slave_adapter
generic map ( generic map (
g_master_use_struct => TRUE, g_master_use_struct => TRUE,
g_master_mode => CLASSIC, g_master_mode => PIPELINED,
g_master_granularity => WORD, g_master_granularity => WORD,
g_slave_use_struct => TRUE, g_slave_use_struct => TRUE,
g_slave_mode => g_WB_CSR_MODE, g_slave_mode => g_WB_CSR_MODE,
......
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 877b153c
...@@ -38,9 +38,10 @@ use work.timetag_core_pkg.all; ...@@ -38,9 +38,10 @@ use work.timetag_core_pkg.all;
entity fmc_adc_mezzanine is entity fmc_adc_mezzanine is
generic( generic (
g_MULTISHOT_RAM_SIZE : natural := 2048 g_MULTISHOT_RAM_SIZE : natural := 2048;
); g_WB_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_GRANULARITY : t_wishbone_address_granularity := BYTE);
port ( port (
-- Clock, reset -- Clock, reset
sys_clk_i : in std_logic; sys_clk_i : in std_logic;
...@@ -106,10 +107,9 @@ entity fmc_adc_mezzanine is ...@@ -106,10 +107,9 @@ entity fmc_adc_mezzanine is
wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit
wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds
wr_tm_cycles_i : in std_logic_vector(27 downto 0); -- WR timecode 8ns ticks wr_tm_cycles_i : in std_logic_vector(27 downto 0); -- WR timecode 8ns ticks
wr_enable_i : in std_logic -- enable white rabbit features on mezzanine wr_enable_i : in std_logic); -- enable white rabbit features on mezzanine
);
end fmc_adc_mezzanine;
end fmc_adc_mezzanine;
architecture rtl of fmc_adc_mezzanine is architecture rtl of fmc_adc_mezzanine is
...@@ -212,6 +212,9 @@ architecture rtl of fmc_adc_mezzanine is ...@@ -212,6 +212,9 @@ architecture rtl of fmc_adc_mezzanine is
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal wb_csr_out : t_wishbone_slave_in;
signal wb_csr_in : t_wishbone_slave_out;
-- Mezzanine system I2C for EEPROM -- Mezzanine system I2C for EEPROM
signal sys_scl_in : std_logic; signal sys_scl_in : std_logic;
signal sys_scl_out : std_logic; signal sys_scl_out : std_logic;
...@@ -256,15 +259,36 @@ begin ...@@ -256,15 +259,36 @@ begin
-- Main wishbone crossbar for mezzanine -- Main wishbone crossbar for mezzanine
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Additional register to help timing cmp_fmc_wb_slave_adapter_in : wb_slave_adapter
cmp_xwb_reg : xwb_register_link generic map (
port map( g_master_use_struct => TRUE,
g_master_mode => PIPELINED,
g_master_granularity => BYTE,
g_slave_use_struct => TRUE,
g_slave_mode => g_WB_MODE,
g_slave_granularity => g_WB_GRANULARITY)
port map (
clk_sys_i => sys_clk_i, clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
slave_i => wb_csr_slave_i, slave_i => wb_csr_slave_i,
slave_o => wb_csr_slave_o, slave_o => wb_csr_slave_o,
master_i => cnx_master_in(c_WB_MASTER), master_i => wb_csr_in,
master_o => cnx_master_out(c_WB_MASTER)); master_o => wb_csr_out);
-- Additional register to help timing
cmp_xwb_register : xwb_register
generic map (
g_WB_MODE => PIPELINED,
-- Do not register the return path (ACK/STALL).
-- See xwb_register for more details.
g_FULL_REG => FALSE)
port map (
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
slave_i => wb_csr_out,
slave_o => wb_csr_in,
master_i => cnx_master_in(c_WB_MASTER),
master_o => cnx_master_out(c_WB_MASTER));
cmp_sdb_crossbar : xwb_sdb_crossbar cmp_sdb_crossbar : xwb_sdb_crossbar
generic map ( generic map (
...@@ -273,6 +297,7 @@ begin ...@@ -273,6 +297,7 @@ begin
g_registered => TRUE, g_registered => TRUE,
g_wraparound => TRUE, g_wraparound => TRUE,
g_layout => c_INTERCONNECT_LAYOUT, g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_wb_mode => PIPELINED,
g_sdb_addr => c_SDB_ADDRESS) g_sdb_addr => c_SDB_ADDRESS)
port map ( port map (
clk_sys_i => sys_clk_i, clk_sys_i => sys_clk_i,
...@@ -288,7 +313,7 @@ begin ...@@ -288,7 +313,7 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc_sys_i2c : xwb_i2c_master cmp_fmc_sys_i2c : xwb_i2c_master
generic map( generic map(
g_interface_mode => CLASSIC, g_interface_mode => PIPELINED,
g_address_granularity => BYTE g_address_granularity => BYTE
) )
port map ( port map (
...@@ -321,7 +346,7 @@ begin ...@@ -321,7 +346,7 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc_spi : xwb_spi cmp_fmc_spi : xwb_spi
generic map( generic map(
g_interface_mode => CLASSIC, g_interface_mode => PIPELINED,
g_address_granularity => BYTE g_address_granularity => BYTE
) )
port map ( port map (
...@@ -365,7 +390,7 @@ begin ...@@ -365,7 +390,7 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc_i2c : xwb_i2c_master cmp_fmc_i2c : xwb_i2c_master
generic map( generic map(
g_interface_mode => CLASSIC, g_interface_mode => PIPELINED,
g_address_granularity => BYTE g_address_granularity => BYTE
) )
port map ( port map (
...@@ -400,6 +425,8 @@ begin ...@@ -400,6 +425,8 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
generic map ( generic map (
g_WB_CSR_MODE => PIPELINED,
g_WB_CSR_GRANULARITY => BYTE,
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE
) )
port map( port map(
...@@ -452,7 +479,7 @@ begin ...@@ -452,7 +479,7 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc_onewire : xwb_onewire_master cmp_fmc_onewire : xwb_onewire_master
generic map( generic map(
g_interface_mode => CLASSIC, g_interface_mode => PIPELINED,
g_address_granularity => BYTE, g_address_granularity => BYTE,
g_num_ports => 1, g_num_ports => 1,
g_ow_btp_normal => "5.0", g_ow_btp_normal => "5.0",
......
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ 877b153c
...@@ -43,9 +43,10 @@ package fmc_adc_mezzanine_pkg is ...@@ -43,9 +43,10 @@ package fmc_adc_mezzanine_pkg is
-- Components declaration -- Components declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
component fmc_adc_mezzanine component fmc_adc_mezzanine
generic( generic (
g_MULTISHOT_RAM_SIZE : natural := 2048 g_MULTISHOT_RAM_SIZE : natural := 2048;
); g_WB_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_GRANULARITY : t_wishbone_address_granularity := BYTE);
port ( port (
-- Clock, reset -- Clock, reset
sys_clk_i : in std_logic; sys_clk_i : in std_logic;
...@@ -111,14 +112,8 @@ package fmc_adc_mezzanine_pkg is ...@@ -111,14 +112,8 @@ package fmc_adc_mezzanine_pkg is
wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit
wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds
wr_tm_cycles_i : in std_logic_vector(27 downto 0); -- WR timecode 8ns ticks wr_tm_cycles_i : in std_logic_vector(27 downto 0); -- WR timecode 8ns ticks
wr_enable_i : in std_logic -- enable white rabbit features on mezzanine wr_enable_i : in std_logic); -- enable white rabbit features on mezzanine
);
end component fmc_adc_mezzanine;
end fmc_adc_mezzanine_pkg;
package body fmc_adc_mezzanine_pkg is
end component fmc_adc_mezzanine;
end fmc_adc_mezzanine_pkg; end fmc_adc_mezzanine_pkg;
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