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FMC ADC 100M 14b 4cha - Gateware
Commit 9a8eb2b9 authored by mcattin's avatar mcattin
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Bug fix in top (ddr ctrl wb addr width), if decimation is 0 -> no decimation 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@48 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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Showing with 31 additions and 181 deletions
hdl/spec/ip_cores/coregen.cgc
View file @ 9a8eb2b9
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hdl/spec/ip_cores/coregen.log
View file @ 9a8eb2b9
......@@ -4,42 +4,16 @@ Opening project file
/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/coregen.cgp.
Project, 'coregen', initialised from file
'/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/coregen.cgp'.
Customize and GenerateCustomizing IP...
Recustomize and Generate (Under Original Project Settings)Customizing IP...
Release 12.2 - Xilinx CORE Generator IP GUI Launcher M.63c (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Initializing IP model...
Finished initialising IP model.
Finished Customizing.
Generating IP...
Cancelled Customization.
Recustomize and Generate (Under Original Project Settings)Customizing IP...
Release 12.2 - Xilinx CORE Generator IP GUI Launcher M.63c (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Initializing IP model...
Finished initialising IP model.
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Partition Report
XST: Design Summary
Generating Implementation files.
Generating ISE symbol file...
Generating NGC file.
Finished Generation Stage.
Generating IP instantiation template...
Generating the VHDL instantiation template.
Finished generating IP instantiation template.
Generating metadata file...
Finished generating metadata file.
Generating metadata file...
Finished generating metadata file.
Generating ISE file...
Finished ISE file generation.
Generating FLIST file...
Finished FLIST file generation.
Preparing output directory...
Finished preparing output directory.
Launching readme viewer...
Launched readme viewer.
Moving files to output directory...
Finished moving files to output directory
Saved options for project 'coregen'.
Cancelled Customization.
Closed project file.
hdl/spec/ise_project/_xmsgs/pn_parser.xmsgs
View file @ 9a8eb2b9
......@@ -8,5 +8,8 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/rtl/ddr3_ctrl.vhd&quot; into library work</arg>
</msg>
</messages>
hdl/spec/ise_project/iseconfig/spec_top.xreport
View file @ 9a8eb2b9
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2011-03-21T12:53:12</DateModified>
<DateModified>2011-03-21T17:12:40</DateModified>
<ModuleName>spec_top_fmc_adc_100Ms</ModuleName>
<SummaryTimeStamp>2011-03-09T11:19:20</SummaryTimeStamp>
<SavedFilePath>/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ise_project/iseconfig/spec_top.xreport</SavedFilePath>
......
hdl/spec/ise_project/spec_fmc_adc_100Ms.gise
View file @ 9a8eb2b9
......@@ -137,7 +137,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1300706177" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1300705954">
<transform xil_pn:end_ts="1300723000" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1300722755">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -159,7 +159,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1300706204" xil_pn:in_ck="6806541686375937701" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300706177">
<transform xil_pn:end_ts="1300723032" xil_pn:in_ck="6806541686375937701" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300723000">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -169,7 +169,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ngd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1300706615" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1300706204">
<transform xil_pn:end_ts="1300723455" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1300723032">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -183,7 +183,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_summary.xml"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1300706876" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1300706615">
<transform xil_pn:end_ts="1300723870" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1300723455">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -198,7 +198,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_pad.txt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1300706942" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1300706876">
<transform xil_pn:end_ts="1300723940" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1300723870">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -216,9 +216,10 @@
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1300706876" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1300706835">
<transform xil_pn:end_ts="1300723870" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1300723828">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/spec/rtl/fmc_adc_100Ms_core.vhd
View file @ 9a8eb2b9
......@@ -375,8 +375,8 @@ begin
-- Resets
------------------------------------------------------------------------------
sys_rst <= not(sys_rst_n_i);
fs_rst_n <= sys_rst_n_i;
fs_rst <= not(sys_rst_n_i);
fs_rst_n <= sys_rst_n_i and locked_out;
fs_rst <= not(fs_rst_n);
------------------------------------------------------------------------------
-- ADC data clock buffer
......@@ -667,11 +667,13 @@ begin
p_deci_cnt : process (fs_clk)
begin
if fs_rst_n = '0' then
decim_cnt <= (others => '0');
decim_cnt <= to_unsigned(1, decim_cnt'length);
decim_en <= '0';
elsif rising_edge(fs_clk) then
if decim_cnt = to_unsigned(0, decim_cnt'length) then
decim_cnt <= unsigned(decim_factor) - 1;
if decim_factor /= X"0000" then
decim_cnt <= unsigned(decim_factor) - 1;
end if;
decim_en <= '1';
else
decim_cnt <= decim_cnt - 1;
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 9a8eb2b9
......@@ -270,7 +270,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
wb0_cyc_i : in std_logic;
wb0_stb_i : in std_logic;
wb0_we_i : in std_logic;
wb0_addr_i : in std_logic_vector(29 downto 0);
wb0_addr_i : in std_logic_vector(27 downto 0);
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_ack_o : out std_logic;
......@@ -281,7 +281,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
wb1_cyc_i : in std_logic;
wb1_stb_i : in std_logic;
wb1_we_i : in std_logic;
wb1_addr_i : in std_logic_vector(29 downto 0);
wb1_addr_i : in std_logic_vector(27 downto 0);
wb1_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb1_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb1_ack_o : out std_logic;
......@@ -530,7 +530,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal wb_dma_we : std_logic;
signal wb_dma_ack : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal wb_dma_stall : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal wb_dma_adr_ddr : std_logic_vector(29 downto 0);
-- FMC ADC core to DDR wishbone bus
signal wb_ddr_adr : std_logic_vector(31 downto 0);
......
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