hdl: Preliminary support for logical OR of internal threshold triggers

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

hdl: Preliminary support for logical OR of internal threshold triggers
Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
9e14427f · Tim Mottram · Dimitris Lampridis · b98da95d · 9e14427f · 9e14427f
Commit 9e14427f authored Oct 27, 2017 by Tim Mottram Committed by Dimitris Lampridis Jan 22, 2018
7 changed files
--- a/doc/manual/fmc_adc_100Ms_csr.tex
+++ b/doc/manual/fmc_adc_100Ms_csr.tex
--- a/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
--- a/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
--- a/hdl/adc/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ../rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created        : Thu Jun 16 17:04:12 2016
+-- Created        : Mon Jan 22 15:24:47 2018
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
@@ -63,13 +63,10 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
      ctl_trig_led_o                           : std_logic;
      ctl_acq_led_o                            : std_logic;
      trig_cfg_hw_trig_sel_o                   : std_logic_vector(1 downto 0);
-      trig_cfg_hw_trig_pol_o                   : std_logic;
+      trig_cfg_ex_hw_trig_pol_o                : std_logic;
      trig_cfg_hw_trig_en_o                    : std_logic;
      trig_cfg_sw_trig_en_o                    : std_logic;
-      trig_cfg_int_trig_sel_o                  : std_logic_vector(1 downto 0);
      trig_cfg_int_trig_test_en_o              : std_logic;
-      trig_cfg_int_trig_thres_filt_o           : std_logic_vector(7 downto 0);
-      trig_cfg_int_trig_thres_o                : std_logic_vector(15 downto 0);
      trig_dly_o                               : std_logic_vector(31 downto 0);
      sw_trig_o                                : std_logic_vector(31 downto 0);
      sw_trig_wr_o                             : std_logic;
@@ -81,18 +78,38 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
      ch1_gain_val_o                           : std_logic_vector(15 downto 0);
      ch1_offset_val_o                         : std_logic_vector(15 downto 0);
      ch1_sat_val_o                            : std_logic_vector(14 downto 0);
+      ch1_trig_trig_en_o                       : std_logic;
+      ch1_trig_trig_pol_o                      : std_logic;
+      ch1_trig_reserved_o                      : std_logic_vector(5 downto 0);
+      ch1_trig_int_trig_thres_filt_o           : std_logic_vector(7 downto 0);
+      ch1_trig_int_trig_thres_o                : std_logic_vector(15 downto 0);
      ch2_ctl_ssr_o                            : std_logic_vector(6 downto 0);
      ch2_gain_val_o                           : std_logic_vector(15 downto 0);
      ch2_offset_val_o                         : std_logic_vector(15 downto 0);
      ch2_sat_val_o                            : std_logic_vector(14 downto 0);
+      ch2_trig_trig_en_o                       : std_logic;
+      ch2_trig_trig_pol_o                      : std_logic;
+      ch2_trig_reserved_o                      : std_logic_vector(5 downto 0);
+      ch2_trig_int_trig_thres_filt_o           : std_logic_vector(7 downto 0);
+      ch2_trig_int_trig_thres_o                : std_logic_vector(15 downto 0);
      ch3_ctl_ssr_o                            : std_logic_vector(6 downto 0);
      ch3_gain_val_o                           : std_logic_vector(15 downto 0);
      ch3_offset_val_o                         : std_logic_vector(15 downto 0);
      ch3_sat_val_o                            : std_logic_vector(14 downto 0);
+      ch3_trig_trig_en_o                       : std_logic;
+      ch3_trig_trig_pol_o                      : std_logic;
+      ch3_trig_reserved_o                      : std_logic_vector(5 downto 0);
+      ch3_trig_int_trig_thres_filt_o           : std_logic_vector(7 downto 0);
+      ch3_trig_int_trig_thres_o                : std_logic_vector(15 downto 0);
      ch4_ctl_ssr_o                            : std_logic_vector(6 downto 0);
      ch4_gain_val_o                           : std_logic_vector(15 downto 0);
      ch4_offset_val_o                         : std_logic_vector(15 downto 0);
      ch4_sat_val_o                            : std_logic_vector(14 downto 0);
+      ch4_trig_trig_en_o                       : std_logic;
+      ch4_trig_trig_pol_o                      : std_logic;
+      ch4_trig_reserved_o                      : std_logic_vector(5 downto 0);
+      ch4_trig_int_trig_thres_filt_o           : std_logic_vector(7 downto 0);
+      ch4_trig_int_trig_thres_o                : std_logic_vector(15 downto 0);
      end record;
    constant c_fmc_adc_100ms_csr_out_registers_init_value: t_fmc_adc_100ms_csr_out_registers := (
@@ -105,13 +122,10 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
      ctl_trig_led_o => '0',
      ctl_acq_led_o => '0',
      trig_cfg_hw_trig_sel_o => (others => '0'),
-      trig_cfg_hw_trig_pol_o => '0',
+      trig_cfg_ex_hw_trig_pol_o => '0',
      trig_cfg_hw_trig_en_o => '0',
      trig_cfg_sw_trig_en_o => '0',
-      trig_cfg_int_trig_sel_o => (others => '0'),
      trig_cfg_int_trig_test_en_o => '0',
-      trig_cfg_int_trig_thres_filt_o => (others => '0'),
-      trig_cfg_int_trig_thres_o => (others => '0'),
      trig_dly_o => (others => '0'),
      sw_trig_o => (others => '0'),
      sw_trig_wr_o => '0',
@@ -123,18 +137,38 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
      ch1_gain_val_o => (others => '0'),
      ch1_offset_val_o => (others => '0'),
      ch1_sat_val_o => (others => '0'),
+      ch1_trig_trig_en_o => '0',
+      ch1_trig_trig_pol_o => '0',
+      ch1_trig_reserved_o => (others => '0'),
+      ch1_trig_int_trig_thres_filt_o => (others => '0'),
+      ch1_trig_int_trig_thres_o => (others => '0'),
      ch2_ctl_ssr_o => (others => '0'),
      ch2_gain_val_o => (others => '0'),
      ch2_offset_val_o => (others => '0'),
      ch2_sat_val_o => (others => '0'),
+      ch2_trig_trig_en_o => '0',
+      ch2_trig_trig_pol_o => '0',
+      ch2_trig_reserved_o => (others => '0'),
+      ch2_trig_int_trig_thres_filt_o => (others => '0'),
+      ch2_trig_int_trig_thres_o => (others => '0'),
      ch3_ctl_ssr_o => (others => '0'),
      ch3_gain_val_o => (others => '0'),
      ch3_offset_val_o => (others => '0'),
      ch3_sat_val_o => (others => '0'),
+      ch3_trig_trig_en_o => '0',
+      ch3_trig_trig_pol_o => '0',
+      ch3_trig_reserved_o => (others => '0'),
+      ch3_trig_int_trig_thres_filt_o => (others => '0'),
+      ch3_trig_int_trig_thres_o => (others => '0'),
      ch4_ctl_ssr_o => (others => '0'),
      ch4_gain_val_o => (others => '0'),
      ch4_offset_val_o => (others => '0'),
-      ch4_sat_val_o => (others => '0')
+      ch4_sat_val_o => (others => '0'),
+      ch4_trig_trig_en_o => '0',
+      ch4_trig_trig_pol_o => '0',
+      ch4_trig_reserved_o => (others => '0'),
+      ch4_trig_int_trig_thres_filt_o => (others => '0'),
+      ch4_trig_int_trig_thres_o => (others => '0')
      );
    function "or" (left, right: t_fmc_adc_100ms_csr_in_registers) return t_fmc_adc_100ms_csr_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
@@ -154,10 +188,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
 variable tmp: std_logic_vector(x'length-1 downto 0);
 begin
 for i in 0 to x'length-1 loop
-if(x(i) = 'X' or x(i) = 'U') then
+if x(i) = '1' then
-tmp(i):= '0';
+tmp(i):= '1';
 else
-tmp(i):=x(i);
+tmp(i):= '0';
 end if; 
 end loop; 
 return tmp;

--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
@@ -151,9 +151,9 @@ peripheral {
    };
    field {
-      name = "Hardware trigger polarity";
+      name = "External Hardware trigger polarity";
      description = "0: positive edge/slope\n1: negative edge/slope";
-      prefix = "hw_trig_pol";
+      prefix = "ex_hw_trig_pol";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
@@ -180,17 +180,6 @@ peripheral {
      clock = "fs_clk_i";
    };
-    field {
-      name = "Channel selection for internal trigger";
-      description = "00: channel 1\n01: channel 2\n10: channel 3\n11: channel 4";
-      prefix = "int_trig_sel";
-      type = SLV;
-      size = 2;
-      access_bus = READ_WRITE;
-      access_dev = READ_ONLY;
-      clock = "fs_clk_i";
-    };
    field {
      name = "Enable internal trigger test mode";
      description = "Test mode:\n  ch1 = Channel 1 input(analogue)\n ch2 = Channel input over threshold (digital)\n  ch3 = Channel input over threshold filtered (digital)\n  ch4 = Trigger (digital)";
@@ -201,27 +190,18 @@ peripheral {
      clock = "fs_clk_i";
    };
+--[[
    field {
-      name = "Internal trigger threshold glitch filter";
+      name = "Reserved";
-      description = "Configures the internal trigger threshold glitch filter length.";
+      description = "Ignore on read, write with 0's";
-      prefix = "int_trig_thres_filt";
+      prefix = "reserved";
-      type = SLV;
-      size = 8;
-      access_bus = READ_WRITE;
-      access_dev = READ_ONLY;
-      clock = "fs_clk_i";
-    };
-    field {
-      name = "Threshold for internal trigger";
-      description = "Treated as binary two's complement and compared to raw ADC data.";
-      prefix = "int_trig_thres";
      type = SLV;
-      size = 16;
+      size = 26;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      clock = "fs_clk_i";
    };
+]]
  };
  reg {
@@ -521,6 +501,59 @@ peripheral {
 ]]
  };
+  reg {
+    name = "Channel 1 trigger configuration register";
+    prefix = "ch1_trig";
+    field {
+      name = "Trigger enable for channel 1";
+      discription = "0: disable\n1: enable, Active only if internal trigger in Trigger Configuration is enabled";
+      prefix = "trig_en";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+    field {
+      name = "Trigger polarity";
+      description = "0: positive edge/slope\n1: negative edge/slope";
+      prefix = "trig_pol";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 6;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+    field {
+      name = "Internal trigger threshold glitch filter for Channel 1";
+      description = "Configures the internal trigger threshold glitch filter length.";
+      prefix = "int_trig_thres_filt";
+      type = SLV;
+      size = 8;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+    field {
+      name = "Threshold for Channel 1 internal trigger";
+      description = "Treated as binary two's complement and compared to raw ADC data.";
+      prefix = "int_trig_thres";
+      type = SLV;
+      size = 16;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+  };
  reg {
    name = "Channel 2 control register";
    prefix = "ch2_ctl";
@@ -652,6 +685,59 @@ peripheral {
 ]]
  };
+  reg {
+    name = "Channel 2 trigger configuration register";
+    prefix = "ch2_trig";
+    field {
+      name = "Trigger enable for channel 2";
+      discription = "0: disable\n1: enable, Active only if internal trigger in Trigger Configuration is enabled";
+      prefix = "trig_en";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+    field {
+      name = "Trigger polarity";
+      description = "0: positive edge/slope\n1: negative edge/slope";
+      prefix = "trig_pol";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 6;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+    field {
+      name = "Internal trigger threshold glitch filter for Channel 2";
+      description = "Configures the internal trigger threshold glitch filter length.";
+      prefix = "int_trig_thres_filt";
+      type = SLV;
+      size = 8;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+    field {
+      name = "Threshold for Channel 2 internal trigger";
+      description = "Treated as binary two's complement and compared to raw ADC data.";
+      prefix = "int_trig_thres";
+      type = SLV;
+      size = 16;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+  };
  reg {
    name = "Channel 3 control register";
    prefix = "ch3_ctl";
@@ -783,6 +869,59 @@ peripheral {
 ]]
  };
+  reg {
+    name = "Channel 3 trigger configuration register";
+    prefix = "ch3_trig";
+    field {
+      name = "Trigger enable for channel 3";
+      discription = "0: disable\n1: enable, Active only if internal trigger in Trigger Configuration is enabled";
+      prefix = "trig_en";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+    field {
+      name = "Trigger polarity";
+      description = "0: positive edge/slope\n1: negative edge/slope";
+      prefix = "trig_pol";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 6;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+    field {
+      name = "Internal trigger threshold glitch filter for Channel 3";
+      description = "Configures the internal trigger threshold glitch filter length.";
+      prefix = "int_trig_thres_filt";
+      type = SLV;
+      size = 8;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+    field {
+      name = "Threshold for Channel 3 internal trigger";
+      description = "Treated as binary two's complement and compared to raw ADC data.";
+      prefix = "int_trig_thres";
+      type = SLV;
+      size = 16;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+  };
  reg {
    name = "Channel 4 control register";
    prefix = "ch4_ctl";
@@ -914,6 +1053,60 @@ peripheral {
 ]]
  };
+  reg {
+    name = "Channel 4 trigger configuration register";
+    prefix = "ch4_trig";
+    field {
+      name = "Trigger enable for channel 4";
+      discription = "0: disable\n1: enable, Active only if internal trigger in Trigger Configuration is enabled";
+      prefix = "trig_en";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+    field {
+      name = "trigger polarity";
+      description = "0: positive edge/slope\n1: negative edge/slope";
+      prefix = "trig_pol";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 6;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+    field {
+      name = "Internal trigger threshold glitch filter for Channel 4";
+      description = "Configures the internal trigger threshold glitch filter length.";
+      prefix = "int_trig_thres_filt";
+      type = SLV;
+      size = 8;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+    field {
+      name = "Threshold for Channel 4 internal trigger";
+      description = "Treated as binary two's complement and compared to raw ADC data.";
+      prefix = "int_trig_thres";
+      type = SLV;
+      size = 16;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+  };
  reg {
    name = "Multi-shot sample depth register";
    prefix = "multi_depth";