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FMC ADC 100M 14b 4cha - Gateware
Commit af4ed69a authored by Dimitris Lampridis's avatar Dimitris Lampridis
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syn: update build options and constraints

parent bf0d09de
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Showing with 15 additions and 10 deletions
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
View file @ af4ed69a
......@@ -380,6 +380,14 @@ NET "adc_si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "adc_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# IOBs
#----------------------------------------
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE;
#===============================================================================
# Timing Constraints
#===============================================================================
......@@ -498,4 +506,3 @@ TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DAT
TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "adc_sync_reg" 10ns DATAPATHONLY;
hdl/syn/spec_ref_design_wr/syn_extra_steps.tcl
View file @ af4ed69a
......@@ -18,8 +18,8 @@ xilinx::project open $project_file
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
#xilinx::project set "Pack I/O Registers into IOBs" "Yes"
#xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
......
hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
View file @ af4ed69a
......@@ -581,11 +581,9 @@ NET "adc_one_wire_b[*]" IOSTANDARD = "LVCMOS25";
# IOBs
#----------------------------------------
# Force PPS output to always be placed as IOB register
INST "cmp_xwrc_board_svec/*/wrapped_ppsgen/pps_out_o" IOB = FORCE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE;
#===============================================================================
# Timing Constraints
......
hdl/syn/svec_ref_design_wr/syn_extra_steps.tcl
View file @ af4ed69a
......@@ -18,8 +18,8 @@ xilinx::project open $project_file
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
#xilinx::project set "Pack I/O Registers into IOBs" "Yes"
#xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
......
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