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FMC ADC 100M 14b 4cha - Gateware
Commit bb2303fc authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[doc] revert to generating html from cheby

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doc/manual/fmc_adc_100Ms_csr.adoc deleted 100644 → 0
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doc/manual/fmc_adc_alt_trigin.adoc deleted 100644 → 0
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== Memory map summary
FMC ADC alt trigger out registers
|===
|HW address | Type | Name | HDL name
|0x00
|REG
|version
|version
|0x04
|REG
|ctrl
|ctrl
|0x08
|REG
|seconds
|seconds
|0x10
|REG
|cycles
|cycles
|===
== Registers description
=== version
[horizontal]
HDL name:: version
address:: 0x0
block offset:: 0x0
access mode:: ro
Core version
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| version[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| version[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| version[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| version[7:0]
|===
=== ctrl
[horizontal]
HDL name:: ctrl
address:: 0x4
block offset:: 0x4
access mode:: rw
Control register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
| -
| -
| -
| -
| -
| -
| -
s| enable
|===
enable:: Enable trigger, cleared when triggered
=== seconds
[horizontal]
HDL name:: seconds
address:: 0x8
block offset:: 0x8
access mode:: rw
Time (seconds) to trigger
[cols="8*^"]
|===
| 63
| 62
| 61
| 60
| 59
| 58
| 57
| 56
8+s| seconds[63:56]
| 55
| 54
| 53
| 52
| 51
| 50
| 49
| 48
8+s| seconds[55:48]
| 47
| 46
| 45
| 44
| 43
| 42
| 41
| 40
8+s| seconds[47:40]
| 39
| 38
| 37
| 36
| 35
| 34
| 33
| 32
8+s| seconds[39:32]
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| seconds[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| seconds[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| seconds[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| seconds[7:0]
|===
=== cycles
[horizontal]
HDL name:: cycles
address:: 0x10
block offset:: 0x10
access mode:: rw
Time (cycles) to trigger
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| cycles[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| cycles[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| cycles[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| cycles[7:0]
|===
doc/manual/fmc_adc_alt_trigout.adoc deleted 100644 → 0
View file @ 5a05ec75
== Memory map summary
FMC ADC alt trigger out registers
|===
|HW address | Type | Name | HDL name
|0x00
|REG
|status
|status
|0x08
|REG
|ts_mask_sec
|ts_mask_sec
|0x10
|REG
|ts_cycles
|ts_cycles
|===
== Registers description
=== status
[horizontal]
HDL name:: status
address:: 0x0
block offset:: 0x0
access mode:: ro
Status register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
s| ts_present
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
| -
| -
| -
| -
| -
s| wr_valid
s| wr_link
s| wr_enable
|===
wr_enable:: Set when WR is enabled
wr_link:: WR link status
wr_valid:: Set when WR time is valid
ts_present:: Set when the timestamp fifo is not empty
=== ts_mask_sec
[horizontal]
HDL name:: ts_mask_sec
address:: 0x8
block offset:: 0x8
access mode:: ro
Time (seconds) of the last event
[cols="8*^"]
|===
| 63
| 62
| 61
| 60
| 59
| 58
| 57
| 56
| -
| -
| -
| -
| -
| -
| -
s| ext_mask
| 55
| 54
| 53
| 52
| 51
| 50
| 49
| 48
| -
| -
| -
| -
s| ch4_mask
s| ch3_mask
s| ch2_mask
s| ch1_mask
| 47
| 46
| 45
| 44
| 43
| 42
| 41
| 40
| -
| -
| -
| -
| -
| -
| -
| -
| 39
| 38
| 37
| 36
| 35
| 34
| 33
| 32
8+s| ts_sec[39:32]
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| ts_sec[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| ts_sec[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| ts_sec[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| ts_sec[7:0]
|===
ts_sec:: Seconds part of the timestamp
ch1_mask:: Set if channel 1 triggered
ch2_mask:: Set if channel 2 triggered
ch3_mask:: Set if channel 3 triggered
ch4_mask:: Set if channel 4 triggered
ext_mask:: Set if external trigger
=== ts_cycles
[horizontal]
HDL name:: ts_cycles
address:: 0x10
block offset:: 0x10
access mode:: ro
Cycles part of timestamp fifo.
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
4+s| cycles[27:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| cycles[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| cycles[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| cycles[7:0]
|===
cycles:: Cycles
doc/manual/timetag_core_regs.adoc deleted 100644 → 0
View file @ 5a05ec75
This diff is collapsed.
hdl/rtl/Makefile
View file @ bb2303fc
......@@ -13,6 +13,6 @@ $(TARGETS): %.vhd : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@
@cheby -i $< \
--doc=md --gen-doc=$(DOC)/$(@:.vhd=.adoc) \
--gen-doc=$(DOC)/$(@:.vhd=.html) \
--gen-consts=$(SIM)/$(@:.vhd=.v) \
--gen-c=$(SW)/$(@:.vhd=.h)
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