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FMC ADC 100M 14b 4cha - Gateware
Commit d1059605 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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sim: fix fmc_adc_mezzanine simulation

parent c70ccee6
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Showing with 5 additions and 4 deletions
hdl/testbench/fmc_adc_mezzanine/Manifest.py
View file @ d1059605
...@@ -12,7 +12,7 @@ fetchto = "../../ip_cores" ...@@ -12,7 +12,7 @@ fetchto = "../../ip_cores"
include_dirs = [ include_dirs = [
"../include", "../include",
fetchto + "/general-cores/sim/", fetchto + "/general-cores/sim/",
fetchto + "/general-cores/modules/wishbone/wb_spi/" fetchto + "/general-cores/modules/wishbone/wb_spi/",
] ]
files = [ files = [
...@@ -27,5 +27,3 @@ modules = { ...@@ -27,5 +27,3 @@ modules = {
"git://ohwr.org/hdl-core-lib/general-cores.git", "git://ohwr.org/hdl-core-lib/general-cores.git",
], ],
} }
ctrls = [ "bank3_64b_32b" ]
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @ d1059605
...@@ -53,6 +53,7 @@ module main; ...@@ -53,6 +53,7 @@ module main;
.trig_irq_o (), .trig_irq_o (),
.acq_end_irq_o (), .acq_end_irq_o (),
.eic_irq_o (), .eic_irq_o (),
.acq_cfg_ok_o (),
.ext_trigger_p_i (ext_trig), .ext_trigger_p_i (ext_trig),
.ext_trigger_n_i (~ext_trig), .ext_trigger_n_i (~ext_trig),
.adc_dco_p_i (adc0_dco), .adc_dco_p_i (adc0_dco),
...@@ -156,13 +157,15 @@ module main; ...@@ -156,13 +157,15 @@ module main;
initial begin initial begin
CBusAccessor acc; CWishboneAccessor acc;
uint64_t val, expected; uint64_t val, expected;
$timeformat (-6, 3, "us", 10); $timeformat (-6, 3, "us", 10);
acc = Host.get_accessor(); acc = Host.get_accessor();
acc.set_mode(PIPELINED);
#1us; #1us;
expected = 'h5344422d; expected = 'h5344422d;
......
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