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FMC ADC 100M 14b 4cha - Gateware
Commit e46239ae authored by mcattin's avatar mcattin
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Updated DDR core. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@124 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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hdl/spec/syn/spec_fmc_adc_100Ms.xise
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hdl/spec/syn/spec_top_fmc_adc_100Ms.par
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hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
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hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
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hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
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......@@ -11,46 +11,46 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Jul 6 11:47:41 2012
Mapped Date : Tue Jul 10 18:00:09 2012
Design Summary
--------------
Number of errors: 0
Number of warnings: 4
Number of warnings: 8
Slice Logic Utilization:
Number of Slice Registers: 6,833 out of 54,576 12%
Number used as Flip Flops: 6,833
Number of Slice Registers: 6,824 out of 54,576 12%
Number used as Flip Flops: 6,824
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,319 out of 27,288 19%
Number used as logic: 4,913 out of 27,288 18%
Number using O6 output only: 3,084
Number of Slice LUTs: 5,386 out of 27,288 19%
Number used as logic: 4,924 out of 27,288 18%
Number using O6 output only: 3,103
Number using O5 output only: 279
Number using O5 and O6: 1,550
Number using O5 and O6: 1,542
Number used as ROM: 0
Number used as Memory: 3 out of 6,408 1%
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 3
Number using O6 output only: 3
Number used as Shift Register: 2
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 403
Number with same-slice register load: 392
Number used exclusively as route-thrus: 460
Number with same-slice register load: 449
Number with same-slice carry load: 11
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,467 out of 6,822 36%
Number of occupied Slices: 2,496 out of 6,822 36%
Nummber of MUXCYs used: 1,424 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,755
Number with an unused Flip Flop: 1,761 out of 7,755 22%
Number with an unused LUT: 2,436 out of 7,755 31%
Number of fully used LUT-FF pairs: 3,558 out of 7,755 45%
Number of unique control sets: 262
Number of LUT Flip Flop pairs used: 7,727
Number with an unused Flip Flop: 1,807 out of 7,727 23%
Number with an unused LUT: 2,341 out of 7,727 30%
Number of fully used LUT-FF pairs: 3,579 out of 7,727 46%
Number of unique control sets: 261
Number of slice register sites lost
to control set restrictions: 700 out of 54,576 1%
to control set restrictions: 686 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -71,9 +71,9 @@ Specific Feature Utilization:
Number of BUFIO2FB/BUFIO2FB_2CLKs: 2 out of 32 6%
Number used as BUFIO2FBs: 2
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 7 out of 16 43%
Number used as BUFGs: 7
Number used as BUFGMUX: 0
Number of BUFG/BUFGMUXs: 6 out of 16 37%
Number used as BUFGs: 5
Number used as BUFGMUX: 1
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 38 out of 376 10%
Number used as ILOGIC2s: 0
......@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.75
Average Fanout of Non-Clock Nets: 3.76
Peak Memory Usage: 409 MB
Total REAL time to MAP completion: 4 mins 35 secs
Total CPU time to MAP completion (all processors): 4 mins 38 secs
Peak Memory Usage: 411 MB
Total REAL time to MAP completion: 4 mins 33 secs
Total CPU time to MAP completion (all processors): 4 mins 36 secs
Table of Contents
-----------------
......@@ -133,6 +133,22 @@ WARNING:MapLib:701 - Signal L_CLKn connected to top level port L_CLKn has been
removed.
WARNING:MapLib:701 - Signal DDR3_ZIO connected to top level port DDR3_ZIO has
been removed.
WARNING:MapLib:41 - All members of TNM group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl_memc3_inf
rastructure_inst_clk0_bufg_in" have been optimized out of the design.
WARNING:MapLib:41 - All members of TNM group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl_memc3_inf
rastructure_inst_clk0_bufg_in_0" have been optimized out of the design.
WARNING:MapLib:50 - The period specification
"TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl_memc3_
infrastructure_inst_clk0_bufg_in" has been discarded because the group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl_memc3_inf
rastructure_inst_clk0_bufg_in" has been optimized away.
WARNING:MapLib:50 - The period specification
"TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl_memc3_
infrastructure_inst_clk0_bufg_in_0" has been discarded because the group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_bank3_64b_32b_cmp_ddr3_ctrl_memc3_inf
rastructure_inst_clk0_bufg_in_0" has been optimized away.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
......@@ -148,8 +164,8 @@ INFO:LIT:243 - Logical network
astructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 9 more times for the following
(max. 5 shown):
N637,
N639,
N640,
N642,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
......@@ -170,9 +186,9 @@ INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
99 block(s) removed
101 block(s) removed
8 block(s) optimized away
71 signal(s) removed
74 signal(s) removed
Section 5 - Removed Logic
-------------------------
......@@ -195,6 +211,15 @@ tructure_inst/rst0_sync_r<24>" is loadless and has been removed.
tructure_inst/rst0_sync_r_24" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/clk0_bufg" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/U_BUFG_CLK0" (CKBUF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/clk0_bufg_in" is loadless and has been removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r<23>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
......@@ -338,11 +363,17 @@ tructure_inst/rst0_sync_r<0>" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst0_sync_r_0" (FF) removed.
*The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/c3_async_rst
" is loadless and has been removed.
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst_tmp" is loadless and has been removed.
* Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/rst_tmp1" (ROM) removed.
* The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/syn_clk0_powerup_pll_locked" is loadless and has been removed.
* Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infras
tructure_inst/syn_clk0_powerup_pll_locked" (FF) removed.
Loadless block "cmp_clk_250_buf" (CKBUF) removed.
The signal "sys_clk_250_buf" is loadless and has been removed.
Loadless block
......
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